Lines Matching +full:pipe +full:- +full:grf
1 // SPDX-License-Identifier: GPL-2.0
3 * Rockchip PIPE USB3.0 PCIE SATA Combo Phy driver
8 #include <dt-bindings/phy/phy.h>
146 temp = readl(priv->mmio + reg); in rockchip_combphy_updatel()
148 writel(temp, priv->mmio + reg); in rockchip_combphy_updatel()
156 tmp = en ? reg->enable : reg->disable; in rockchip_combphy_param_write()
157 mask = GENMASK(reg->bitend, reg->bitstart); in rockchip_combphy_param_write()
158 val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT); in rockchip_combphy_param_write()
160 return regmap_write(base, reg->offset, val); in rockchip_combphy_param_write()
165 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; in rockchip_combphy_is_ready()
168 mask = GENMASK(cfg->pipe_phy_status.bitend, in rockchip_combphy_is_ready()
169 cfg->pipe_phy_status.bitstart); in rockchip_combphy_is_ready()
171 regmap_read(priv->phy_grf, cfg->pipe_phy_status.offset, &val); in rockchip_combphy_is_ready()
172 val = (val & mask) >> cfg->pipe_phy_status.bitstart; in rockchip_combphy_is_ready()
180 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; in rockchip_combphy_init()
184 ret = clk_bulk_prepare_enable(priv->num_clks, priv->clks); in rockchip_combphy_init()
186 dev_err(priv->dev, "failed to enable clks\n"); in rockchip_combphy_init()
190 switch (priv->type) { in rockchip_combphy_init()
196 if (priv->cfg->combphy_cfg) in rockchip_combphy_init()
197 ret = priv->cfg->combphy_cfg(priv); in rockchip_combphy_init()
200 dev_err(priv->dev, "incompatible PHY type\n"); in rockchip_combphy_init()
201 ret = -EINVAL; in rockchip_combphy_init()
206 dev_err(priv->dev, "failed to init phy for phy type %x\n", priv->type); in rockchip_combphy_init()
210 ret = reset_control_deassert(priv->phy_rst); in rockchip_combphy_init()
214 if (priv->type == PHY_TYPE_USB3) { in rockchip_combphy_init()
217 val == cfg->pipe_phy_status.enable, in rockchip_combphy_init()
220 dev_warn(priv->dev, "wait phy status ready timeout\n"); in rockchip_combphy_init()
226 clk_bulk_disable_unprepare(priv->num_clks, priv->clks); in rockchip_combphy_init()
235 clk_bulk_disable_unprepare(priv->num_clks, priv->clks); in rockchip_combphy_exit()
236 reset_control_assert(priv->phy_rst); in rockchip_combphy_exit()
251 if (args->args_count != 1) { in rockchip_combphy_xlate()
253 return ERR_PTR(-EINVAL); in rockchip_combphy_xlate()
256 if (priv->type != PHY_NONE && priv->type != args->args[0]) in rockchip_combphy_xlate()
258 args->args[0], priv->type); in rockchip_combphy_xlate()
260 priv->type = args->args[0]; in rockchip_combphy_xlate()
262 return priv->phy; in rockchip_combphy_xlate()
269 priv->num_clks = devm_clk_bulk_get_all(dev, &priv->clks); in rockchip_combphy_parse_dt()
270 if (priv->num_clks < 1) in rockchip_combphy_parse_dt()
271 return -EINVAL; in rockchip_combphy_parse_dt()
273 priv->refclk = NULL; in rockchip_combphy_parse_dt()
274 for (i = 0; i < priv->num_clks; i++) { in rockchip_combphy_parse_dt()
275 if (!strncmp(priv->clks[i].id, "ref", 3)) { in rockchip_combphy_parse_dt()
276 priv->refclk = priv->clks[i].clk; in rockchip_combphy_parse_dt()
281 if (!priv->refclk) { in rockchip_combphy_parse_dt()
283 return -EINVAL; in rockchip_combphy_parse_dt()
286 priv->pipe_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,pipe-grf"); in rockchip_combphy_parse_dt()
287 if (IS_ERR(priv->pipe_grf)) { in rockchip_combphy_parse_dt()
288 dev_err(dev, "failed to find peri_ctrl pipe-grf regmap\n"); in rockchip_combphy_parse_dt()
289 return PTR_ERR(priv->pipe_grf); in rockchip_combphy_parse_dt()
292 priv->phy_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,pipe-phy-grf"); in rockchip_combphy_parse_dt()
293 if (IS_ERR(priv->phy_grf)) { in rockchip_combphy_parse_dt()
294 dev_err(dev, "failed to find peri_ctrl pipe-phy-grf regmap\n"); in rockchip_combphy_parse_dt()
295 return PTR_ERR(priv->phy_grf); in rockchip_combphy_parse_dt()
298 priv->enable_ssc = device_property_present(dev, "rockchip,enable-ssc"); in rockchip_combphy_parse_dt()
300 priv->ext_refclk = device_property_present(dev, "rockchip,ext-refclk"); in rockchip_combphy_parse_dt()
302 priv->phy_rst = devm_reset_control_array_get_exclusive(dev); in rockchip_combphy_parse_dt()
303 if (IS_ERR(priv->phy_rst)) in rockchip_combphy_parse_dt()
304 return dev_err_probe(dev, PTR_ERR(priv->phy_rst), "failed to get phy reset\n"); in rockchip_combphy_parse_dt()
312 struct device *dev = &pdev->dev; in rockchip_combphy_probe()
321 return -EINVAL; in rockchip_combphy_probe()
326 return -ENOMEM; in rockchip_combphy_probe()
328 priv->mmio = devm_platform_get_and_ioremap_resource(pdev, 0, &res); in rockchip_combphy_probe()
329 if (IS_ERR(priv->mmio)) { in rockchip_combphy_probe()
330 ret = PTR_ERR(priv->mmio); in rockchip_combphy_probe()
334 priv->dev = dev; in rockchip_combphy_probe()
335 priv->type = PHY_NONE; in rockchip_combphy_probe()
336 priv->cfg = phy_cfg; in rockchip_combphy_probe()
342 ret = reset_control_assert(priv->phy_rst); in rockchip_combphy_probe()
348 priv->phy = devm_phy_create(dev, NULL, &rochchip_combphy_ops); in rockchip_combphy_probe()
349 if (IS_ERR(priv->phy)) { in rockchip_combphy_probe()
351 return PTR_ERR(priv->phy); in rockchip_combphy_probe()
355 phy_set_drvdata(priv->phy, priv); in rockchip_combphy_probe()
364 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; in rk3568_combphy_cfg()
368 switch (priv->type) { in rk3568_combphy_cfg()
375 rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true); in rk3568_combphy_cfg()
376 rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true); in rk3568_combphy_cfg()
377 rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_pcie, true); in rk3568_combphy_cfg()
378 rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_pcie, true); in rk3568_combphy_cfg()
388 val = readl(priv->mmio + PHYREG15); in rk3568_combphy_cfg()
390 writel(val, priv->mmio + PHYREG15); in rk3568_combphy_cfg()
398 writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12); in rk3568_combphy_cfg()
405 writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18); in rk3568_combphy_cfg()
406 writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11); in rk3568_combphy_cfg()
408 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_usb, true); in rk3568_combphy_cfg()
409 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); in rk3568_combphy_cfg()
410 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); in rk3568_combphy_cfg()
411 rockchip_combphy_param_write(priv->phy_grf, &cfg->usb_mode_set, true); in rk3568_combphy_cfg()
416 val = readl(priv->mmio + PHYREG15); in rk3568_combphy_cfg()
418 writel(val, priv->mmio + PHYREG15); in rk3568_combphy_cfg()
425 writel(val, priv->mmio + PHYREG7); in rk3568_combphy_cfg()
427 rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_sata, true); in rk3568_combphy_cfg()
428 rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_sata, true); in rk3568_combphy_cfg()
429 rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_sata, true); in rk3568_combphy_cfg()
430 rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_sata, true); in rk3568_combphy_cfg()
431 rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true); in rk3568_combphy_cfg()
435 rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true); in rk3568_combphy_cfg()
436 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true); in rk3568_combphy_cfg()
437 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true); in rk3568_combphy_cfg()
438 rockchip_combphy_param_write(priv->phy_grf, &cfg->sgmii_mode_set, true); in rk3568_combphy_cfg()
442 rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true); in rk3568_combphy_cfg()
443 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true); in rk3568_combphy_cfg()
444 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_rate_sel, true); in rk3568_combphy_cfg()
445 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true); in rk3568_combphy_cfg()
446 rockchip_combphy_param_write(priv->phy_grf, &cfg->qsgmii_mode_set, true); in rk3568_combphy_cfg()
450 dev_err(priv->dev, "incompatible PHY type\n"); in rk3568_combphy_cfg()
451 return -EINVAL; in rk3568_combphy_cfg()
454 rate = clk_get_rate(priv->refclk); in rk3568_combphy_cfg()
458 if (priv->type == PHY_TYPE_USB3 || priv->type == PHY_TYPE_SATA) { in rk3568_combphy_cfg()
464 writel(PHYREG16_SSC_CNT_VALUE, priv->mmio + PHYREG16); in rk3568_combphy_cfg()
469 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_25m, true); in rk3568_combphy_cfg()
473 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); in rk3568_combphy_cfg()
474 if (priv->type == PHY_TYPE_PCIE) { in rk3568_combphy_cfg()
481 writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12); in rk3568_combphy_cfg()
487 writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18); in rk3568_combphy_cfg()
488 writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11); in rk3568_combphy_cfg()
489 } else if (priv->type == PHY_TYPE_SATA) { in rk3568_combphy_cfg()
498 dev_err(priv->dev, "unsupported rate: %lu\n", rate); in rk3568_combphy_cfg()
499 return -EINVAL; in rk3568_combphy_cfg()
502 if (priv->ext_refclk) { in rk3568_combphy_cfg()
503 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true); in rk3568_combphy_cfg()
504 if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) { in rk3568_combphy_cfg()
509 val = readl(priv->mmio + PHYREG14); in rk3568_combphy_cfg()
511 writel(val, priv->mmio + PHYREG14); in rk3568_combphy_cfg()
515 if (priv->enable_ssc) { in rk3568_combphy_cfg()
516 val = readl(priv->mmio + PHYREG8); in rk3568_combphy_cfg()
518 writel(val, priv->mmio + PHYREG8); in rk3568_combphy_cfg()
525 /* pipe-phy-grf */
552 /* pipe-grf */
564 .compatible = "rockchip,rk3568-naneng-combphy",
574 .name = "rockchip-naneng-combphy",