19 #define RG_PE1_PIPE_REG				0x02c
23 #define RG_P0_TO_P1_WIDTH			0x100
24 #define RG_PE1_H_LCDDS_REG			0x49c
25 #define RG_PE1_H_LCDDS_PCW			GENMASK(30, 0)
27 #define RG_PE1_FRC_H_XTAL_REG			0x400
31 #define RG_PE1_FRC_PHY_REG			0x000
35 #define RG_PE1_H_PLL_REG			0x490
43 #define RG_PE1_H_PLL_FBKSEL_REG			0x4bc
46 #define	RG_PE1_H_LCDDS_SSC_PRD_REG		0x4a4
47 #define RG_PE1_H_LCDDS_SSC_PRD			GENMASK(15, 0)
49 #define RG_PE1_H_LCDDS_SSC_DELTA_REG		0x4a8
50 #define RG_PE1_H_LCDDS_SSC_DELTA		GENMASK(11, 0)
53 #define RG_PE1_LCDDS_CLK_PH_INV_REG		0x4a0
56 #define RG_PE1_H_PLL_BR_REG			0x4ac
59 #define	RG_PE1_MSTCKDIV_REG			0x414
107 	mt7621_phy_rmw(phy, RG_PE1_PIPE_REG, 0, RG_PE1_PIPE_RST);  in mt7621_bypass_pipe_rst()
108 	mt7621_phy_rmw(phy, RG_PE1_PIPE_REG, 0, RG_PE1_PIPE_CMD_FRC);  in mt7621_bypass_pipe_rst()
112 			       0, RG_PE1_PIPE_RST);  in mt7621_bypass_pipe_rst()
114 			       0, RG_PE1_PIPE_CMD_FRC);  in mt7621_bypass_pipe_rst()
132 		       FIELD_PREP(RG_PE1_H_XTAL_TYPE, 0x00));  in mt7621_set_phy_for_ssc()
146 			       FIELD_PREP(RG_PE1_H_PLL_PREDIV, 0x01));  in mt7621_set_phy_for_ssc()
151 			       FIELD_PREP(RG_PE1_H_PLL_PREDIV, 0x00));  in mt7621_set_phy_for_ssc()
156 			       FIELD_PREP(RG_PE1_H_PLL_FBKSEL, 0x01));  in mt7621_set_phy_for_ssc()
161 			       FIELD_PREP(RG_PE1_H_LCDDS_SSC_PRD, 0x00));  in mt7621_set_phy_for_ssc()
166 			       FIELD_PREP(RG_PE1_H_LCDDS_SSC_PRD, 0x18d));  in mt7621_set_phy_for_ssc()
172 			       FIELD_PREP(RG_PE1_H_LCDDS_SSC_DELTA, 0x4a) |  in mt7621_set_phy_for_ssc()
173 			       FIELD_PREP(RG_PE1_H_LCDDS_SSC_DELTA1, 0x4a));  in mt7621_set_phy_for_ssc()
178 			       FIELD_PREP(RG_PE1_H_PLL_PREDIV, 0x00));  in mt7621_set_phy_for_ssc()
191 		       FIELD_PREP(RG_PE1_H_PLL_BC, 0x02) |  in mt7621_set_phy_for_ssc()
192 		       FIELD_PREP(RG_PE1_H_PLL_BP, 0x06) |  in mt7621_set_phy_for_ssc()
193 		       FIELD_PREP(RG_PE1_H_PLL_IR, 0x02) |  in mt7621_set_phy_for_ssc()
194 		       FIELD_PREP(RG_PE1_H_PLL_IC, 0x01) |  in mt7621_set_phy_for_ssc()
195 		       FIELD_PREP(RG_PE1_PLL_DIVEN, 0x02));  in mt7621_set_phy_for_ssc()
198 		       FIELD_PREP(RG_PE1_H_PLL_BR, 0x00));  in mt7621_set_phy_for_ssc()
204 			       FIELD_PREP(RG_PE1_MSTCKDIV, 0x01) |  in mt7621_set_phy_for_ssc()
208 	return 0;  in mt7621_set_phy_for_ssc()
234 	return 0;  in mt7621_pci_phy_power_on()
250 	return 0;  in mt7621_pci_phy_power_off()
255 	return 0;  in mt7621_pci_phy_exit()
271 	if (WARN_ON(args->args[0] >= MAX_PHYS))  in mt7621_pcie_phy_of_xlate()
274 	mt7621_phy->has_dual_port = args->args[0];  in mt7621_pcie_phy_of_xlate()
276 	dev_dbg(dev, "PHY for 0x%px (dual port = %d)\n",  in mt7621_pcie_phy_of_xlate()
291 	.max_register = 0x700,
312 	phy->port_base = devm_platform_ioremap_resource(pdev, 0);  in mt7621_pci_phy_probe()