Lines Matching +full:- +full:phy
1 // SPDX-License-Identifier: GPL-2.0+
3 * Mediatek MT7621 PCI PHY Driver
7 #include <dt-bindings/phy/phy.h>
14 #include <linux/phy/phy.h>
67 * struct mt7621_pci_phy - Mt7621 Pcie PHY core
70 * @phy: pointer to the kernel PHY device
73 * @has_dual_port: if the phy has dual ports.
80 struct phy *phy; member
87 static inline void mt7621_phy_rmw(struct mt7621_pci_phy *phy, in mt7621_phy_rmw() argument
99 regmap_read(phy->regmap, reg, &val); in mt7621_phy_rmw()
102 regmap_write(phy->regmap, reg, val); in mt7621_phy_rmw()
105 static void mt7621_bypass_pipe_rst(struct mt7621_pci_phy *phy) in mt7621_bypass_pipe_rst() argument
107 mt7621_phy_rmw(phy, RG_PE1_PIPE_REG, 0, RG_PE1_PIPE_RST); in mt7621_bypass_pipe_rst()
108 mt7621_phy_rmw(phy, RG_PE1_PIPE_REG, 0, RG_PE1_PIPE_CMD_FRC); in mt7621_bypass_pipe_rst()
110 if (phy->has_dual_port) { in mt7621_bypass_pipe_rst()
111 mt7621_phy_rmw(phy, RG_PE1_PIPE_REG + RG_P0_TO_P1_WIDTH, in mt7621_bypass_pipe_rst()
113 mt7621_phy_rmw(phy, RG_PE1_PIPE_REG + RG_P0_TO_P1_WIDTH, in mt7621_bypass_pipe_rst()
118 static int mt7621_set_phy_for_ssc(struct mt7621_pci_phy *phy) in mt7621_set_phy_for_ssc() argument
120 struct device *dev = phy->dev; in mt7621_set_phy_for_ssc()
123 clk_rate = clk_get_rate(phy->sys_clk); in mt7621_set_phy_for_ssc()
125 return -EINVAL; in mt7621_set_phy_for_ssc()
127 /* Set PCIe Port PHY to disable SSC */ in mt7621_set_phy_for_ssc()
129 mt7621_phy_rmw(phy, RG_PE1_FRC_H_XTAL_REG, in mt7621_set_phy_for_ssc()
135 mt7621_phy_rmw(phy, RG_PE1_FRC_PHY_REG, RG_PE1_PHY_EN, in mt7621_set_phy_for_ssc()
138 if (phy->has_dual_port) { in mt7621_set_phy_for_ssc()
139 mt7621_phy_rmw(phy, RG_PE1_FRC_PHY_REG + RG_P0_TO_P1_WIDTH, in mt7621_set_phy_for_ssc()
144 /* Set Pre-divider ratio (for host mode) */ in mt7621_set_phy_for_ssc()
145 mt7621_phy_rmw(phy, RG_PE1_H_PLL_REG, RG_PE1_H_PLL_PREDIV, in mt7621_set_phy_for_ssc()
150 mt7621_phy_rmw(phy, RG_PE1_H_PLL_REG, RG_PE1_H_PLL_PREDIV, in mt7621_set_phy_for_ssc()
154 mt7621_phy_rmw(phy, RG_PE1_H_PLL_FBKSEL_REG, in mt7621_set_phy_for_ssc()
159 mt7621_phy_rmw(phy, RG_PE1_H_LCDDS_SSC_PRD_REG, in mt7621_set_phy_for_ssc()
164 mt7621_phy_rmw(phy, RG_PE1_H_LCDDS_SSC_PRD_REG, in mt7621_set_phy_for_ssc()
169 mt7621_phy_rmw(phy, RG_PE1_H_LCDDS_SSC_DELTA_REG, in mt7621_set_phy_for_ssc()
177 mt7621_phy_rmw(phy, RG_PE1_H_PLL_REG, RG_PE1_H_PLL_PREDIV, in mt7621_set_phy_for_ssc()
184 mt7621_phy_rmw(phy, RG_PE1_LCDDS_CLK_PH_INV_REG, in mt7621_set_phy_for_ssc()
188 mt7621_phy_rmw(phy, RG_PE1_H_PLL_REG, in mt7621_set_phy_for_ssc()
197 mt7621_phy_rmw(phy, RG_PE1_H_PLL_BR_REG, RG_PE1_H_PLL_BR, in mt7621_set_phy_for_ssc()
202 mt7621_phy_rmw(phy, RG_PE1_MSTCKDIV_REG, in mt7621_set_phy_for_ssc()
211 static int mt7621_pci_phy_init(struct phy *phy) in mt7621_pci_phy_init() argument
213 struct mt7621_pci_phy *mphy = phy_get_drvdata(phy); in mt7621_pci_phy_init()
215 if (mphy->bypass_pipe_rst) in mt7621_pci_phy_init()
221 static int mt7621_pci_phy_power_on(struct phy *phy) in mt7621_pci_phy_power_on() argument
223 struct mt7621_pci_phy *mphy = phy_get_drvdata(phy); in mt7621_pci_phy_power_on()
225 /* Enable PHY and disable force mode */ in mt7621_pci_phy_power_on()
229 if (mphy->has_dual_port) { in mt7621_pci_phy_power_on()
237 static int mt7621_pci_phy_power_off(struct phy *phy) in mt7621_pci_phy_power_off() argument
239 struct mt7621_pci_phy *mphy = phy_get_drvdata(phy); in mt7621_pci_phy_power_off()
241 /* Disable PHY */ in mt7621_pci_phy_power_off()
245 if (mphy->has_dual_port) { in mt7621_pci_phy_power_off()
253 static int mt7621_pci_phy_exit(struct phy *phy) in mt7621_pci_phy_exit() argument
266 static struct phy *mt7621_pcie_phy_of_xlate(struct device *dev, in mt7621_pcie_phy_of_xlate()
271 if (WARN_ON(args->args[0] >= MAX_PHYS)) in mt7621_pcie_phy_of_xlate()
272 return ERR_PTR(-ENODEV); in mt7621_pcie_phy_of_xlate()
274 mt7621_phy->has_dual_port = args->args[0]; in mt7621_pcie_phy_of_xlate()
276 dev_dbg(dev, "PHY for 0x%px (dual port = %d)\n", in mt7621_pcie_phy_of_xlate()
277 mt7621_phy->port_base, mt7621_phy->has_dual_port); in mt7621_pcie_phy_of_xlate()
279 return mt7621_phy->phy; in mt7621_pcie_phy_of_xlate()
296 struct device *dev = &pdev->dev; in mt7621_pci_phy_probe()
299 struct mt7621_pci_phy *phy; in mt7621_pci_phy_probe() local
301 phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL); in mt7621_pci_phy_probe()
302 if (!phy) in mt7621_pci_phy_probe()
303 return -ENOMEM; in mt7621_pci_phy_probe()
307 phy->bypass_pipe_rst = true; in mt7621_pci_phy_probe()
309 phy->dev = dev; in mt7621_pci_phy_probe()
310 platform_set_drvdata(pdev, phy); in mt7621_pci_phy_probe()
312 phy->port_base = devm_platform_ioremap_resource(pdev, 0); in mt7621_pci_phy_probe()
313 if (IS_ERR(phy->port_base)) { in mt7621_pci_phy_probe()
314 dev_err(dev, "failed to remap phy regs\n"); in mt7621_pci_phy_probe()
315 return PTR_ERR(phy->port_base); in mt7621_pci_phy_probe()
318 phy->regmap = devm_regmap_init_mmio(phy->dev, phy->port_base, in mt7621_pci_phy_probe()
320 if (IS_ERR(phy->regmap)) in mt7621_pci_phy_probe()
321 return PTR_ERR(phy->regmap); in mt7621_pci_phy_probe()
323 phy->phy = devm_phy_create(dev, dev->of_node, &mt7621_pci_phy_ops); in mt7621_pci_phy_probe()
324 if (IS_ERR(phy->phy)) { in mt7621_pci_phy_probe()
325 dev_err(dev, "failed to create phy\n"); in mt7621_pci_phy_probe()
326 return PTR_ERR(phy->phy); in mt7621_pci_phy_probe()
329 phy->sys_clk = devm_clk_get(dev, NULL); in mt7621_pci_phy_probe()
330 if (IS_ERR(phy->sys_clk)) { in mt7621_pci_phy_probe()
331 dev_err(dev, "failed to get phy clock\n"); in mt7621_pci_phy_probe()
332 return PTR_ERR(phy->sys_clk); in mt7621_pci_phy_probe()
335 phy_set_drvdata(phy->phy, phy); in mt7621_pci_phy_probe()
343 { .compatible = "mediatek,mt7621-pci-phy" },
351 .name = "mt7621-pci-phy",
359 MODULE_DESCRIPTION("MediaTek MT7621 PCIe PHY driver");