152 static int qcom_snps_hsphy_suspend(struct qcom_snps_hsphy *hsphy)  in qcom_snps_hsphy_suspend()  argument
154 	dev_dbg(&hsphy->phy->dev, "Suspend QCOM SNPS PHY\n");  in qcom_snps_hsphy_suspend()
156 	if (hsphy->mode == PHY_MODE_USB_HOST) {  in qcom_snps_hsphy_suspend()
158 		qcom_snps_hsphy_write_mask(hsphy->base,  in qcom_snps_hsphy_suspend()
163 		qcom_snps_hsphy_write_mask(hsphy->base,  in qcom_snps_hsphy_suspend()
168 	clk_disable_unprepare(hsphy->cfg_ahb_clk);  in qcom_snps_hsphy_suspend()
172 static int qcom_snps_hsphy_resume(struct qcom_snps_hsphy *hsphy)  in qcom_snps_hsphy_resume()  argument
176 	dev_dbg(&hsphy->phy->dev, "Resume QCOM SNPS PHY, mode\n");  in qcom_snps_hsphy_resume()
178 	ret = clk_prepare_enable(hsphy->cfg_ahb_clk);  in qcom_snps_hsphy_resume()
180 		dev_err(&hsphy->phy->dev, "failed to enable cfg ahb clock\n");  in qcom_snps_hsphy_resume()
189 	struct qcom_snps_hsphy *hsphy = dev_get_drvdata(dev);  in qcom_snps_hsphy_runtime_suspend()  local
191 	if (!hsphy->phy_initialized)  in qcom_snps_hsphy_runtime_suspend()
194 	qcom_snps_hsphy_suspend(hsphy);  in qcom_snps_hsphy_runtime_suspend()
200 	struct qcom_snps_hsphy *hsphy = dev_get_drvdata(dev);  in qcom_snps_hsphy_runtime_resume()  local
202 	if (!hsphy->phy_initialized)  in qcom_snps_hsphy_runtime_resume()
205 	qcom_snps_hsphy_resume(hsphy);  in qcom_snps_hsphy_runtime_resume()
212 	struct qcom_snps_hsphy *hsphy = phy_get_drvdata(phy);  in qcom_snps_hsphy_set_mode()  local
214 	hsphy->mode = mode;  in qcom_snps_hsphy_set_mode()
368 	struct qcom_snps_hsphy *hsphy = phy_get_drvdata(phy);  in qcom_snps_hsphy_init()  local
373 	ret = regulator_bulk_enable(ARRAY_SIZE(hsphy->vregs), hsphy->vregs);  in qcom_snps_hsphy_init()
377 	ret = clk_prepare_enable(hsphy->cfg_ahb_clk);  in qcom_snps_hsphy_init()
383 	ret = reset_control_assert(hsphy->phy_reset);  in qcom_snps_hsphy_init()
391 	ret = reset_control_deassert(hsphy->phy_reset);  in qcom_snps_hsphy_init()
397 	qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_CFG0,  in qcom_snps_hsphy_init()
400 	qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_UTMI_CTRL5,  in qcom_snps_hsphy_init()
402 	qcom_snps_hsphy_write_mask(hsphy->base,  in qcom_snps_hsphy_init()
405 	qcom_snps_hsphy_write_mask(hsphy->base,  in qcom_snps_hsphy_init()
408 	qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_REFCLK_CTRL,  in qcom_snps_hsphy_init()
410 	qcom_snps_hsphy_write_mask(hsphy->base,  in qcom_snps_hsphy_init()
413 	qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL1,  in qcom_snps_hsphy_init()
416 	for (i = 0; i < ARRAY_SIZE(hsphy->update_seq_cfg); i++) {  in qcom_snps_hsphy_init()
417 		if (hsphy->update_seq_cfg[i].need_update)  in qcom_snps_hsphy_init()
418 			qcom_snps_hsphy_write_mask(hsphy->base,  in qcom_snps_hsphy_init()
419 					hsphy->update_seq_cfg[i].offset,  in qcom_snps_hsphy_init()
420 					hsphy->update_seq_cfg[i].mask,  in qcom_snps_hsphy_init()
421 					hsphy->update_seq_cfg[i].value);  in qcom_snps_hsphy_init()
424 	qcom_snps_hsphy_write_mask(hsphy->base,  in qcom_snps_hsphy_init()
428 	qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL2,  in qcom_snps_hsphy_init()
432 	qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_UTMI_CTRL0,  in qcom_snps_hsphy_init()
435 	qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON0,  in qcom_snps_hsphy_init()
438 	qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_UTMI_CTRL5,  in qcom_snps_hsphy_init()
441 	qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL2,  in qcom_snps_hsphy_init()
444 	qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_CFG0,  in qcom_snps_hsphy_init()
447 	hsphy->phy_initialized = true;  in qcom_snps_hsphy_init()
452 	clk_disable_unprepare(hsphy->cfg_ahb_clk);  in qcom_snps_hsphy_init()
454 	regulator_bulk_disable(ARRAY_SIZE(hsphy->vregs), hsphy->vregs);  in qcom_snps_hsphy_init()
461 	struct qcom_snps_hsphy *hsphy = phy_get_drvdata(phy);  in qcom_snps_hsphy_exit()  local
463 	reset_control_assert(hsphy->phy_reset);  in qcom_snps_hsphy_exit()
464 	clk_disable_unprepare(hsphy->cfg_ahb_clk);  in qcom_snps_hsphy_exit()
465 	regulator_bulk_disable(ARRAY_SIZE(hsphy->vregs), hsphy->vregs);  in qcom_snps_hsphy_exit()
466 	hsphy->phy_initialized = false;  in qcom_snps_hsphy_exit()
523 	struct qcom_snps_hsphy *hsphy;  in qcom_snps_hsphy_read_override_param_seq()  local
529 	hsphy = dev_get_drvdata(dev);  in qcom_snps_hsphy_read_override_param_seq()
537 					&hsphy->update_seq_cfg[i]);  in qcom_snps_hsphy_read_override_param_seq()
538 		dev_dbg(&hsphy->phy->dev, "Read param: %s dt_val: %d reg_val: 0x%x\n",  in qcom_snps_hsphy_read_override_param_seq()
539 			cfg[i].prop_name, val, hsphy->update_seq_cfg[i].value);  in qcom_snps_hsphy_read_override_param_seq()
547 	struct qcom_snps_hsphy *hsphy;  in qcom_snps_hsphy_probe()  local
553 	hsphy = devm_kzalloc(dev, sizeof(*hsphy), GFP_KERNEL);  in qcom_snps_hsphy_probe()
554 	if (!hsphy)  in qcom_snps_hsphy_probe()
557 	hsphy->base = devm_platform_ioremap_resource(pdev, 0);  in qcom_snps_hsphy_probe()
558 	if (IS_ERR(hsphy->base))  in qcom_snps_hsphy_probe()
559 		return PTR_ERR(hsphy->base);  in qcom_snps_hsphy_probe()
561 	hsphy->ref_clk = devm_clk_get(dev, "ref");  in qcom_snps_hsphy_probe()
562 	if (IS_ERR(hsphy->ref_clk))  in qcom_snps_hsphy_probe()
563 		return dev_err_probe(dev, PTR_ERR(hsphy->ref_clk),  in qcom_snps_hsphy_probe()
566 	hsphy->phy_reset = devm_reset_control_get_exclusive(&pdev->dev, NULL);  in qcom_snps_hsphy_probe()
567 	if (IS_ERR(hsphy->phy_reset)) {  in qcom_snps_hsphy_probe()
569 		return PTR_ERR(hsphy->phy_reset);  in qcom_snps_hsphy_probe()
572 	num = ARRAY_SIZE(hsphy->vregs);  in qcom_snps_hsphy_probe()
574 		hsphy->vregs[i].supply = qcom_snps_hsphy_vreg_names[i];  in qcom_snps_hsphy_probe()
576 	ret = devm_regulator_bulk_get(dev, num, hsphy->vregs);  in qcom_snps_hsphy_probe()
595 	hsphy->phy = generic_phy;  in qcom_snps_hsphy_probe()
597 	dev_set_drvdata(dev, hsphy);  in qcom_snps_hsphy_probe()
598 	phy_set_drvdata(generic_phy, hsphy);  in qcom_snps_hsphy_probe()