Lines Matching +full:efuse +full:- +full:tx +full:- +full:imp
1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/nvmem-consumer.h>
23 #include <dt-bindings/phy/phy-qcom-qusb2.h>
106 * if yes, then offset gives index in the reg-layout
124 /* set of registers with offsets different per-PHY */
295 /* true if PHY default clk scheme is single-ended */
374 "vdd", "vdda-pll", "vdda-phy-dpdm",
379 /* struct override_param - structure holding qusb2 v2 phy overriding param
388 /*struct override_params - structure holding qusb2 v2 phy overriding params
391 * @preemphasis: Amplitude Pre-Emphasis to be updated in TUNE1 register
392 * @preemphasis_width: half/full-width Pre-Emphasis updated via TUNE1
408 * struct qusb2_phy - structure holding qusb2 phy attributes
425 * @has_se_clk_scheme: indicate if PHY has single-ended ref clock scheme
509 const struct qusb2_phy_cfg *cfg = qphy->cfg; in qusb2_phy_override_phy_params()
510 struct override_params *or = &qphy->overrides; in qusb2_phy_override_phy_params()
512 if (or->imp_res_offset.override) in qusb2_phy_override_phy_params()
513 qusb2_write_mask(qphy->base, QUSB2PHY_IMP_CTRL1, in qusb2_phy_override_phy_params()
514 or->imp_res_offset.value << IMP_RES_OFFSET_SHIFT, in qusb2_phy_override_phy_params()
517 if (or->bias_ctrl.override) in qusb2_phy_override_phy_params()
518 qusb2_write_mask(qphy->base, QUSB2PHY_PLL_BIAS_CONTROL_2, in qusb2_phy_override_phy_params()
519 or->bias_ctrl.value << BIAS_CTRL2_RES_OFFSET_SHIFT, in qusb2_phy_override_phy_params()
522 if (or->charge_ctrl.override) in qusb2_phy_override_phy_params()
523 qusb2_write_mask(qphy->base, QUSB2PHY_CHG_CTRL2, in qusb2_phy_override_phy_params()
524 or->charge_ctrl.value << CHG_CTRL2_OFFSET_SHIFT, in qusb2_phy_override_phy_params()
527 if (or->hstx_trim.override) in qusb2_phy_override_phy_params()
528 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1], in qusb2_phy_override_phy_params()
529 or->hstx_trim.value << HSTX_TRIM_SHIFT, in qusb2_phy_override_phy_params()
532 if (or->preemphasis.override) in qusb2_phy_override_phy_params()
533 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1], in qusb2_phy_override_phy_params()
534 or->preemphasis.value << PREEMPHASIS_EN_SHIFT, in qusb2_phy_override_phy_params()
537 if (or->preemphasis_width.override) { in qusb2_phy_override_phy_params()
538 if (or->preemphasis_width.value == in qusb2_phy_override_phy_params()
540 qusb2_setbits(qphy->base, in qusb2_phy_override_phy_params()
541 cfg->regs[QUSB2PHY_PORT_TUNE1], in qusb2_phy_override_phy_params()
544 qusb2_clrbits(qphy->base, in qusb2_phy_override_phy_params()
545 cfg->regs[QUSB2PHY_PORT_TUNE1], in qusb2_phy_override_phy_params()
549 if (or->hsdisc_trim.override) in qusb2_phy_override_phy_params()
550 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE2], in qusb2_phy_override_phy_params()
551 or->hsdisc_trim.value << HSDISC_TRIM_SHIFT, in qusb2_phy_override_phy_params()
556 * Fetches HS Tx tuning value from nvmem and sets the
562 struct device *dev = &qphy->phy->dev; in qusb2_phy_set_tune2_param()
563 const struct qusb2_phy_cfg *cfg = qphy->cfg; in qusb2_phy_set_tune2_param()
566 /* efuse register is optional */ in qusb2_phy_set_tune2_param()
567 if (!qphy->cell) in qusb2_phy_set_tune2_param()
571 * Read efuse register having TUNE2/1 parameter's high nibble. in qusb2_phy_set_tune2_param()
572 * If efuse register shows value as 0x0 (indicating value is not in qusb2_phy_set_tune2_param()
573 * fused), or if we fail to find a valid efuse register setting, in qusb2_phy_set_tune2_param()
577 val = nvmem_cell_read(qphy->cell, NULL); in qusb2_phy_set_tune2_param()
579 dev_dbg(dev, "failed to read a valid hs-tx trim value\n"); in qusb2_phy_set_tune2_param()
585 dev_dbg(dev, "failed to read a valid hs-tx trim value\n"); in qusb2_phy_set_tune2_param()
590 if (cfg->update_tune1_with_efuse) in qusb2_phy_set_tune2_param()
591 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1], in qusb2_phy_set_tune2_param()
594 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE2], in qusb2_phy_set_tune2_param()
603 qphy->mode = mode; in qusb2_phy_set_mode()
611 const struct qusb2_phy_cfg *cfg = qphy->cfg; in qusb2_phy_runtime_suspend()
614 dev_vdbg(dev, "Suspending QUSB2 Phy, mode:%d\n", qphy->mode); in qusb2_phy_runtime_suspend()
616 if (!qphy->phy_initialized) { in qusb2_phy_runtime_suspend()
624 * current D+/D- levels are e.g. if currently D+ high, D- low in qusb2_phy_runtime_suspend()
625 * (HS 'J'/Suspend), configure the mask to trigger on D+ low OR D- high in qusb2_phy_runtime_suspend()
628 switch (qphy->mode) { in qusb2_phy_runtime_suspend()
646 writel(intr_mask, qphy->base + cfg->regs[QUSB2PHY_INTR_CTRL]); in qusb2_phy_runtime_suspend()
649 if (cfg->has_pll_override) { in qusb2_phy_runtime_suspend()
650 qusb2_setbits(qphy->base, in qusb2_phy_runtime_suspend()
651 cfg->regs[QUSB2PHY_PLL_CORE_INPUT_OVERRIDE], in qusb2_phy_runtime_suspend()
656 /* enable phy auto-resume only if device is connected on bus */ in qusb2_phy_runtime_suspend()
657 if (qphy->mode != PHY_MODE_INVALID) { in qusb2_phy_runtime_suspend()
658 qusb2_setbits(qphy->base, cfg->regs[QUSB2PHY_PORT_TEST1], in qusb2_phy_runtime_suspend()
659 cfg->autoresume_en); in qusb2_phy_runtime_suspend()
661 qusb2_clrbits(qphy->base, cfg->regs[QUSB2PHY_PORT_TEST1], in qusb2_phy_runtime_suspend()
662 cfg->autoresume_en); in qusb2_phy_runtime_suspend()
665 if (!qphy->has_se_clk_scheme) in qusb2_phy_runtime_suspend()
666 clk_disable_unprepare(qphy->ref_clk); in qusb2_phy_runtime_suspend()
668 clk_disable_unprepare(qphy->cfg_ahb_clk); in qusb2_phy_runtime_suspend()
669 clk_disable_unprepare(qphy->iface_clk); in qusb2_phy_runtime_suspend()
677 const struct qusb2_phy_cfg *cfg = qphy->cfg; in qusb2_phy_runtime_resume()
680 dev_vdbg(dev, "Resuming QUSB2 phy, mode:%d\n", qphy->mode); in qusb2_phy_runtime_resume()
682 if (!qphy->phy_initialized) { in qusb2_phy_runtime_resume()
687 ret = clk_prepare_enable(qphy->iface_clk); in qusb2_phy_runtime_resume()
693 ret = clk_prepare_enable(qphy->cfg_ahb_clk); in qusb2_phy_runtime_resume()
699 if (!qphy->has_se_clk_scheme) { in qusb2_phy_runtime_resume()
700 ret = clk_prepare_enable(qphy->ref_clk); in qusb2_phy_runtime_resume()
707 writel(0x0, qphy->base + cfg->regs[QUSB2PHY_INTR_CTRL]); in qusb2_phy_runtime_resume()
710 if (cfg->has_pll_override) { in qusb2_phy_runtime_resume()
711 qusb2_clrbits(qphy->base, in qusb2_phy_runtime_resume()
712 cfg->regs[QUSB2PHY_PLL_CORE_INPUT_OVERRIDE], in qusb2_phy_runtime_resume()
719 clk_disable_unprepare(qphy->cfg_ahb_clk); in qusb2_phy_runtime_resume()
721 clk_disable_unprepare(qphy->iface_clk); in qusb2_phy_runtime_resume()
729 const struct qusb2_phy_cfg *cfg = qphy->cfg; in qusb2_phy_init()
734 dev_vdbg(&phy->dev, "%s(): Initializing QUSB2 phy\n", __func__); in qusb2_phy_init()
737 ret = regulator_bulk_enable(ARRAY_SIZE(qphy->vregs), qphy->vregs); in qusb2_phy_init()
741 ret = clk_prepare_enable(qphy->iface_clk); in qusb2_phy_init()
743 dev_err(&phy->dev, "failed to enable iface_clk, %d\n", ret); in qusb2_phy_init()
748 ret = clk_prepare_enable(qphy->cfg_ahb_clk); in qusb2_phy_init()
750 dev_err(&phy->dev, "failed to enable cfg ahb clock, %d\n", ret); in qusb2_phy_init()
755 ret = reset_control_assert(qphy->phy_reset); in qusb2_phy_init()
757 dev_err(&phy->dev, "failed to assert phy_reset, %d\n", ret); in qusb2_phy_init()
764 ret = reset_control_deassert(qphy->phy_reset); in qusb2_phy_init()
766 dev_err(&phy->dev, "failed to de-assert phy_reset, %d\n", ret); in qusb2_phy_init()
771 qusb2_setbits(qphy->base, cfg->regs[QUSB2PHY_PORT_POWERDOWN], in qusb2_phy_init()
772 qphy->cfg->disable_ctrl); in qusb2_phy_init()
774 if (cfg->has_pll_test) { in qusb2_phy_init()
776 val = readl(qphy->base + QUSB2PHY_PLL_TEST); in qusb2_phy_init()
779 qcom_qusb2_phy_configure(qphy->base, cfg->regs, cfg->tbl, in qusb2_phy_init()
780 cfg->tbl_num); in qusb2_phy_init()
785 /* Set efuse value for tuning the PHY */ in qusb2_phy_init()
789 qusb2_clrbits(qphy->base, cfg->regs[QUSB2PHY_PORT_POWERDOWN], in qusb2_phy_init()
800 qphy->has_se_clk_scheme = cfg->se_clk_scheme_default; in qusb2_phy_init()
803 * read TCSR_PHY_CLK_SCHEME register to check if single-ended in qusb2_phy_init()
805 * ref_clk and use single-ended clock, otherwise use differential in qusb2_phy_init()
808 if (qphy->tcsr) { in qusb2_phy_init()
809 ret = regmap_read(qphy->tcsr, qphy->cfg->clk_scheme_offset, in qusb2_phy_init()
812 dev_err(&phy->dev, "failed to read clk scheme reg\n"); in qusb2_phy_init()
818 dev_vdbg(&phy->dev, "%s(): select differential clk\n", in qusb2_phy_init()
820 qphy->has_se_clk_scheme = false; in qusb2_phy_init()
822 dev_vdbg(&phy->dev, "%s(): select single-ended clk\n", in qusb2_phy_init()
827 if (!qphy->has_se_clk_scheme) { in qusb2_phy_init()
828 ret = clk_prepare_enable(qphy->ref_clk); in qusb2_phy_init()
830 dev_err(&phy->dev, "failed to enable ref clk, %d\n", in qusb2_phy_init()
836 if (cfg->has_pll_test) { in qusb2_phy_init()
837 if (!qphy->has_se_clk_scheme) in qusb2_phy_init()
842 writel(val, qphy->base + QUSB2PHY_PLL_TEST); in qusb2_phy_init()
845 readl(qphy->base + QUSB2PHY_PLL_TEST); in qusb2_phy_init()
851 val = readb(qphy->base + cfg->regs[QUSB2PHY_PLL_STATUS]); in qusb2_phy_init()
852 if (!(val & cfg->mask_core_ready)) { in qusb2_phy_init()
853 dev_err(&phy->dev, in qusb2_phy_init()
855 ret = -EBUSY; in qusb2_phy_init()
858 qphy->phy_initialized = true; in qusb2_phy_init()
863 if (!qphy->has_se_clk_scheme) in qusb2_phy_init()
864 clk_disable_unprepare(qphy->ref_clk); in qusb2_phy_init()
866 reset_control_assert(qphy->phy_reset); in qusb2_phy_init()
868 clk_disable_unprepare(qphy->cfg_ahb_clk); in qusb2_phy_init()
870 clk_disable_unprepare(qphy->iface_clk); in qusb2_phy_init()
872 regulator_bulk_disable(ARRAY_SIZE(qphy->vregs), qphy->vregs); in qusb2_phy_init()
882 qusb2_setbits(qphy->base, qphy->cfg->regs[QUSB2PHY_PORT_POWERDOWN], in qusb2_phy_exit()
883 qphy->cfg->disable_ctrl); in qusb2_phy_exit()
885 if (!qphy->has_se_clk_scheme) in qusb2_phy_exit()
886 clk_disable_unprepare(qphy->ref_clk); in qusb2_phy_exit()
888 reset_control_assert(qphy->phy_reset); in qusb2_phy_exit()
890 clk_disable_unprepare(qphy->cfg_ahb_clk); in qusb2_phy_exit()
891 clk_disable_unprepare(qphy->iface_clk); in qusb2_phy_exit()
893 regulator_bulk_disable(ARRAY_SIZE(qphy->vregs), qphy->vregs); in qusb2_phy_exit()
895 qphy->phy_initialized = false; in qusb2_phy_exit()
909 .compatible = "qcom,ipq6018-qusb2-phy",
912 .compatible = "qcom,ipq8074-qusb2-phy",
915 .compatible = "qcom,msm8953-qusb2-phy",
918 .compatible = "qcom,msm8996-qusb2-phy",
921 .compatible = "qcom,msm8998-qusb2-phy",
924 .compatible = "qcom,qcm2290-qusb2-phy",
927 .compatible = "qcom,sdm660-qusb2-phy",
930 .compatible = "qcom,sm4250-qusb2-phy",
933 .compatible = "qcom,sm6115-qusb2-phy",
938 * trees that didn't include "qcom,qusb2-v2-phy"
940 .compatible = "qcom,sdm845-qusb2-phy",
943 .compatible = "qcom,qusb2-v2-phy",
957 struct device *dev = &pdev->dev; in qusb2_phy_probe()
968 return -ENOMEM; in qusb2_phy_probe()
969 or = &qphy->overrides; in qusb2_phy_probe()
971 qphy->base = devm_platform_ioremap_resource(pdev, 0); in qusb2_phy_probe()
972 if (IS_ERR(qphy->base)) in qusb2_phy_probe()
973 return PTR_ERR(qphy->base); in qusb2_phy_probe()
975 qphy->cfg_ahb_clk = devm_clk_get(dev, "cfg_ahb"); in qusb2_phy_probe()
976 if (IS_ERR(qphy->cfg_ahb_clk)) in qusb2_phy_probe()
977 return dev_err_probe(dev, PTR_ERR(qphy->cfg_ahb_clk), in qusb2_phy_probe()
980 qphy->ref_clk = devm_clk_get(dev, "ref"); in qusb2_phy_probe()
981 if (IS_ERR(qphy->ref_clk)) in qusb2_phy_probe()
982 return dev_err_probe(dev, PTR_ERR(qphy->ref_clk), in qusb2_phy_probe()
985 qphy->iface_clk = devm_clk_get_optional(dev, "iface"); in qusb2_phy_probe()
986 if (IS_ERR(qphy->iface_clk)) in qusb2_phy_probe()
987 return PTR_ERR(qphy->iface_clk); in qusb2_phy_probe()
989 qphy->phy_reset = devm_reset_control_get_by_index(&pdev->dev, 0); in qusb2_phy_probe()
990 if (IS_ERR(qphy->phy_reset)) { in qusb2_phy_probe()
992 return PTR_ERR(qphy->phy_reset); in qusb2_phy_probe()
995 num = ARRAY_SIZE(qphy->vregs); in qusb2_phy_probe()
997 qphy->vregs[i].supply = qusb2_phy_vreg_names[i]; in qusb2_phy_probe()
999 ret = devm_regulator_bulk_get(dev, num, qphy->vregs); in qusb2_phy_probe()
1005 qphy->cfg = of_device_get_match_data(dev); in qusb2_phy_probe()
1007 qphy->tcsr = syscon_regmap_lookup_by_phandle(dev->of_node, in qusb2_phy_probe()
1008 "qcom,tcsr-syscon"); in qusb2_phy_probe()
1009 if (IS_ERR(qphy->tcsr)) { in qusb2_phy_probe()
1011 qphy->tcsr = NULL; in qusb2_phy_probe()
1014 qphy->cell = devm_nvmem_cell_get(dev, NULL); in qusb2_phy_probe()
1015 if (IS_ERR(qphy->cell)) { in qusb2_phy_probe()
1016 if (PTR_ERR(qphy->cell) == -EPROBE_DEFER) in qusb2_phy_probe()
1017 return -EPROBE_DEFER; in qusb2_phy_probe()
1018 qphy->cell = NULL; in qusb2_phy_probe()
1022 if (!of_property_read_u32(dev->of_node, "qcom,imp-res-offset-value", in qusb2_phy_probe()
1024 or->imp_res_offset.value = (u8)value; in qusb2_phy_probe()
1025 or->imp_res_offset.override = true; in qusb2_phy_probe()
1028 if (!of_property_read_u32(dev->of_node, "qcom,bias-ctrl-value", in qusb2_phy_probe()
1030 or->bias_ctrl.value = (u8)value; in qusb2_phy_probe()
1031 or->bias_ctrl.override = true; in qusb2_phy_probe()
1034 if (!of_property_read_u32(dev->of_node, "qcom,charge-ctrl-value", in qusb2_phy_probe()
1036 or->charge_ctrl.value = (u8)value; in qusb2_phy_probe()
1037 or->charge_ctrl.override = true; in qusb2_phy_probe()
1040 if (!of_property_read_u32(dev->of_node, "qcom,hstx-trim-value", in qusb2_phy_probe()
1042 or->hstx_trim.value = (u8)value; in qusb2_phy_probe()
1043 or->hstx_trim.override = true; in qusb2_phy_probe()
1046 if (!of_property_read_u32(dev->of_node, "qcom,preemphasis-level", in qusb2_phy_probe()
1048 or->preemphasis.value = (u8)value; in qusb2_phy_probe()
1049 or->preemphasis.override = true; in qusb2_phy_probe()
1052 if (!of_property_read_u32(dev->of_node, "qcom,preemphasis-width", in qusb2_phy_probe()
1054 or->preemphasis_width.value = (u8)value; in qusb2_phy_probe()
1055 or->preemphasis_width.override = true; in qusb2_phy_probe()
1058 if (!of_property_read_u32(dev->of_node, "qcom,hsdisc-trim-value", in qusb2_phy_probe()
1060 or->hsdisc_trim.value = (u8)value; in qusb2_phy_probe()
1061 or->hsdisc_trim.override = true; in qusb2_phy_probe()
1079 qphy->phy = generic_phy; in qusb2_phy_probe()
1086 dev_info(dev, "Registered Qcom-QUSB2 phy\n"); in qusb2_phy_probe()
1096 .name = "qcom-qusb2-phy",