Lines Matching +full:0 +full:x124
11 #define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c
12 #define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x010
13 #define QPHY_V5_PCS_UFS_PLL_CNTL 0x02c
14 #define QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x030
15 #define QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x038
16 #define QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074
17 #define QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0b4
18 #define QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL 0x124
19 #define QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME 0x150
20 #define QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1 0x154
21 #define QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2 0x158
22 #define QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND 0x160
23 #define QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND 0x168
24 #define QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1 0x1d8
25 #define QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1 0x1e0