Lines Matching +full:gcc +full:- +full:sdx55
1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
23 #include <dt-bindings/phy/phy.h>
25 #include "phy-qcom-qmp.h"
46 * if yes, then offset gives index in the reg-layout
78 /* set of registers with offsets different per-PHY */
1303 /* struct qmp_phy_cfg - per-PHY initialization config */
1307 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
1358 * struct qmp_phy - per-lane phy descriptor
1387 * struct qcom_qmp - structure holding QMP phy block attributes
1395 * @phys: array of per-lane phy descriptors
1443 "vdda-phy", "vdda-pll",
1835 if (!(t->lane_mask & lane_mask)) in qmp_pcie_configure_lane()
1838 if (t->in_layout) in qmp_pcie_configure_lane()
1839 writel(t->val, base + regs[t->offset]); in qmp_pcie_configure_lane()
1841 writel(t->val, base + t->offset); in qmp_pcie_configure_lane()
1855 const struct qmp_phy_cfg *cfg = qphy->cfg; in qmp_pcie_serdes_init()
1856 void __iomem *serdes = qphy->serdes; in qmp_pcie_serdes_init()
1857 const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl; in qmp_pcie_serdes_init()
1858 int serdes_tbl_num = cfg->serdes_tbl_num; in qmp_pcie_serdes_init()
1860 qmp_pcie_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num); in qmp_pcie_serdes_init()
1861 qmp_pcie_configure(serdes, cfg->regs, cfg->serdes_tbl_sec, cfg->serdes_tbl_num_sec); in qmp_pcie_serdes_init()
1869 struct qcom_qmp *qmp = qphy->qmp; in qmp_pcie_init()
1870 const struct qmp_phy_cfg *cfg = qphy->cfg; in qmp_pcie_init()
1871 void __iomem *pcs = qphy->pcs; in qmp_pcie_init()
1875 ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs); in qmp_pcie_init()
1877 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret); in qmp_pcie_init()
1881 ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets); in qmp_pcie_init()
1883 dev_err(qmp->dev, "reset assert failed\n"); in qmp_pcie_init()
1887 ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets); in qmp_pcie_init()
1889 dev_err(qmp->dev, "reset deassert failed\n"); in qmp_pcie_init()
1893 ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks); in qmp_pcie_init()
1897 if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) in qmp_pcie_init()
1899 cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], in qmp_pcie_init()
1900 cfg->pwrdn_ctrl); in qmp_pcie_init()
1903 cfg->pwrdn_ctrl); in qmp_pcie_init()
1908 reset_control_bulk_assert(cfg->num_resets, qmp->resets); in qmp_pcie_init()
1910 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); in qmp_pcie_init()
1918 struct qcom_qmp *qmp = qphy->qmp; in qmp_pcie_exit()
1919 const struct qmp_phy_cfg *cfg = qphy->cfg; in qmp_pcie_exit()
1921 reset_control_bulk_assert(cfg->num_resets, qmp->resets); in qmp_pcie_exit()
1923 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); in qmp_pcie_exit()
1925 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); in qmp_pcie_exit()
1933 struct qcom_qmp *qmp = qphy->qmp; in qmp_pcie_power_on()
1934 const struct qmp_phy_cfg *cfg = qphy->cfg; in qmp_pcie_power_on()
1935 void __iomem *tx = qphy->tx; in qmp_pcie_power_on()
1936 void __iomem *rx = qphy->rx; in qmp_pcie_power_on()
1937 void __iomem *pcs = qphy->pcs; in qmp_pcie_power_on()
1938 void __iomem *pcs_misc = qphy->pcs_misc; in qmp_pcie_power_on()
1945 ret = clk_prepare_enable(qphy->pipe_clk); in qmp_pcie_power_on()
1947 dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret); in qmp_pcie_power_on()
1952 qmp_pcie_configure_lane(tx, cfg->regs, cfg->tx_tbl, cfg->tx_tbl_num, 1); in qmp_pcie_power_on()
1953 qmp_pcie_configure_lane(tx, cfg->regs, cfg->tx_tbl_sec, cfg->tx_tbl_num_sec, 1); in qmp_pcie_power_on()
1955 if (cfg->lanes >= 2) { in qmp_pcie_power_on()
1956 qmp_pcie_configure_lane(qphy->tx2, cfg->regs, cfg->tx_tbl, in qmp_pcie_power_on()
1957 cfg->tx_tbl_num, 2); in qmp_pcie_power_on()
1958 qmp_pcie_configure_lane(qphy->tx2, cfg->regs, cfg->tx_tbl_sec, in qmp_pcie_power_on()
1959 cfg->tx_tbl_num_sec, 2); in qmp_pcie_power_on()
1962 qmp_pcie_configure_lane(rx, cfg->regs, cfg->rx_tbl, cfg->rx_tbl_num, 1); in qmp_pcie_power_on()
1963 qmp_pcie_configure_lane(rx, cfg->regs, cfg->rx_tbl_sec, cfg->rx_tbl_num_sec, 1); in qmp_pcie_power_on()
1965 if (cfg->lanes >= 2) { in qmp_pcie_power_on()
1966 qmp_pcie_configure_lane(qphy->rx2, cfg->regs, cfg->rx_tbl, in qmp_pcie_power_on()
1967 cfg->rx_tbl_num, 2); in qmp_pcie_power_on()
1968 qmp_pcie_configure_lane(qphy->rx2, cfg->regs, cfg->rx_tbl_sec, in qmp_pcie_power_on()
1969 cfg->rx_tbl_num_sec, 2); in qmp_pcie_power_on()
1972 qmp_pcie_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num); in qmp_pcie_power_on()
1973 qmp_pcie_configure(pcs, cfg->regs, cfg->pcs_tbl_sec, cfg->pcs_tbl_num_sec); in qmp_pcie_power_on()
1975 qmp_pcie_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl, cfg->pcs_misc_tbl_num); in qmp_pcie_power_on()
1976 qmp_pcie_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl_sec, cfg->pcs_misc_tbl_num_sec); in qmp_pcie_power_on()
1980 * This is active low enable signal to power-down PHY. in qmp_pcie_power_on()
1982 qphy_setbits(pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl); in qmp_pcie_power_on()
1984 if (cfg->has_pwrdn_delay) in qmp_pcie_power_on()
1985 usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max); in qmp_pcie_power_on()
1988 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); in qmp_pcie_power_on()
1990 /* start SerDes and Phy-Coding-Sublayer */ in qmp_pcie_power_on()
1991 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); in qmp_pcie_power_on()
1993 status = pcs + cfg->regs[QPHY_PCS_STATUS]; in qmp_pcie_power_on()
1994 mask = cfg->phy_status; in qmp_pcie_power_on()
2000 dev_err(qmp->dev, "phy initialization timed-out\n"); in qmp_pcie_power_on()
2007 clk_disable_unprepare(qphy->pipe_clk); in qmp_pcie_power_on()
2015 const struct qmp_phy_cfg *cfg = qphy->cfg; in qmp_pcie_power_off()
2017 clk_disable_unprepare(qphy->pipe_clk); in qmp_pcie_power_off()
2020 qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); in qmp_pcie_power_off()
2022 /* stop SerDes and Phy-Coding-Sublayer */ in qmp_pcie_power_off()
2023 qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); in qmp_pcie_power_off()
2026 if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) { in qmp_pcie_power_off()
2027 qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], in qmp_pcie_power_off()
2028 cfg->pwrdn_ctrl); in qmp_pcie_power_off()
2030 qphy_clrbits(qphy->pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL, in qmp_pcie_power_off()
2031 cfg->pwrdn_ctrl); in qmp_pcie_power_off()
2066 int num = cfg->num_vregs; in qmp_pcie_vreg_init()
2069 qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL); in qmp_pcie_vreg_init()
2070 if (!qmp->vregs) in qmp_pcie_vreg_init()
2071 return -ENOMEM; in qmp_pcie_vreg_init()
2074 qmp->vregs[i].supply = cfg->vreg_list[i]; in qmp_pcie_vreg_init()
2076 return devm_regulator_bulk_get(dev, num, qmp->vregs); in qmp_pcie_vreg_init()
2085 qmp->resets = devm_kcalloc(dev, cfg->num_resets, in qmp_pcie_reset_init()
2086 sizeof(*qmp->resets), GFP_KERNEL); in qmp_pcie_reset_init()
2087 if (!qmp->resets) in qmp_pcie_reset_init()
2088 return -ENOMEM; in qmp_pcie_reset_init()
2090 for (i = 0; i < cfg->num_resets; i++) in qmp_pcie_reset_init()
2091 qmp->resets[i].id = cfg->reset_list[i]; in qmp_pcie_reset_init()
2093 ret = devm_reset_control_bulk_get_exclusive(dev, cfg->num_resets, qmp->resets); in qmp_pcie_reset_init()
2103 int num = cfg->num_clks; in qmp_pcie_clk_init()
2106 qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL); in qmp_pcie_clk_init()
2107 if (!qmp->clks) in qmp_pcie_clk_init()
2108 return -ENOMEM; in qmp_pcie_clk_init()
2111 qmp->clks[i].id = cfg->clk_list[i]; in qmp_pcie_clk_init()
2113 return devm_clk_bulk_get(dev, num, qmp->clks); in qmp_pcie_clk_init()
2124 * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate
2125 * controls it. The <s>_pipe_clk coming out of the GCC is requested
2127 * We register the <s>_pipe_clksrc here. The gcc driver takes care
2131 * +---------------+
2132 * | PHY block |<<---------------------------------------+
2134 * | +-------+ | +-----+ |
2135 * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+
2136 * clk | +-------+ | +-----+
2137 * +---------------+
2145 ret = of_property_read_string(np, "clock-output-names", &init.name); in phy_pipe_clk_register()
2147 dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np); in phy_pipe_clk_register()
2151 fixed = devm_kzalloc(qmp->dev, sizeof(*fixed), GFP_KERNEL); in phy_pipe_clk_register()
2153 return -ENOMEM; in phy_pipe_clk_register()
2158 * Controllers using QMP PHY-s use 125MHz pipe clock interface in phy_pipe_clk_register()
2161 if (qmp->phys[0]->cfg->pipe_clock_rate) in phy_pipe_clk_register()
2162 fixed->fixed_rate = qmp->phys[0]->cfg->pipe_clock_rate; in phy_pipe_clk_register()
2164 fixed->fixed_rate = 125000000; in phy_pipe_clk_register()
2166 fixed->hw.init = &init; in phy_pipe_clk_register()
2168 ret = devm_clk_hw_register(qmp->dev, &fixed->hw); in phy_pipe_clk_register()
2172 ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw); in phy_pipe_clk_register()
2180 return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np); in phy_pipe_clk_register()
2199 return -ENOMEM; in qmp_pcie_create()
2201 qphy->cfg = cfg; in qmp_pcie_create()
2202 qphy->serdes = serdes; in qmp_pcie_create()
2205 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2. in qmp_pcie_create()
2206 * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5 in qmp_pcie_create()
2207 * For single lane PHYs: pcs_misc (optional) -> 3. in qmp_pcie_create()
2209 qphy->tx = devm_of_iomap(dev, np, 0, NULL); in qmp_pcie_create()
2210 if (IS_ERR(qphy->tx)) in qmp_pcie_create()
2211 return PTR_ERR(qphy->tx); in qmp_pcie_create()
2213 if (of_device_is_compatible(dev->of_node, "qcom,sdm845-qhp-pcie-phy")) in qmp_pcie_create()
2214 qphy->rx = qphy->tx; in qmp_pcie_create()
2216 qphy->rx = devm_of_iomap(dev, np, 1, NULL); in qmp_pcie_create()
2217 if (IS_ERR(qphy->rx)) in qmp_pcie_create()
2218 return PTR_ERR(qphy->rx); in qmp_pcie_create()
2220 qphy->pcs = devm_of_iomap(dev, np, 2, NULL); in qmp_pcie_create()
2221 if (IS_ERR(qphy->pcs)) in qmp_pcie_create()
2222 return PTR_ERR(qphy->pcs); in qmp_pcie_create()
2224 if (cfg->lanes >= 2) { in qmp_pcie_create()
2225 qphy->tx2 = devm_of_iomap(dev, np, 3, NULL); in qmp_pcie_create()
2226 if (IS_ERR(qphy->tx2)) in qmp_pcie_create()
2227 return PTR_ERR(qphy->tx2); in qmp_pcie_create()
2229 qphy->rx2 = devm_of_iomap(dev, np, 4, NULL); in qmp_pcie_create()
2230 if (IS_ERR(qphy->rx2)) in qmp_pcie_create()
2231 return PTR_ERR(qphy->rx2); in qmp_pcie_create()
2233 qphy->pcs_misc = devm_of_iomap(dev, np, 5, NULL); in qmp_pcie_create()
2235 qphy->pcs_misc = devm_of_iomap(dev, np, 3, NULL); in qmp_pcie_create()
2238 if (IS_ERR(qphy->pcs_misc) && in qmp_pcie_create()
2239 of_device_is_compatible(dev->of_node, "qcom,ipq6018-qmp-pcie-phy")) in qmp_pcie_create()
2240 qphy->pcs_misc = qphy->pcs + 0x400; in qmp_pcie_create()
2242 if (IS_ERR(qphy->pcs_misc)) { in qmp_pcie_create()
2243 if (cfg->pcs_misc_tbl || cfg->pcs_misc_tbl_sec) in qmp_pcie_create()
2244 return PTR_ERR(qphy->pcs_misc); in qmp_pcie_create()
2247 qphy->pipe_clk = devm_get_clk_from_child(dev, np, NULL); in qmp_pcie_create()
2248 if (IS_ERR(qphy->pipe_clk)) { in qmp_pcie_create()
2249 return dev_err_probe(dev, PTR_ERR(qphy->pipe_clk), in qmp_pcie_create()
2260 qphy->phy = generic_phy; in qmp_pcie_create()
2261 qphy->qmp = qmp; in qmp_pcie_create()
2262 qmp->phys[id] = qphy; in qmp_pcie_create()
2270 .compatible = "qcom,msm8998-qmp-pcie-phy",
2273 .compatible = "qcom,ipq8074-qmp-pcie-phy",
2276 .compatible = "qcom,ipq8074-qmp-gen3-pcie-phy",
2279 .compatible = "qcom,ipq6018-qmp-pcie-phy",
2282 .compatible = "qcom,sc8180x-qmp-pcie-phy",
2285 .compatible = "qcom,sdm845-qhp-pcie-phy",
2288 .compatible = "qcom,sdm845-qmp-pcie-phy",
2291 .compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy",
2294 .compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy",
2297 .compatible = "qcom,sm8250-qmp-modem-pcie-phy",
2300 .compatible = "qcom,sdx55-qmp-pcie-phy",
2303 .compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy",
2306 .compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy",
2316 struct device *dev = &pdev->dev; in qmp_pcie_probe()
2326 return -ENOMEM; in qmp_pcie_probe()
2328 qmp->dev = dev; in qmp_pcie_probe()
2334 return -EINVAL; in qmp_pcie_probe()
2354 num = of_get_available_child_count(dev->of_node); in qmp_pcie_probe()
2357 return -EINVAL; in qmp_pcie_probe()
2359 qmp->phys = devm_kcalloc(dev, num, sizeof(*qmp->phys), GFP_KERNEL); in qmp_pcie_probe()
2360 if (!qmp->phys) in qmp_pcie_probe()
2361 return -ENOMEM; in qmp_pcie_probe()
2364 for_each_available_child_of_node(dev->of_node, child) { in qmp_pcie_probe()
2365 /* Create per-lane phy */ in qmp_pcie_probe()
2379 dev_err(qmp->dev, in qmp_pcie_probe()
2399 .name = "qcom-qmp-pcie-phy",