Lines Matching refs:pcs
915 void __iomem *pcs; member
1426 qphy->pcs + QSERDES_DP_PHY_PD_CTL); in qcom_qmp_v3_phy_dp_aux_init()
1433 writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL); in qcom_qmp_v3_phy_dp_aux_init()
1439 qphy->pcs + QSERDES_DP_PHY_PD_CTL); in qcom_qmp_v3_phy_dp_aux_init()
1447 writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0); in qcom_qmp_v3_phy_dp_aux_init()
1448 writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1); in qcom_qmp_v3_phy_dp_aux_init()
1449 writel(0x24, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2); in qcom_qmp_v3_phy_dp_aux_init()
1450 writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3); in qcom_qmp_v3_phy_dp_aux_init()
1451 writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4); in qcom_qmp_v3_phy_dp_aux_init()
1452 writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5); in qcom_qmp_v3_phy_dp_aux_init()
1453 writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6); in qcom_qmp_v3_phy_dp_aux_init()
1454 writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7); in qcom_qmp_v3_phy_dp_aux_init()
1455 writel(0xbb, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8); in qcom_qmp_v3_phy_dp_aux_init()
1456 writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9); in qcom_qmp_v3_phy_dp_aux_init()
1462 qphy->pcs + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK); in qcom_qmp_v3_phy_dp_aux_init()
1549 writel(val, qphy->pcs + QSERDES_DP_PHY_PD_CTL); in qmp_combo_configure_dp_mode()
1551 writel(0x5c, qphy->pcs + QSERDES_DP_PHY_MODE); in qmp_combo_configure_dp_mode()
1565 writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL); in qcom_qmp_v3_phy_configure_dp_phy()
1566 writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL); in qcom_qmp_v3_phy_configure_dp_phy()
1589 writel(phy_vco_div, qphy->pcs + QSERDES_V3_DP_PHY_VCO_DIV); in qcom_qmp_v3_phy_configure_dp_phy()
1594 writel(0x04, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2); in qcom_qmp_v3_phy_configure_dp_phy()
1595 writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG); in qcom_qmp_v3_phy_configure_dp_phy()
1596 writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG); in qcom_qmp_v3_phy_configure_dp_phy()
1597 writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG); in qcom_qmp_v3_phy_configure_dp_phy()
1598 writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG); in qcom_qmp_v3_phy_configure_dp_phy()
1609 writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG); in qcom_qmp_v3_phy_configure_dp_phy()
1611 if (readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS, in qcom_qmp_v3_phy_configure_dp_phy()
1618 writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG); in qcom_qmp_v3_phy_configure_dp_phy()
1620 writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG); in qcom_qmp_v3_phy_configure_dp_phy()
1622 return readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS, in qcom_qmp_v3_phy_configure_dp_phy()
1642 writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1); in qcom_qmp_v3_dp_phy_calibrate()
1651 qphy->pcs + QSERDES_DP_PHY_PD_CTL); in qcom_qmp_v4_phy_dp_aux_init()
1656 writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0); in qcom_qmp_v4_phy_dp_aux_init()
1657 writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1); in qcom_qmp_v4_phy_dp_aux_init()
1658 writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2); in qcom_qmp_v4_phy_dp_aux_init()
1659 writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3); in qcom_qmp_v4_phy_dp_aux_init()
1660 writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4); in qcom_qmp_v4_phy_dp_aux_init()
1661 writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5); in qcom_qmp_v4_phy_dp_aux_init()
1662 writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6); in qcom_qmp_v4_phy_dp_aux_init()
1663 writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7); in qcom_qmp_v4_phy_dp_aux_init()
1664 writel(0xb7, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8); in qcom_qmp_v4_phy_dp_aux_init()
1665 writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9); in qcom_qmp_v4_phy_dp_aux_init()
1671 qphy->pcs + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK); in qcom_qmp_v4_phy_dp_aux_init()
1694 writel(0x0f, qphy->pcs + QSERDES_V4_DP_PHY_CFG_1); in qcom_qmp_v45_phy_configure_dp_phy()
1698 writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1); in qcom_qmp_v45_phy_configure_dp_phy()
1699 writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2); in qcom_qmp_v45_phy_configure_dp_phy()
1701 writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL); in qcom_qmp_v45_phy_configure_dp_phy()
1702 writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL); in qcom_qmp_v45_phy_configure_dp_phy()
1725 writel(phy_vco_div, qphy->pcs + QSERDES_V4_DP_PHY_VCO_DIV); in qcom_qmp_v45_phy_configure_dp_phy()
1730 writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG); in qcom_qmp_v45_phy_configure_dp_phy()
1731 writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG); in qcom_qmp_v45_phy_configure_dp_phy()
1732 writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG); in qcom_qmp_v45_phy_configure_dp_phy()
1733 writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG); in qcom_qmp_v45_phy_configure_dp_phy()
1758 writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG); in qcom_qmp_v45_phy_configure_dp_phy()
1760 if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS, in qcom_qmp_v45_phy_configure_dp_phy()
1767 if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS, in qcom_qmp_v45_phy_configure_dp_phy()
1816 writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG); in qcom_qmp_v4_phy_configure_dp_phy()
1818 writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG); in qcom_qmp_v4_phy_configure_dp_phy()
1820 if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS, in qcom_qmp_v4_phy_configure_dp_phy()
1873 writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG); in qcom_qmp_v5_phy_configure_dp_phy()
1875 writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG); in qcom_qmp_v5_phy_configure_dp_phy()
1877 if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS, in qcom_qmp_v5_phy_configure_dp_phy()
1909 writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1); in qcom_qmp_v4_dp_phy_calibrate()
1944 void __iomem *pcs = qphy->pcs; in qmp_combo_com_init() local
1998 qphy_setbits(pcs, in qmp_combo_com_init()
2002 qphy_setbits(pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL, in qmp_combo_com_init()
2068 void __iomem *pcs = qphy->pcs; in qmp_combo_power_on() local
2104 qmp_combo_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num); in qmp_combo_power_on()
2115 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); in qmp_combo_power_on()
2117 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); in qmp_combo_power_on()
2119 status = pcs + cfg->regs[QPHY_PCS_STATUS]; in qmp_combo_power_on()
2147 writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL); in qmp_combo_power_off()
2150 qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); in qmp_combo_power_off()
2153 qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); in qmp_combo_power_off()
2157 qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], in qmp_combo_power_off()
2160 qphy_clrbits(qphy->pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL, in qmp_combo_power_off()
2214 void __iomem *pcs_usb = qphy->pcs_usb ?: qphy->pcs; in qmp_combo_enable_autonomous_mode()
2243 void __iomem *pcs_usb = qphy->pcs_usb ?: qphy->pcs; in qmp_combo_disable_autonomous_mode()
2685 qphy->pcs = devm_of_iomap(dev, np, 2, NULL); in qmp_combo_create()
2686 if (IS_ERR(qphy->pcs)) in qmp_combo_create()
2687 return PTR_ERR(qphy->pcs); in qmp_combo_create()
2690 qphy->pcs_usb = qphy->pcs + cfg->pcs_usb_offset; in qmp_combo_create()