Lines Matching +full:sm8250 +full:- +full:dispcc
1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
23 #include <dt-bindings/phy/phy.h>
25 #include "phy-qcom-qmp.h"
74 * if yes, then offset gives index in the reg-layout
106 /* set of registers with offsets different per-PHY */
753 { .name = "vdda-phy", .enable_load = 21800 },
754 { .name = "vdda-pll", .enable_load = 36000 },
815 /* struct qmp_phy_cfg - per-PHY initialization config */
817 /* phy-type - PCIE/UFS/USB */
821 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
890 * struct qmp_phy - per-lane phy descriptor
935 * struct qcom_qmp - structure holding QMP phy block attributes
944 * @phys: array of per-lane phy descriptors
1010 /* the primary usb3 phy on sm8250 doesn't have a ref clock */
1363 if (!(t->lane_mask & lane_mask)) in qmp_combo_configure_lane()
1366 if (t->in_layout) in qmp_combo_configure_lane()
1367 writel(t->val, base + regs[t->offset]); in qmp_combo_configure_lane()
1369 writel(t->val, base + t->offset); in qmp_combo_configure_lane()
1383 const struct qmp_phy_cfg *cfg = qphy->cfg; in qmp_combo_serdes_init()
1384 void __iomem *serdes = qphy->serdes; in qmp_combo_serdes_init()
1385 const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; in qmp_combo_serdes_init()
1386 const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl; in qmp_combo_serdes_init()
1387 int serdes_tbl_num = cfg->serdes_tbl_num; in qmp_combo_serdes_init()
1389 qmp_combo_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num); in qmp_combo_serdes_init()
1391 if (cfg->type == PHY_TYPE_DP) { in qmp_combo_serdes_init()
1392 switch (dp_opts->link_rate) { in qmp_combo_serdes_init()
1394 qmp_combo_configure(serdes, cfg->regs, in qmp_combo_serdes_init()
1395 cfg->serdes_tbl_rbr, in qmp_combo_serdes_init()
1396 cfg->serdes_tbl_rbr_num); in qmp_combo_serdes_init()
1399 qmp_combo_configure(serdes, cfg->regs, in qmp_combo_serdes_init()
1400 cfg->serdes_tbl_hbr, in qmp_combo_serdes_init()
1401 cfg->serdes_tbl_hbr_num); in qmp_combo_serdes_init()
1404 qmp_combo_configure(serdes, cfg->regs, in qmp_combo_serdes_init()
1405 cfg->serdes_tbl_hbr2, in qmp_combo_serdes_init()
1406 cfg->serdes_tbl_hbr2_num); in qmp_combo_serdes_init()
1409 qmp_combo_configure(serdes, cfg->regs, in qmp_combo_serdes_init()
1410 cfg->serdes_tbl_hbr3, in qmp_combo_serdes_init()
1411 cfg->serdes_tbl_hbr3_num); in qmp_combo_serdes_init()
1415 return -EINVAL; in qmp_combo_serdes_init()
1426 qphy->pcs + QSERDES_DP_PHY_PD_CTL); in qcom_qmp_v3_phy_dp_aux_init()
1431 qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN); in qcom_qmp_v3_phy_dp_aux_init()
1433 writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL); in qcom_qmp_v3_phy_dp_aux_init()
1439 qphy->pcs + QSERDES_DP_PHY_PD_CTL); in qcom_qmp_v3_phy_dp_aux_init()
1445 qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN); in qcom_qmp_v3_phy_dp_aux_init()
1447 writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0); in qcom_qmp_v3_phy_dp_aux_init()
1448 writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1); in qcom_qmp_v3_phy_dp_aux_init()
1449 writel(0x24, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2); in qcom_qmp_v3_phy_dp_aux_init()
1450 writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3); in qcom_qmp_v3_phy_dp_aux_init()
1451 writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4); in qcom_qmp_v3_phy_dp_aux_init()
1452 writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5); in qcom_qmp_v3_phy_dp_aux_init()
1453 writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6); in qcom_qmp_v3_phy_dp_aux_init()
1454 writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7); in qcom_qmp_v3_phy_dp_aux_init()
1455 writel(0xbb, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8); in qcom_qmp_v3_phy_dp_aux_init()
1456 writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9); in qcom_qmp_v3_phy_dp_aux_init()
1457 qphy->dp_aux_cfg = 0; in qcom_qmp_v3_phy_dp_aux_init()
1462 qphy->pcs + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK); in qcom_qmp_v3_phy_dp_aux_init()
1468 const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; in qmp_combo_configure_dp_swing()
1469 const struct qmp_phy_cfg *cfg = qphy->cfg; in qmp_combo_configure_dp_swing()
1474 for (i = 0; i < dp_opts->lanes; i++) { in qmp_combo_configure_dp_swing()
1475 v_level = max(v_level, dp_opts->voltage[i]); in qmp_combo_configure_dp_swing()
1476 p_level = max(p_level, dp_opts->pre[i]); in qmp_combo_configure_dp_swing()
1479 if (dp_opts->link_rate <= 2700) { in qmp_combo_configure_dp_swing()
1480 voltage_swing_cfg = (*cfg->swing_hbr_rbr)[v_level][p_level]; in qmp_combo_configure_dp_swing()
1481 pre_emphasis_cfg = (*cfg->pre_emphasis_hbr_rbr)[v_level][p_level]; in qmp_combo_configure_dp_swing()
1483 voltage_swing_cfg = (*cfg->swing_hbr3_hbr2)[v_level][p_level]; in qmp_combo_configure_dp_swing()
1484 pre_emphasis_cfg = (*cfg->pre_emphasis_hbr3_hbr2)[v_level][p_level]; in qmp_combo_configure_dp_swing()
1489 return -EINVAL; in qmp_combo_configure_dp_swing()
1495 writel(voltage_swing_cfg, qphy->tx + drv_lvl_reg); in qmp_combo_configure_dp_swing()
1496 writel(pre_emphasis_cfg, qphy->tx + emp_post_reg); in qmp_combo_configure_dp_swing()
1497 writel(voltage_swing_cfg, qphy->tx2 + drv_lvl_reg); in qmp_combo_configure_dp_swing()
1498 writel(pre_emphasis_cfg, qphy->tx2 + emp_post_reg); in qmp_combo_configure_dp_swing()
1505 const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; in qcom_qmp_v3_phy_configure_dp_tx()
1512 if (dp_opts->lanes == 1) { in qcom_qmp_v3_phy_configure_dp_tx()
1520 writel(drvr_en, qphy->tx + QSERDES_V3_TX_HIGHZ_DRVR_EN); in qcom_qmp_v3_phy_configure_dp_tx()
1521 writel(bias_en, qphy->tx + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN); in qcom_qmp_v3_phy_configure_dp_tx()
1522 writel(drvr_en, qphy->tx2 + QSERDES_V3_TX_HIGHZ_DRVR_EN); in qcom_qmp_v3_phy_configure_dp_tx()
1523 writel(bias_en, qphy->tx2 + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN); in qcom_qmp_v3_phy_configure_dp_tx()
1536 * use type-c connector to understand orientation and lanes. in qmp_combo_configure_dp_mode()
1539 * the orientation of the type-c cable. in qmp_combo_configure_dp_mode()
1546 * writel(0x4c, qphy->pcs + QSERDES_V3_DP_PHY_MODE); in qmp_combo_configure_dp_mode()
1549 writel(val, qphy->pcs + QSERDES_DP_PHY_PD_CTL); in qmp_combo_configure_dp_mode()
1551 writel(0x5c, qphy->pcs + QSERDES_DP_PHY_MODE); in qmp_combo_configure_dp_mode()
1558 const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks; in qcom_qmp_v3_phy_configure_dp_phy()
1559 const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; in qcom_qmp_v3_phy_configure_dp_phy()
1565 writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL); in qcom_qmp_v3_phy_configure_dp_phy()
1566 writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL); in qcom_qmp_v3_phy_configure_dp_phy()
1568 switch (dp_opts->link_rate) { in qcom_qmp_v3_phy_configure_dp_phy()
1587 return -EINVAL; in qcom_qmp_v3_phy_configure_dp_phy()
1589 writel(phy_vco_div, qphy->pcs + QSERDES_V3_DP_PHY_VCO_DIV); in qcom_qmp_v3_phy_configure_dp_phy()
1591 clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000); in qcom_qmp_v3_phy_configure_dp_phy()
1592 clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq); in qcom_qmp_v3_phy_configure_dp_phy()
1594 writel(0x04, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2); in qcom_qmp_v3_phy_configure_dp_phy()
1595 writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG); in qcom_qmp_v3_phy_configure_dp_phy()
1596 writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG); in qcom_qmp_v3_phy_configure_dp_phy()
1597 writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG); in qcom_qmp_v3_phy_configure_dp_phy()
1598 writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG); in qcom_qmp_v3_phy_configure_dp_phy()
1600 writel(0x20, qphy->serdes + QSERDES_V3_COM_RESETSM_CNTRL); in qcom_qmp_v3_phy_configure_dp_phy()
1602 if (readl_poll_timeout(qphy->serdes + QSERDES_V3_COM_C_READY_STATUS, in qcom_qmp_v3_phy_configure_dp_phy()
1607 return -ETIMEDOUT; in qcom_qmp_v3_phy_configure_dp_phy()
1609 writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG); in qcom_qmp_v3_phy_configure_dp_phy()
1611 if (readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS, in qcom_qmp_v3_phy_configure_dp_phy()
1616 return -ETIMEDOUT; in qcom_qmp_v3_phy_configure_dp_phy()
1618 writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG); in qcom_qmp_v3_phy_configure_dp_phy()
1620 writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG); in qcom_qmp_v3_phy_configure_dp_phy()
1622 return readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS, in qcom_qmp_v3_phy_configure_dp_phy()
1638 qphy->dp_aux_cfg++; in qcom_qmp_v3_dp_phy_calibrate()
1639 qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings); in qcom_qmp_v3_dp_phy_calibrate()
1640 val = cfg1_settings[qphy->dp_aux_cfg]; in qcom_qmp_v3_dp_phy_calibrate()
1642 writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1); in qcom_qmp_v3_dp_phy_calibrate()
1651 qphy->pcs + QSERDES_DP_PHY_PD_CTL); in qcom_qmp_v4_phy_dp_aux_init()
1654 writel(0x17, qphy->serdes + QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN); in qcom_qmp_v4_phy_dp_aux_init()
1656 writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0); in qcom_qmp_v4_phy_dp_aux_init()
1657 writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1); in qcom_qmp_v4_phy_dp_aux_init()
1658 writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2); in qcom_qmp_v4_phy_dp_aux_init()
1659 writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3); in qcom_qmp_v4_phy_dp_aux_init()
1660 writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4); in qcom_qmp_v4_phy_dp_aux_init()
1661 writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5); in qcom_qmp_v4_phy_dp_aux_init()
1662 writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6); in qcom_qmp_v4_phy_dp_aux_init()
1663 writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7); in qcom_qmp_v4_phy_dp_aux_init()
1664 writel(0xb7, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8); in qcom_qmp_v4_phy_dp_aux_init()
1665 writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9); in qcom_qmp_v4_phy_dp_aux_init()
1666 qphy->dp_aux_cfg = 0; in qcom_qmp_v4_phy_dp_aux_init()
1671 qphy->pcs + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK); in qcom_qmp_v4_phy_dp_aux_init()
1677 writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL); in qcom_qmp_v4_phy_configure_dp_tx()
1678 writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL); in qcom_qmp_v4_phy_configure_dp_tx()
1680 writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL); in qcom_qmp_v4_phy_configure_dp_tx()
1681 writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL); in qcom_qmp_v4_phy_configure_dp_tx()
1689 const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks; in qcom_qmp_v45_phy_configure_dp_phy()
1690 const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; in qcom_qmp_v45_phy_configure_dp_phy()
1694 writel(0x0f, qphy->pcs + QSERDES_V4_DP_PHY_CFG_1); in qcom_qmp_v45_phy_configure_dp_phy()
1698 writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1); in qcom_qmp_v45_phy_configure_dp_phy()
1699 writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2); in qcom_qmp_v45_phy_configure_dp_phy()
1701 writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL); in qcom_qmp_v45_phy_configure_dp_phy()
1702 writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL); in qcom_qmp_v45_phy_configure_dp_phy()
1704 switch (dp_opts->link_rate) { in qcom_qmp_v45_phy_configure_dp_phy()
1723 return -EINVAL; in qcom_qmp_v45_phy_configure_dp_phy()
1725 writel(phy_vco_div, qphy->pcs + QSERDES_V4_DP_PHY_VCO_DIV); in qcom_qmp_v45_phy_configure_dp_phy()
1727 clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000); in qcom_qmp_v45_phy_configure_dp_phy()
1728 clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq); in qcom_qmp_v45_phy_configure_dp_phy()
1730 writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG); in qcom_qmp_v45_phy_configure_dp_phy()
1731 writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG); in qcom_qmp_v45_phy_configure_dp_phy()
1732 writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG); in qcom_qmp_v45_phy_configure_dp_phy()
1733 writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG); in qcom_qmp_v45_phy_configure_dp_phy()
1735 writel(0x20, qphy->serdes + QSERDES_V4_COM_RESETSM_CNTRL); in qcom_qmp_v45_phy_configure_dp_phy()
1737 if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_C_READY_STATUS, in qcom_qmp_v45_phy_configure_dp_phy()
1742 return -ETIMEDOUT; in qcom_qmp_v45_phy_configure_dp_phy()
1744 if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS, in qcom_qmp_v45_phy_configure_dp_phy()
1749 return -ETIMEDOUT; in qcom_qmp_v45_phy_configure_dp_phy()
1751 if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS, in qcom_qmp_v45_phy_configure_dp_phy()
1756 return -ETIMEDOUT; in qcom_qmp_v45_phy_configure_dp_phy()
1758 writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG); in qcom_qmp_v45_phy_configure_dp_phy()
1760 if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS, in qcom_qmp_v45_phy_configure_dp_phy()
1765 return -ETIMEDOUT; in qcom_qmp_v45_phy_configure_dp_phy()
1767 if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS, in qcom_qmp_v45_phy_configure_dp_phy()
1772 return -ETIMEDOUT; in qcom_qmp_v45_phy_configure_dp_phy()
1779 const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; in qcom_qmp_v4_phy_configure_dp_phy()
1794 if (dp_opts->lanes == 1) { in qcom_qmp_v4_phy_configure_dp_phy()
1799 } else if (dp_opts->lanes == 2) { in qcom_qmp_v4_phy_configure_dp_phy()
1811 writel(drvr0_en, qphy->tx + QSERDES_V4_TX_HIGHZ_DRVR_EN); in qcom_qmp_v4_phy_configure_dp_phy()
1812 writel(bias0_en, qphy->tx + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN); in qcom_qmp_v4_phy_configure_dp_phy()
1813 writel(drvr1_en, qphy->tx2 + QSERDES_V4_TX_HIGHZ_DRVR_EN); in qcom_qmp_v4_phy_configure_dp_phy()
1814 writel(bias1_en, qphy->tx2 + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN); in qcom_qmp_v4_phy_configure_dp_phy()
1816 writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG); in qcom_qmp_v4_phy_configure_dp_phy()
1818 writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG); in qcom_qmp_v4_phy_configure_dp_phy()
1820 if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS, in qcom_qmp_v4_phy_configure_dp_phy()
1825 return -ETIMEDOUT; in qcom_qmp_v4_phy_configure_dp_phy()
1827 writel(0x0a, qphy->tx + QSERDES_V4_TX_TX_POL_INV); in qcom_qmp_v4_phy_configure_dp_phy()
1828 writel(0x0a, qphy->tx2 + QSERDES_V4_TX_TX_POL_INV); in qcom_qmp_v4_phy_configure_dp_phy()
1830 writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL); in qcom_qmp_v4_phy_configure_dp_phy()
1831 writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL); in qcom_qmp_v4_phy_configure_dp_phy()
1833 writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL); in qcom_qmp_v4_phy_configure_dp_phy()
1834 writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL); in qcom_qmp_v4_phy_configure_dp_phy()
1841 const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; in qcom_qmp_v5_phy_configure_dp_phy()
1851 if (dp_opts->lanes == 1) { in qcom_qmp_v5_phy_configure_dp_phy()
1856 } else if (dp_opts->lanes == 2) { in qcom_qmp_v5_phy_configure_dp_phy()
1868 writel(drvr0_en, qphy->tx + QSERDES_V5_5NM_TX_HIGHZ_DRVR_EN); in qcom_qmp_v5_phy_configure_dp_phy()
1869 writel(bias0_en, qphy->tx + QSERDES_V5_5NM_TX_TRANSCEIVER_BIAS_EN); in qcom_qmp_v5_phy_configure_dp_phy()
1870 writel(drvr1_en, qphy->tx2 + QSERDES_V5_5NM_TX_HIGHZ_DRVR_EN); in qcom_qmp_v5_phy_configure_dp_phy()
1871 writel(bias1_en, qphy->tx2 + QSERDES_V5_5NM_TX_TRANSCEIVER_BIAS_EN); in qcom_qmp_v5_phy_configure_dp_phy()
1873 writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG); in qcom_qmp_v5_phy_configure_dp_phy()
1875 writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG); in qcom_qmp_v5_phy_configure_dp_phy()
1877 if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS, in qcom_qmp_v5_phy_configure_dp_phy()
1882 return -ETIMEDOUT; in qcom_qmp_v5_phy_configure_dp_phy()
1884 writel(0x0a, qphy->tx + QSERDES_V5_5NM_TX_TX_POL_INV); in qcom_qmp_v5_phy_configure_dp_phy()
1885 writel(0x0a, qphy->tx2 + QSERDES_V5_5NM_TX_TX_POL_INV); in qcom_qmp_v5_phy_configure_dp_phy()
1887 writel(0x27, qphy->tx + QSERDES_V5_5NM_TX_TX_DRV_LVL); in qcom_qmp_v5_phy_configure_dp_phy()
1888 writel(0x27, qphy->tx2 + QSERDES_V5_5NM_TX_TX_DRV_LVL); in qcom_qmp_v5_phy_configure_dp_phy()
1890 writel(0x20, qphy->tx + QSERDES_V5_5NM_TX_TX_EMP_POST1_LVL); in qcom_qmp_v5_phy_configure_dp_phy()
1891 writel(0x20, qphy->tx2 + QSERDES_V5_5NM_TX_TX_EMP_POST1_LVL); in qcom_qmp_v5_phy_configure_dp_phy()
1905 qphy->dp_aux_cfg++; in qcom_qmp_v4_dp_phy_calibrate()
1906 qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings); in qcom_qmp_v4_dp_phy_calibrate()
1907 val = cfg1_settings[qphy->dp_aux_cfg]; in qcom_qmp_v4_dp_phy_calibrate()
1909 writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1); in qcom_qmp_v4_dp_phy_calibrate()
1916 const struct phy_configure_opts_dp *dp_opts = &opts->dp; in qcom_qmp_dp_phy_configure()
1918 const struct qmp_phy_cfg *cfg = qphy->cfg; in qcom_qmp_dp_phy_configure()
1920 memcpy(&qphy->dp_opts, dp_opts, sizeof(*dp_opts)); in qcom_qmp_dp_phy_configure()
1921 if (qphy->dp_opts.set_voltages) { in qcom_qmp_dp_phy_configure()
1922 cfg->configure_dp_tx(qphy); in qcom_qmp_dp_phy_configure()
1923 qphy->dp_opts.set_voltages = 0; in qcom_qmp_dp_phy_configure()
1932 const struct qmp_phy_cfg *cfg = qphy->cfg; in qcom_qmp_dp_phy_calibrate()
1934 if (cfg->calibrate_dp_phy) in qcom_qmp_dp_phy_calibrate()
1935 return cfg->calibrate_dp_phy(qphy); in qcom_qmp_dp_phy_calibrate()
1942 struct qcom_qmp *qmp = qphy->qmp; in qmp_combo_com_init()
1943 const struct qmp_phy_cfg *cfg = qphy->cfg; in qmp_combo_com_init()
1944 void __iomem *pcs = qphy->pcs; in qmp_combo_com_init()
1945 void __iomem *dp_com = qmp->dp_com; in qmp_combo_com_init()
1948 mutex_lock(&qmp->phy_mutex); in qmp_combo_com_init()
1949 if (qmp->init_count++) { in qmp_combo_com_init()
1950 mutex_unlock(&qmp->phy_mutex); in qmp_combo_com_init()
1955 ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs); in qmp_combo_com_init()
1957 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret); in qmp_combo_com_init()
1961 ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets); in qmp_combo_com_init()
1963 dev_err(qmp->dev, "reset assert failed\n"); in qmp_combo_com_init()
1967 ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets); in qmp_combo_com_init()
1969 dev_err(qmp->dev, "reset deassert failed\n"); in qmp_combo_com_init()
1973 ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks); in qmp_combo_com_init()
1984 /* Default type-c orientation, i.e CC1 */ in qmp_combo_com_init()
1997 if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) in qmp_combo_com_init()
1999 cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], in qmp_combo_com_init()
2000 cfg->pwrdn_ctrl); in qmp_combo_com_init()
2003 cfg->pwrdn_ctrl); in qmp_combo_com_init()
2005 mutex_unlock(&qmp->phy_mutex); in qmp_combo_com_init()
2010 reset_control_bulk_assert(cfg->num_resets, qmp->resets); in qmp_combo_com_init()
2012 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); in qmp_combo_com_init()
2014 mutex_unlock(&qmp->phy_mutex); in qmp_combo_com_init()
2021 struct qcom_qmp *qmp = qphy->qmp; in qmp_combo_com_exit()
2022 const struct qmp_phy_cfg *cfg = qphy->cfg; in qmp_combo_com_exit()
2024 mutex_lock(&qmp->phy_mutex); in qmp_combo_com_exit()
2025 if (--qmp->init_count) { in qmp_combo_com_exit()
2026 mutex_unlock(&qmp->phy_mutex); in qmp_combo_com_exit()
2030 reset_control_assert(qmp->ufs_reset); in qmp_combo_com_exit()
2032 reset_control_bulk_assert(cfg->num_resets, qmp->resets); in qmp_combo_com_exit()
2034 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); in qmp_combo_com_exit()
2036 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); in qmp_combo_com_exit()
2038 mutex_unlock(&qmp->phy_mutex); in qmp_combo_com_exit()
2046 struct qcom_qmp *qmp = qphy->qmp; in qmp_combo_init()
2047 const struct qmp_phy_cfg *cfg = qphy->cfg; in qmp_combo_init()
2049 dev_vdbg(qmp->dev, "Initializing QMP phy\n"); in qmp_combo_init()
2055 if (cfg->type == PHY_TYPE_DP) in qmp_combo_init()
2056 cfg->dp_aux_init(qphy); in qmp_combo_init()
2064 struct qcom_qmp *qmp = qphy->qmp; in qmp_combo_power_on()
2065 const struct qmp_phy_cfg *cfg = qphy->cfg; in qmp_combo_power_on()
2066 void __iomem *tx = qphy->tx; in qmp_combo_power_on()
2067 void __iomem *rx = qphy->rx; in qmp_combo_power_on()
2068 void __iomem *pcs = qphy->pcs; in qmp_combo_power_on()
2075 ret = clk_prepare_enable(qphy->pipe_clk); in qmp_combo_power_on()
2077 dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret); in qmp_combo_power_on()
2082 qmp_combo_configure_lane(tx, cfg->regs, cfg->tx_tbl, cfg->tx_tbl_num, 1); in qmp_combo_power_on()
2084 if (cfg->lanes >= 2) { in qmp_combo_power_on()
2085 qmp_combo_configure_lane(qphy->tx2, cfg->regs, cfg->tx_tbl, in qmp_combo_power_on()
2086 cfg->tx_tbl_num, 2); in qmp_combo_power_on()
2090 if (cfg->type == PHY_TYPE_DP) in qmp_combo_power_on()
2091 cfg->configure_dp_tx(qphy); in qmp_combo_power_on()
2093 qmp_combo_configure_lane(rx, cfg->regs, cfg->rx_tbl, cfg->rx_tbl_num, 1); in qmp_combo_power_on()
2095 if (cfg->lanes >= 2) { in qmp_combo_power_on()
2096 qmp_combo_configure_lane(qphy->rx2, cfg->regs, cfg->rx_tbl, in qmp_combo_power_on()
2097 cfg->rx_tbl_num, 2); in qmp_combo_power_on()
2101 if (cfg->type == PHY_TYPE_DP) in qmp_combo_power_on()
2102 cfg->configure_dp_phy(qphy); in qmp_combo_power_on()
2104 qmp_combo_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num); in qmp_combo_power_on()
2106 ret = reset_control_deassert(qmp->ufs_reset); in qmp_combo_power_on()
2110 if (cfg->has_pwrdn_delay) in qmp_combo_power_on()
2111 usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max); in qmp_combo_power_on()
2113 if (cfg->type != PHY_TYPE_DP) { in qmp_combo_power_on()
2115 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); in qmp_combo_power_on()
2116 /* start SerDes and Phy-Coding-Sublayer */ in qmp_combo_power_on()
2117 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); in qmp_combo_power_on()
2119 status = pcs + cfg->regs[QPHY_PCS_STATUS]; in qmp_combo_power_on()
2120 mask = cfg->phy_status; in qmp_combo_power_on()
2126 dev_err(qmp->dev, "phy initialization timed-out\n"); in qmp_combo_power_on()
2133 clk_disable_unprepare(qphy->pipe_clk); in qmp_combo_power_on()
2141 const struct qmp_phy_cfg *cfg = qphy->cfg; in qmp_combo_power_off()
2143 clk_disable_unprepare(qphy->pipe_clk); in qmp_combo_power_off()
2145 if (cfg->type == PHY_TYPE_DP) { in qmp_combo_power_off()
2147 writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL); in qmp_combo_power_off()
2150 qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); in qmp_combo_power_off()
2152 /* stop SerDes and Phy-Coding-Sublayer */ in qmp_combo_power_off()
2153 qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); in qmp_combo_power_off()
2156 if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) { in qmp_combo_power_off()
2157 qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], in qmp_combo_power_off()
2158 cfg->pwrdn_ctrl); in qmp_combo_power_off()
2160 qphy_clrbits(qphy->pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL, in qmp_combo_power_off()
2161 cfg->pwrdn_ctrl); in qmp_combo_power_off()
2206 qphy->mode = mode; in qmp_combo_set_mode()
2213 const struct qmp_phy_cfg *cfg = qphy->cfg; in qmp_combo_enable_autonomous_mode()
2214 void __iomem *pcs_usb = qphy->pcs_usb ?: qphy->pcs; in qmp_combo_enable_autonomous_mode()
2215 void __iomem *pcs_misc = qphy->pcs_misc; in qmp_combo_enable_autonomous_mode()
2218 if (qphy->mode == PHY_MODE_USB_HOST_SS || in qmp_combo_enable_autonomous_mode()
2219 qphy->mode == PHY_MODE_USB_DEVICE_SS) in qmp_combo_enable_autonomous_mode()
2225 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); in qmp_combo_enable_autonomous_mode()
2227 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); in qmp_combo_enable_autonomous_mode()
2229 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], in qmp_combo_enable_autonomous_mode()
2233 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask); in qmp_combo_enable_autonomous_mode()
2242 const struct qmp_phy_cfg *cfg = qphy->cfg; in qmp_combo_disable_autonomous_mode()
2243 void __iomem *pcs_usb = qphy->pcs_usb ?: qphy->pcs; in qmp_combo_disable_autonomous_mode()
2244 void __iomem *pcs_misc = qphy->pcs_misc; in qmp_combo_disable_autonomous_mode()
2250 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], in qmp_combo_disable_autonomous_mode()
2253 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); in qmp_combo_disable_autonomous_mode()
2255 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); in qmp_combo_disable_autonomous_mode()
2261 struct qmp_phy *qphy = qmp->phys[0]; in qmp_combo_runtime_suspend()
2262 const struct qmp_phy_cfg *cfg = qphy->cfg; in qmp_combo_runtime_suspend()
2264 dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qphy->mode); in qmp_combo_runtime_suspend()
2267 if (cfg->type != PHY_TYPE_USB3) in qmp_combo_runtime_suspend()
2270 if (!qmp->init_count) { in qmp_combo_runtime_suspend()
2277 clk_disable_unprepare(qphy->pipe_clk); in qmp_combo_runtime_suspend()
2278 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); in qmp_combo_runtime_suspend()
2286 struct qmp_phy *qphy = qmp->phys[0]; in qmp_combo_runtime_resume()
2287 const struct qmp_phy_cfg *cfg = qphy->cfg; in qmp_combo_runtime_resume()
2290 dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qphy->mode); in qmp_combo_runtime_resume()
2293 if (cfg->type != PHY_TYPE_USB3) in qmp_combo_runtime_resume()
2296 if (!qmp->init_count) { in qmp_combo_runtime_resume()
2301 ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks); in qmp_combo_runtime_resume()
2305 ret = clk_prepare_enable(qphy->pipe_clk); in qmp_combo_runtime_resume()
2308 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); in qmp_combo_runtime_resume()
2320 int num = cfg->num_vregs; in qmp_combo_vreg_init()
2323 qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL); in qmp_combo_vreg_init()
2324 if (!qmp->vregs) in qmp_combo_vreg_init()
2325 return -ENOMEM; in qmp_combo_vreg_init()
2328 qmp->vregs[i].supply = cfg->vreg_list[i].name; in qmp_combo_vreg_init()
2330 ret = devm_regulator_bulk_get(dev, num, qmp->vregs); in qmp_combo_vreg_init()
2337 ret = regulator_set_load(qmp->vregs[i].consumer, in qmp_combo_vreg_init()
2338 cfg->vreg_list[i].enable_load); in qmp_combo_vreg_init()
2341 qmp->vregs[i].supply); in qmp_combo_vreg_init()
2355 qmp->resets = devm_kcalloc(dev, cfg->num_resets, in qmp_combo_reset_init()
2356 sizeof(*qmp->resets), GFP_KERNEL); in qmp_combo_reset_init()
2357 if (!qmp->resets) in qmp_combo_reset_init()
2358 return -ENOMEM; in qmp_combo_reset_init()
2360 for (i = 0; i < cfg->num_resets; i++) in qmp_combo_reset_init()
2361 qmp->resets[i].id = cfg->reset_list[i]; in qmp_combo_reset_init()
2363 ret = devm_reset_control_bulk_get_exclusive(dev, cfg->num_resets, qmp->resets); in qmp_combo_reset_init()
2373 int num = cfg->num_clks; in qmp_combo_clk_init()
2376 qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL); in qmp_combo_clk_init()
2377 if (!qmp->clks) in qmp_combo_clk_init()
2378 return -ENOMEM; in qmp_combo_clk_init()
2381 qmp->clks[i].id = cfg->clk_list[i]; in qmp_combo_clk_init()
2383 return devm_clk_bulk_get(dev, num, qmp->clks); in qmp_combo_clk_init()
2401 * +---------------+
2402 * | PHY block |<<---------------------------------------+
2404 * | +-------+ | +-----+ |
2405 * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+
2406 * clk | +-------+ | +-----+
2407 * +---------------+
2415 ret = of_property_read_string(np, "clock-output-names", &init.name); in phy_pipe_clk_register()
2417 dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np); in phy_pipe_clk_register()
2421 fixed = devm_kzalloc(qmp->dev, sizeof(*fixed), GFP_KERNEL); in phy_pipe_clk_register()
2423 return -ENOMEM; in phy_pipe_clk_register()
2428 fixed->fixed_rate = 125000000; in phy_pipe_clk_register()
2429 fixed->hw.init = &init; in phy_pipe_clk_register()
2431 ret = devm_clk_hw_register(qmp->dev, &fixed->hw); in phy_pipe_clk_register()
2435 ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw); in phy_pipe_clk_register()
2443 return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np); in phy_pipe_clk_register()
2449 * +------------------------------+
2452 * | +-------------------+ |
2454 * | +---------+---------+ |
2456 * | +----------+-----------+ |
2458 * | +----------+-----------+ |
2459 * +------------------------------+
2461 * +---------<---------v------------>----------+
2463 * +--------v----------------+ |
2466 * +--------+----------------+ |
2470 * Input to DISPCC block |
2475 * +--------<------------+-----------------+---<---+
2477 * +----v---------+ +--------v-----+ +--------v------+
2482 * +-------+------+ +-----+--------+ +--------+------+
2484 * v---->----------v-------------<------v
2486 * +----------+-----------------+
2488 * +---------+------------------+
2491 * Input to DISPCC block
2498 switch (req->rate) { in qcom_qmp_dp_pixel_clk_determine_rate()
2504 return -EINVAL; in qcom_qmp_dp_pixel_clk_determine_rate()
2516 qphy = dp_clks->qphy; in qcom_qmp_dp_pixel_clk_recalc_rate()
2517 dp_opts = &qphy->dp_opts; in qcom_qmp_dp_pixel_clk_recalc_rate()
2519 switch (dp_opts->link_rate) { in qcom_qmp_dp_pixel_clk_recalc_rate()
2541 switch (req->rate) { in qcom_qmp_dp_link_clk_determine_rate()
2548 return -EINVAL; in qcom_qmp_dp_link_clk_determine_rate()
2560 qphy = dp_clks->qphy; in qcom_qmp_dp_link_clk_recalc_rate()
2561 dp_opts = &qphy->dp_opts; in qcom_qmp_dp_link_clk_recalc_rate()
2563 switch (dp_opts->link_rate) { in qcom_qmp_dp_link_clk_recalc_rate()
2568 return dp_opts->link_rate * 100000; in qcom_qmp_dp_link_clk_recalc_rate()
2583 unsigned int idx = clkspec->args[0]; in qcom_qmp_dp_clks_hw_get()
2587 return ERR_PTR(-EINVAL); in qcom_qmp_dp_clks_hw_get()
2591 return &dp_clks->dp_link_hw; in qcom_qmp_dp_clks_hw_get()
2593 return &dp_clks->dp_pixel_hw; in qcom_qmp_dp_clks_hw_get()
2604 dp_clks = devm_kzalloc(qmp->dev, sizeof(*dp_clks), GFP_KERNEL); in phy_dp_clks_register()
2606 return -ENOMEM; in phy_dp_clks_register()
2608 dp_clks->qphy = qphy; in phy_dp_clks_register()
2609 qphy->dp_clks = dp_clks; in phy_dp_clks_register()
2611 snprintf(name, sizeof(name), "%s::link_clk", dev_name(qmp->dev)); in phy_dp_clks_register()
2614 dp_clks->dp_link_hw.init = &init; in phy_dp_clks_register()
2615 ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_link_hw); in phy_dp_clks_register()
2619 snprintf(name, sizeof(name), "%s::vco_div_clk", dev_name(qmp->dev)); in phy_dp_clks_register()
2622 dp_clks->dp_pixel_hw.init = &init; in phy_dp_clks_register()
2623 ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_pixel_hw); in phy_dp_clks_register()
2635 return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np); in phy_dp_clks_register()
2667 return -ENOMEM; in qmp_combo_create()
2669 qphy->cfg = cfg; in qmp_combo_create()
2670 qphy->serdes = serdes; in qmp_combo_create()
2673 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2. in qmp_combo_create()
2674 * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5 in qmp_combo_create()
2675 * For single lane PHYs: pcs_misc (optional) -> 3. in qmp_combo_create()
2677 qphy->tx = devm_of_iomap(dev, np, 0, NULL); in qmp_combo_create()
2678 if (IS_ERR(qphy->tx)) in qmp_combo_create()
2679 return PTR_ERR(qphy->tx); in qmp_combo_create()
2681 qphy->rx = devm_of_iomap(dev, np, 1, NULL); in qmp_combo_create()
2682 if (IS_ERR(qphy->rx)) in qmp_combo_create()
2683 return PTR_ERR(qphy->rx); in qmp_combo_create()
2685 qphy->pcs = devm_of_iomap(dev, np, 2, NULL); in qmp_combo_create()
2686 if (IS_ERR(qphy->pcs)) in qmp_combo_create()
2687 return PTR_ERR(qphy->pcs); in qmp_combo_create()
2689 if (cfg->pcs_usb_offset) in qmp_combo_create()
2690 qphy->pcs_usb = qphy->pcs + cfg->pcs_usb_offset; in qmp_combo_create()
2692 if (cfg->lanes >= 2) { in qmp_combo_create()
2693 qphy->tx2 = devm_of_iomap(dev, np, 3, NULL); in qmp_combo_create()
2694 if (IS_ERR(qphy->tx2)) in qmp_combo_create()
2695 return PTR_ERR(qphy->tx2); in qmp_combo_create()
2697 qphy->rx2 = devm_of_iomap(dev, np, 4, NULL); in qmp_combo_create()
2698 if (IS_ERR(qphy->rx2)) in qmp_combo_create()
2699 return PTR_ERR(qphy->rx2); in qmp_combo_create()
2701 qphy->pcs_misc = devm_of_iomap(dev, np, 5, NULL); in qmp_combo_create()
2703 qphy->pcs_misc = devm_of_iomap(dev, np, 3, NULL); in qmp_combo_create()
2706 if (IS_ERR(qphy->pcs_misc)) { in qmp_combo_create()
2707 dev_vdbg(dev, "PHY pcs_misc-reg not used\n"); in qmp_combo_create()
2708 qphy->pcs_misc = NULL; in qmp_combo_create()
2718 qphy->pipe_clk = devm_get_clk_from_child(dev, np, NULL); in qmp_combo_create()
2719 if (IS_ERR(qphy->pipe_clk)) { in qmp_combo_create()
2720 if (cfg->type == PHY_TYPE_USB3) in qmp_combo_create()
2721 return dev_err_probe(dev, PTR_ERR(qphy->pipe_clk), in qmp_combo_create()
2724 qphy->pipe_clk = NULL; in qmp_combo_create()
2727 if (cfg->type == PHY_TYPE_DP) in qmp_combo_create()
2739 qphy->phy = generic_phy; in qmp_combo_create()
2740 qphy->qmp = qmp; in qmp_combo_create()
2741 qmp->phys[id] = qphy; in qmp_combo_create()
2749 .compatible = "qcom,sc7180-qmp-usb3-dp-phy",
2753 .compatible = "qcom,sdm845-qmp-usb3-dp-phy",
2757 .compatible = "qcom,sm8250-qmp-usb3-dp-phy",
2761 .compatible = "qcom,sc8180x-qmp-usb3-dp-phy",
2765 .compatible = "qcom,sc8280xp-qmp-usb43dp-phy",
2780 struct device *dev = &pdev->dev; in qmp_combo_probe()
2795 return -ENOMEM; in qmp_combo_probe()
2797 qmp->dev = dev; in qmp_combo_probe()
2803 return -EINVAL; in qmp_combo_probe()
2805 usb_cfg = combo_cfg->usb_cfg; in qmp_combo_probe()
2813 qmp->dp_com = devm_platform_ioremap_resource(pdev, 1); in qmp_combo_probe()
2814 if (IS_ERR(qmp->dp_com)) in qmp_combo_probe()
2815 return PTR_ERR(qmp->dp_com); in qmp_combo_probe()
2822 dp_cfg = combo_cfg->dp_cfg; in qmp_combo_probe()
2825 mutex_init(&qmp->phy_mutex); in qmp_combo_probe()
2840 num = of_get_available_child_count(dev->of_node); in qmp_combo_probe()
2843 return -EINVAL; in qmp_combo_probe()
2845 qmp->phys = devm_kcalloc(dev, num, sizeof(*qmp->phys), GFP_KERNEL); in qmp_combo_probe()
2846 if (!qmp->phys) in qmp_combo_probe()
2847 return -ENOMEM; in qmp_combo_probe()
2860 for_each_available_child_of_node(dev->of_node, child) { in qmp_combo_probe()
2861 if (of_node_name_eq(child, "dp-phy")) { in qmp_combo_probe()
2865 /* Create per-lane phy */ in qmp_combo_probe()
2873 ret = phy_dp_clks_register(qmp, qmp->phys[id], child); in qmp_combo_probe()
2875 dev_err(qmp->dev, in qmp_combo_probe()
2879 } else if (of_node_name_eq(child, "usb3-phy")) { in qmp_combo_probe()
2883 /* Create per-lane phy */ in qmp_combo_probe()
2897 dev_err(qmp->dev, in qmp_combo_probe()
2918 .name = "qcom-qmp-combo-phy",