267 /* PHY lane CSR accessing from SDS indirectly */
519 	u32 speed[MAX_LANE]; /* Index for override parameter per lane */
657 static void serdes_wr(struct xgene_phy_ctx *ctx, int lane, u32 reg, u32 data)  in serdes_wr()  argument
663 	reg += lane * SERDES_LANE_STRIDE;  in serdes_wr()
672 static void serdes_rd(struct xgene_phy_ctx *ctx, int lane, u32 reg, u32 *data)  in serdes_rd()  argument
677 	reg += lane * SERDES_LANE_STRIDE;  in serdes_rd()
683 static void serdes_clrbits(struct xgene_phy_ctx *ctx, int lane, u32 reg,  in serdes_clrbits()  argument
688 	serdes_rd(ctx, lane, reg, &val);  in serdes_clrbits()
690 	serdes_wr(ctx, lane, reg, val);  in serdes_clrbits()
693 static void serdes_setbits(struct xgene_phy_ctx *ctx, int lane, u32 reg,  in serdes_setbits()  argument
698 	serdes_rd(ctx, lane, reg, &val);  in serdes_setbits()
700 	serdes_wr(ctx, lane, reg, val);  in serdes_setbits()
855 	/* Configure lane for 20-bits */  in xgene_phy_sata_cfg_cmu_core()
943 	int lane;  in xgene_phy_sata_cfg_lanes()  local
945 	for (lane = 0; lane < MAX_LANE; lane++) {  in xgene_phy_sata_cfg_lanes()
946 		serdes_wr(ctx, lane, RXTX_REG147, 0x6);  in xgene_phy_sata_cfg_lanes()
949 		serdes_rd(ctx, lane, RXTX_REG0, &val);  in xgene_phy_sata_cfg_lanes()
953 		serdes_wr(ctx, lane, RXTX_REG0, val);  in xgene_phy_sata_cfg_lanes()
956 		serdes_rd(ctx, lane, RXTX_REG1, &val);  in xgene_phy_sata_cfg_lanes()
959 			ctx->sata_param.txboostgain[lane * 3 +  in xgene_phy_sata_cfg_lanes()
960 			ctx->sata_param.speed[lane]]);  in xgene_phy_sata_cfg_lanes()
961 		serdes_wr(ctx, lane, RXTX_REG1, val);  in xgene_phy_sata_cfg_lanes()
966 		serdes_rd(ctx, lane, RXTX_REG2, &val);  in xgene_phy_sata_cfg_lanes()
970 		serdes_wr(ctx, lane, RXTX_REG2, val);  in xgene_phy_sata_cfg_lanes()
973 		serdes_rd(ctx, lane, RXTX_REG4, &val);  in xgene_phy_sata_cfg_lanes()
975 		serdes_wr(ctx, lane, RXTX_REG4, val);  in xgene_phy_sata_cfg_lanes()
978 			serdes_rd(ctx, lane, RXTX_REG1, &val);  in xgene_phy_sata_cfg_lanes()
981 			serdes_wr(ctx, lane, RXTX_REG1, val);  in xgene_phy_sata_cfg_lanes()
985 		serdes_rd(ctx, lane, RXTX_REG5, &val);  in xgene_phy_sata_cfg_lanes()
987 			ctx->sata_param.txprecursor_cn1[lane * 3 +  in xgene_phy_sata_cfg_lanes()
988 			ctx->sata_param.speed[lane]]);  in xgene_phy_sata_cfg_lanes()
990 			ctx->sata_param.txpostcursor_cp1[lane * 3 +  in xgene_phy_sata_cfg_lanes()
991 			ctx->sata_param.speed[lane]]);  in xgene_phy_sata_cfg_lanes()
993 			ctx->sata_param.txprecursor_cn2[lane * 3 +  in xgene_phy_sata_cfg_lanes()
994 			ctx->sata_param.speed[lane]]);  in xgene_phy_sata_cfg_lanes()
995 		serdes_wr(ctx, lane, RXTX_REG5, val);  in xgene_phy_sata_cfg_lanes()
998 		serdes_rd(ctx, lane, RXTX_REG6, &val);  in xgene_phy_sata_cfg_lanes()
1000 			ctx->sata_param.txamplitude[lane * 3 +  in xgene_phy_sata_cfg_lanes()
1001 			ctx->sata_param.speed[lane]]);  in xgene_phy_sata_cfg_lanes()
1006 		serdes_wr(ctx, lane, RXTX_REG6, val);  in xgene_phy_sata_cfg_lanes()
1009 		serdes_rd(ctx, lane, RXTX_REG7, &val);  in xgene_phy_sata_cfg_lanes()
1012 		serdes_wr(ctx, lane, RXTX_REG7, val);  in xgene_phy_sata_cfg_lanes()
1015 		serdes_rd(ctx, lane, RXTX_REG8, &val);  in xgene_phy_sata_cfg_lanes()
1021 		serdes_wr(ctx, lane, RXTX_REG8, val);  in xgene_phy_sata_cfg_lanes()
1024 		serdes_rd(ctx, lane, RXTX_REG11, &val);  in xgene_phy_sata_cfg_lanes()
1026 		serdes_wr(ctx, lane, RXTX_REG11, val);  in xgene_phy_sata_cfg_lanes()
1029 		serdes_rd(ctx, lane, RXTX_REG12, &val);  in xgene_phy_sata_cfg_lanes()
1033 		serdes_wr(ctx, lane, RXTX_REG12, val);  in xgene_phy_sata_cfg_lanes()
1036 		serdes_rd(ctx, lane, RXTX_REG26, &val);  in xgene_phy_sata_cfg_lanes()
1039 		serdes_wr(ctx, lane, RXTX_REG26, val);  in xgene_phy_sata_cfg_lanes()
1041 		serdes_wr(ctx, lane, RXTX_REG28, 0x0);  in xgene_phy_sata_cfg_lanes()
1044 		serdes_wr(ctx, lane, RXTX_REG31, 0x0);  in xgene_phy_sata_cfg_lanes()
1047 		serdes_rd(ctx, lane, RXTX_REG61, &val);  in xgene_phy_sata_cfg_lanes()
1051 		serdes_wr(ctx, lane, RXTX_REG61, val);  in xgene_phy_sata_cfg_lanes()
1053 		serdes_rd(ctx, lane, RXTX_REG62, &val);  in xgene_phy_sata_cfg_lanes()
1055 		serdes_wr(ctx, lane, RXTX_REG62, val);  in xgene_phy_sata_cfg_lanes()
1060 			serdes_rd(ctx, lane, reg, &val);  in xgene_phy_sata_cfg_lanes()
1064 			serdes_wr(ctx, lane, reg, val);  in xgene_phy_sata_cfg_lanes()
1070 			serdes_rd(ctx, lane, reg, &val);  in xgene_phy_sata_cfg_lanes()
1074 			serdes_wr(ctx, lane, reg, val);  in xgene_phy_sata_cfg_lanes()
1080 			serdes_rd(ctx, lane, reg, &val);  in xgene_phy_sata_cfg_lanes()
1084 			serdes_wr(ctx, lane, reg, val);  in xgene_phy_sata_cfg_lanes()
1087 		serdes_rd(ctx, lane, RXTX_REG102, &val);  in xgene_phy_sata_cfg_lanes()
1089 		serdes_wr(ctx, lane, RXTX_REG102, val);  in xgene_phy_sata_cfg_lanes()
1091 		serdes_wr(ctx, lane, RXTX_REG114, 0xffe0);  in xgene_phy_sata_cfg_lanes()
1093 		serdes_rd(ctx, lane, RXTX_REG125, &val);  in xgene_phy_sata_cfg_lanes()
1095 			ctx->sata_param.txeyedirection[lane * 3 +  in xgene_phy_sata_cfg_lanes()
1096 			ctx->sata_param.speed[lane]]);  in xgene_phy_sata_cfg_lanes()
1098 			ctx->sata_param.txeyetuning[lane * 3 +  in xgene_phy_sata_cfg_lanes()
1099 			ctx->sata_param.speed[lane]]);  in xgene_phy_sata_cfg_lanes()
1101 		serdes_wr(ctx, lane, RXTX_REG125, val);  in xgene_phy_sata_cfg_lanes()
1103 		serdes_rd(ctx, lane, RXTX_REG127, &val);  in xgene_phy_sata_cfg_lanes()
1105 		serdes_wr(ctx, lane, RXTX_REG127, val);  in xgene_phy_sata_cfg_lanes()
1107 		serdes_rd(ctx, lane, RXTX_REG128, &val);  in xgene_phy_sata_cfg_lanes()
1109 		serdes_wr(ctx, lane, RXTX_REG128, val);  in xgene_phy_sata_cfg_lanes()
1111 		serdes_rd(ctx, lane, RXTX_REG145, &val);  in xgene_phy_sata_cfg_lanes()
1121 		serdes_wr(ctx, lane, RXTX_REG145, val);  in xgene_phy_sata_cfg_lanes()
1129 			serdes_wr(ctx, lane, reg, 0xFFFF);  in xgene_phy_sata_cfg_lanes()
1264 	/* Release PHY lane from reset (active high) */  in xgene_phy_hw_init_sata()
1343 static void xgene_phy_force_lat_summer_cal(struct xgene_phy_ctx *ctx, int lane)  in xgene_phy_force_lat_summer_cal()  argument
1371 	serdes_setbits(ctx, lane, RXTX_REG127,  in xgene_phy_force_lat_summer_cal()
1378 	serdes_clrbits(ctx, lane, RXTX_REG127,  in xgene_phy_force_lat_summer_cal()
1387 	serdes_setbits(ctx, lane, RXTX_REG127,  in xgene_phy_force_lat_summer_cal()
1394 	serdes_clrbits(ctx, lane, RXTX_REG127,  in xgene_phy_force_lat_summer_cal()
1397 	/* Configure the PHY lane for calibration */  in xgene_phy_force_lat_summer_cal()
1398 	serdes_wr(ctx, lane, RXTX_REG28, 0x7);  in xgene_phy_force_lat_summer_cal()
1399 	serdes_wr(ctx, lane, RXTX_REG31, 0x7e00);  in xgene_phy_force_lat_summer_cal()
1400 	serdes_clrbits(ctx, lane, RXTX_REG4,  in xgene_phy_force_lat_summer_cal()
1402 	serdes_clrbits(ctx, lane, RXTX_REG7,  in xgene_phy_force_lat_summer_cal()
1405 		serdes_wr(ctx, lane, serdes_reg[i].reg,  in xgene_phy_force_lat_summer_cal()
1409 static void xgene_phy_reset_rxd(struct xgene_phy_ctx *ctx, int lane)  in xgene_phy_reset_rxd()  argument
1412 	serdes_clrbits(ctx, lane, RXTX_REG7, RXTX_REG7_RESETB_RXD_MASK);  in xgene_phy_reset_rxd()
1415 	serdes_setbits(ctx, lane, RXTX_REG7, RXTX_REG7_RESETB_RXD_MASK);  in xgene_phy_reset_rxd()
1423 static void xgene_phy_gen_avg_val(struct xgene_phy_ctx *ctx, int lane)  in xgene_phy_gen_avg_val()  argument
1437 	dev_dbg(ctx->dev, "Generating avg calibration value for lane %d\n",  in xgene_phy_gen_avg_val()
1438 		lane);  in xgene_phy_gen_avg_val()
1441 	serdes_setbits(ctx, lane, RXTX_REG12,  in xgene_phy_gen_avg_val()
1444 	serdes_wr(ctx, lane, RXTX_REG28, 0x0000);  in xgene_phy_gen_avg_val()
1446 	serdes_wr(ctx, lane, RXTX_REG31, 0x0000);  in xgene_phy_gen_avg_val()
1457 		xgene_phy_force_lat_summer_cal(ctx, lane);  in xgene_phy_gen_avg_val()
1459 		serdes_rd(ctx, lane, RXTX_REG21, &val);  in xgene_phy_gen_avg_val()
1464 		serdes_rd(ctx, lane, RXTX_REG22, &val);  in xgene_phy_gen_avg_val()
1469 		serdes_rd(ctx, lane, RXTX_REG23, &val);  in xgene_phy_gen_avg_val()
1473 		serdes_rd(ctx, lane, RXTX_REG24, &val);  in xgene_phy_gen_avg_val()
1477 		serdes_rd(ctx, lane, RXTX_REG121, &val);  in xgene_phy_gen_avg_val()
1507 		xgene_phy_reset_rxd(ctx, lane);  in xgene_phy_gen_avg_val()
1511 	serdes_rd(ctx, lane, RXTX_REG127, &val);  in xgene_phy_gen_avg_val()
1516 	serdes_wr(ctx, lane, RXTX_REG127, val);  in xgene_phy_gen_avg_val()
1518 	serdes_rd(ctx, lane, RXTX_REG128, &val);  in xgene_phy_gen_avg_val()
1523 	serdes_wr(ctx, lane, RXTX_REG128, val);  in xgene_phy_gen_avg_val()
1525 	serdes_rd(ctx, lane, RXTX_REG129, &val);  in xgene_phy_gen_avg_val()
1530 	serdes_wr(ctx, lane, RXTX_REG129, val);  in xgene_phy_gen_avg_val()
1532 	serdes_rd(ctx, lane, RXTX_REG130, &val);  in xgene_phy_gen_avg_val()
1537 	serdes_wr(ctx, lane, RXTX_REG130, val);  in xgene_phy_gen_avg_val()
1540 	serdes_rd(ctx, lane, RXTX_REG14, &val);  in xgene_phy_gen_avg_val()
1543 	serdes_wr(ctx, lane, RXTX_REG14, val);  in xgene_phy_gen_avg_val()
1559 	serdes_rd(ctx, lane, RXTX_REG14, &val);  in xgene_phy_gen_avg_val()
1561 	serdes_wr(ctx, lane, RXTX_REG14, val);  in xgene_phy_gen_avg_val()
1564 	serdes_rd(ctx, lane, RXTX_REG127, &val);  in xgene_phy_gen_avg_val()
1567 	serdes_wr(ctx, lane, RXTX_REG127, val);  in xgene_phy_gen_avg_val()
1570 	serdes_rd(ctx, lane, RXTX_REG12, &val);  in xgene_phy_gen_avg_val()
1572 	serdes_wr(ctx, lane, RXTX_REG12, val);  in xgene_phy_gen_avg_val()
1574 	serdes_wr(ctx, lane, RXTX_REG28, 0x0007);  in xgene_phy_gen_avg_val()
1576 	serdes_wr(ctx, lane, RXTX_REG31, 0x7e00);  in xgene_phy_gen_avg_val()