Lines Matching +full:phy +full:- +full:pma
1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * https://github.com/microchip-ung/sparx-5_reginfo
9 …* https://ww1.microchip.com/downloads/en/DeviceDoc/SparX-5_Family_L2L3_Enterprise_10G_Ethernet_Swi…
19 #include <linux/phy.h>
20 #include <linux/phy/phy.h>
99 u8 if_width; /* UDL if-width: 10/16/20/32/64 */
102 bool no_pwrcycle:1; /* Omit initial power-cycle */
241 bool no_pwrcycle:1; /* Omit initial power-cycle */
647 switch (macro->serdesmode) { in sparx5_sd10g25_get_mode_preset()
649 if (macro->speed == SPEED_25000) in sparx5_sd10g25_get_mode_preset()
651 else if (macro->speed == SPEED_10000) in sparx5_sd10g25_get_mode_preset()
653 else if (macro->speed == SPEED_5000) in sparx5_sd10g25_get_mode_preset()
664 return -EINVAL; in sparx5_sd10g25_get_mode_preset()
676 switch (macro->serdesmode) { in sparx5_sd10g28_get_mode_preset()
678 if (macro->speed == SPEED_10000) { in sparx5_sd10g28_get_mode_preset()
680 } else if (macro->speed == SPEED_5000) { in sparx5_sd10g28_get_mode_preset()
681 if (args->is_6g) in sparx5_sd10g28_get_mode_preset()
686 dev_err(macro->priv->dev, "%s: Illegal speed: %02u, sidx: %02u, mode (%u)", in sparx5_sd10g28_get_mode_preset()
687 __func__, macro->speed, macro->sidx, in sparx5_sd10g28_get_mode_preset()
688 macro->serdesmode); in sparx5_sd10g28_get_mode_preset()
689 return -EINVAL; in sparx5_sd10g28_get_mode_preset()
715 u8 iw = sd25g28_get_iw_setting(macro->priv->dev, mode->bitwidth); in sparx5_sd25g28_get_params()
718 .r_txfifo_ck_div_pmad_2_0 = mode->fifo_ck_div, in sparx5_sd25g28_get_params()
719 .r_rxfifo_ck_div_pmad_2_0 = mode->fifo_ck_div, in sparx5_sd25g28_get_params()
720 .cfg_vco_div_mode_1_0 = mode->vco_div_mode, in sparx5_sd25g28_get_params()
721 .cfg_pre_divsel_1_0 = mode->pre_divsel, in sparx5_sd25g28_get_params()
722 .cfg_sel_div_3_0 = mode->sel_div, in sparx5_sd25g28_get_params()
724 .cfg_pma_tx_ck_bitwidth_2_0 = mode->ck_bitwidth, in sparx5_sd25g28_get_params()
725 .cfg_tx_prediv_1_0 = mode->tx_pre_div, in sparx5_sd25g28_get_params()
726 .cfg_rxdiv_sel_2_0 = mode->ck_bitwidth, in sparx5_sd25g28_get_params()
727 .cfg_tx_subrate_2_0 = mode->subrate, in sparx5_sd25g28_get_params()
728 .cfg_rx_subrate_2_0 = mode->subrate, in sparx5_sd25g28_get_params()
731 .cfg_dfeck_en = mode->dfe_enable, in sparx5_sd25g28_get_params()
732 .cfg_dfe_pd = mode->dfe_enable == 1 ? 0 : 1, in sparx5_sd25g28_get_params()
734 .cfg_dfetap_en_5_1 = mode->dfe_tap, in sparx5_sd25g28_get_params()
737 .cfg_erramp_pd = mode->dfe_enable == 1 ? 0 : 1, in sparx5_sd25g28_get_params()
738 .cfg_pi_DFE_en = mode->dfe_enable, in sparx5_sd25g28_get_params()
751 .cfg_itx_ipdriver_base_2_0 = mode->txmargin, in sparx5_sd25g28_get_params()
752 .cfg_tap_dly_4_0 = media->cfg_tap_dly_4_0, in sparx5_sd25g28_get_params()
753 .cfg_tap_main = media->cfg_tap_main, in sparx5_sd25g28_get_params()
754 .cfg_en_main = media->cfg_en_main, in sparx5_sd25g28_get_params()
755 .cfg_tap_adv_3_0 = media->cfg_tap_adv_3_0, in sparx5_sd25g28_get_params()
756 .cfg_en_adv = media->cfg_en_adv, in sparx5_sd25g28_get_params()
757 .cfg_en_dly = media->cfg_en_dly, in sparx5_sd25g28_get_params()
762 .cfg_pll_reserve_3_0 = args->com_pll_reserve, in sparx5_sd25g28_get_params()
763 .l0_cfg_txcal_en = mode->com_txcal_en, in sparx5_sd25g28_get_params()
764 .l0_cfg_tx_reserve_15_8 = mode->com_tx_reserve_msb, in sparx5_sd25g28_get_params()
765 .l0_cfg_tx_reserve_7_0 = mode->com_tx_reserve_lsb, in sparx5_sd25g28_get_params()
766 .cfg_tx_reserve_15_8 = mode->tx_reserve_msb, in sparx5_sd25g28_get_params()
767 .cfg_tx_reserve_7_0 = mode->tx_reserve_lsb, in sparx5_sd25g28_get_params()
768 .cfg_bw_1_0 = mode->bw, in sparx5_sd25g28_get_params()
777 .cfg_pi_bw_3_0 = mode->cfg_pi_bw_3_0, in sparx5_sd25g28_get_params()
780 .cfg_ctle_rstn = mode->cfg_ctle_rstn, in sparx5_sd25g28_get_params()
781 .r_dfe_rstn = mode->r_dfe_rstn, in sparx5_sd25g28_get_params()
782 .cfg_alos_thr_2_0 = media->cfg_alos_thr_2_0, in sparx5_sd25g28_get_params()
783 .cfg_itx_ipcml_base_1_0 = mode->cfg_itx_ipcml_base, in sparx5_sd25g28_get_params()
786 .cfg_rxterm_2_0 = mode->rxterm, in sparx5_sd25g28_get_params()
790 .cfg_vga_ctrl_byp_4_0 = media->cfg_vga_ctrl_byp_4_0, in sparx5_sd25g28_get_params()
794 .cfg_eqr_force_3_0 = media->cfg_eq_r_force_3_0, in sparx5_sd25g28_get_params()
795 .cfg_eqc_force_3_0 = media->cfg_eq_c_force_3_0, in sparx5_sd25g28_get_params()
801 .cfg_en_dfedig = mode->dfe_enable, in sparx5_sd25g28_get_params()
804 .reg_rst = args->reg_rst, in sparx5_sd25g28_get_params()
812 .r_tx_pol_inv = args->txinvert, in sparx5_sd25g28_get_params()
813 .r_rx_pol_inv = args->rxinvert, in sparx5_sd25g28_get_params()
825 u8 iw = sd10g28_get_iw_setting(macro->priv->dev, mode->bwidth); in sparx5_sd10g28_get_params()
827 .skip_cmu_cfg = args->skip_cmu_cfg, in sparx5_sd10g28_get_params()
828 .is_6g = args->is_6g, in sparx5_sd10g28_get_params()
829 .cmu_sel = mode->cmu_sel, in sparx5_sd10g28_get_params()
830 .cfg_lane_reserve_7_0 = (mode->cmu_sel % 2) << 6, in sparx5_sd10g28_get_params()
831 .cfg_ssc_rtl_clk_sel = (mode->cmu_sel / 2), in sparx5_sd10g28_get_params()
832 .cfg_lane_reserve_15_8 = mode->duty_cycle, in sparx5_sd10g28_get_params()
833 .cfg_txrate_1_0 = mode->rate, in sparx5_sd10g28_get_params()
834 .cfg_rxrate_1_0 = mode->rate, in sparx5_sd10g28_get_params()
835 .fx_100 = macro->serdesmode == SPX5_SD_MODE_100FX, in sparx5_sd10g28_get_params()
842 .cfg_dfeck_en = mode->dfe_enable, in sparx5_sd10g28_get_params()
843 .cfg_dfe_pd = (mode->dfe_enable == 1) ? 0 : 1, in sparx5_sd10g28_get_params()
844 .cfg_dfetap_en_5_1 = mode->dfe_tap, in sparx5_sd10g28_get_params()
845 .cfg_erramp_pd = (mode->dfe_enable == 1) ? 0 : 1, in sparx5_sd10g28_get_params()
846 .cfg_pi_DFE_en = mode->dfe_enable, in sparx5_sd10g28_get_params()
856 .cfg_pd_sq = mode->dfe_enable, in sparx5_sd10g28_get_params()
860 .cfg_en_adv = media->cfg_en_adv, in sparx5_sd10g28_get_params()
862 .cfg_en_dly = media->cfg_en_dly, in sparx5_sd10g28_get_params()
863 .cfg_tap_adv_3_0 = media->cfg_tap_adv_3_0, in sparx5_sd10g28_get_params()
864 .cfg_tap_main = media->cfg_tap_main, in sparx5_sd10g28_get_params()
865 .cfg_tap_dly_4_0 = media->cfg_tap_dly_4_0, in sparx5_sd10g28_get_params()
866 .cfg_vga_ctrl_3_0 = media->cfg_vga_ctrl_3_0, in sparx5_sd10g28_get_params()
867 .cfg_vga_cp_2_0 = media->cfg_vga_cp_2_0, in sparx5_sd10g28_get_params()
868 .cfg_eq_res_3_0 = media->cfg_eq_res_3_0, in sparx5_sd10g28_get_params()
869 .cfg_eq_r_byp = media->cfg_eq_r_byp, in sparx5_sd10g28_get_params()
870 .cfg_eq_c_force_3_0 = media->cfg_eq_c_force_3_0, in sparx5_sd10g28_get_params()
871 .cfg_en_dfedig = mode->dfe_enable, in sparx5_sd10g28_get_params()
875 .cfg_itx_ipdriver_base_2_0 = (args->txswing >> 6), in sparx5_sd10g28_get_params()
876 .cfg_ibias_tune_reserve_5_0 = (args->txswing & 63), in sparx5_sd10g28_get_params()
877 .cfg_txswing_half = (args->txmargin), in sparx5_sd10g28_get_params()
889 .cfg_pi_bw_gen1_3_0 = mode->pi_bw_gen1, in sparx5_sd10g28_get_params()
890 .cfg_pi_bw_gen2 = mode->pi_bw_gen1, in sparx5_sd10g28_get_params()
891 .cfg_pi_bw_gen3 = mode->pi_bw_gen1, in sparx5_sd10g28_get_params()
892 .cfg_pi_bw_gen4 = mode->pi_bw_gen1, in sparx5_sd10g28_get_params()
896 .cfg_rstn_dfedig = mode->dfe_enable, in sparx5_sd10g28_get_params()
897 .cfg_alos_thr_3_0 = media->cfg_alos_thr_3_0, in sparx5_sd10g28_get_params()
918 .r_tx_pol_inv = args->txinvert, in sparx5_sd10g28_get_params()
919 .r_rx_pol_inv = args->rxinvert, in sparx5_sd10g28_get_params()
929 if (params->reg_rst == 1) { in sparx5_sd25g28_reset()
945 struct sparx5_serdes_private *priv = macro->priv; in sparx5_sd25g28_apply_params()
946 void __iomem **regs = priv->regs; in sparx5_sd25g28_apply_params()
947 struct device *dev = priv->dev; in sparx5_sd25g28_apply_params()
948 u32 sd_index = macro->stpidx; in sparx5_sd25g28_apply_params()
962 (params->r_d_width_ctrl_from_hwt) | in sparx5_sd25g28_apply_params()
963 SD25G_LANE_CMU_1A_R_REG_MANUAL_SET(params->r_reg_manual), in sparx5_sd25g28_apply_params()
970 (params->cfg_common_reserve_7_0), in sparx5_sd25g28_apply_params()
975 sdx5_rmw(SD25G_LANE_CMU_09_CFG_EN_DUMMY_SET(params->cfg_en_dummy), in sparx5_sd25g28_apply_params()
981 (params->cfg_pll_reserve_3_0), in sparx5_sd25g28_apply_params()
986 sdx5_rmw(SD25G_LANE_CMU_40_L0_CFG_TXCAL_EN_SET(params->l0_cfg_txcal_en), in sparx5_sd25g28_apply_params()
992 (params->l0_cfg_tx_reserve_15_8), in sparx5_sd25g28_apply_params()
998 (params->l0_cfg_tx_reserve_7_0), in sparx5_sd25g28_apply_params()
1033 sdx5_rmw(SD25G_LANE_CMU_1A_R_DWIDTHCTRL_2_0_SET(params->r_d_width_ctrl_2_0), in sparx5_sd25g28_apply_params()
1039 (params->r_txfifo_ck_div_pmad_2_0) | in sparx5_sd25g28_apply_params()
1041 (params->r_rxfifo_ck_div_pmad_2_0), in sparx5_sd25g28_apply_params()
1047 sdx5_rmw(SD25G_LANE_CMU_0C_CFG_PLL_LOL_SET_SET(params->cfg_pll_lol_set) | in sparx5_sd25g28_apply_params()
1049 (params->cfg_vco_div_mode_1_0), in sparx5_sd25g28_apply_params()
1056 (params->cfg_pre_divsel_1_0), in sparx5_sd25g28_apply_params()
1061 sdx5_rmw(SD25G_LANE_CMU_0E_CFG_SEL_DIV_3_0_SET(params->cfg_sel_div_3_0), in sparx5_sd25g28_apply_params()
1072 (params->cfg_pma_tx_ck_bitwidth_2_0), in sparx5_sd25g28_apply_params()
1078 (params->cfg_tx_prediv_1_0), in sparx5_sd25g28_apply_params()
1084 (params->cfg_rxdiv_sel_2_0), in sparx5_sd25g28_apply_params()
1090 (params->cfg_tx_subrate_2_0), in sparx5_sd25g28_apply_params()
1096 (params->cfg_rx_subrate_2_0), in sparx5_sd25g28_apply_params()
1101 sdx5_rmw(SD25G_LANE_LANE_18_LN_CFG_CDRCK_EN_SET(params->cfg_cdrck_en), in sparx5_sd25g28_apply_params()
1107 (params->cfg_dfetap_en_5_1), in sparx5_sd25g28_apply_params()
1112 sdx5_rmw(SD25G_LANE_LANE_18_LN_CFG_ERRAMP_PD_SET(params->cfg_erramp_pd), in sparx5_sd25g28_apply_params()
1117 sdx5_rmw(SD25G_LANE_LANE_1D_LN_CFG_PI_DFE_EN_SET(params->cfg_pi_dfe_en), in sparx5_sd25g28_apply_params()
1122 sdx5_rmw(SD25G_LANE_LANE_19_LN_CFG_ECDR_PD_SET(params->cfg_ecdr_pd), in sparx5_sd25g28_apply_params()
1128 (params->cfg_itx_ipdriver_base_2_0), in sparx5_sd25g28_apply_params()
1133 sdx5_rmw(SD25G_LANE_LANE_03_LN_CFG_TAP_DLY_4_0_SET(params->cfg_tap_dly_4_0), in sparx5_sd25g28_apply_params()
1138 sdx5_rmw(SD25G_LANE_LANE_06_LN_CFG_TAP_ADV_3_0_SET(params->cfg_tap_adv_3_0), in sparx5_sd25g28_apply_params()
1143 sdx5_rmw(SD25G_LANE_LANE_07_LN_CFG_EN_ADV_SET(params->cfg_en_adv) | in sparx5_sd25g28_apply_params()
1144 SD25G_LANE_LANE_07_LN_CFG_EN_DLY_SET(params->cfg_en_dly), in sparx5_sd25g28_apply_params()
1151 (params->cfg_tx_reserve_15_8), in sparx5_sd25g28_apply_params()
1157 (params->cfg_tx_reserve_7_0), in sparx5_sd25g28_apply_params()
1162 sdx5_rmw(SD25G_LANE_LANE_05_LN_CFG_BW_1_0_SET(params->cfg_bw_1_0), in sparx5_sd25g28_apply_params()
1168 (params->cfg_txcal_man_en), in sparx5_sd25g28_apply_params()
1174 (params->cfg_txcal_shift_code_5_0), in sparx5_sd25g28_apply_params()
1180 (params->cfg_txcal_valid_sel_3_0), in sparx5_sd25g28_apply_params()
1185 sdx5_rmw(SD25G_LANE_LANE_1A_LN_CFG_CDR_KF_2_0_SET(params->cfg_cdr_kf_2_0), in sparx5_sd25g28_apply_params()
1190 sdx5_rmw(SD25G_LANE_LANE_1B_LN_CFG_CDR_M_7_0_SET(params->cfg_cdr_m_7_0), in sparx5_sd25g28_apply_params()
1195 sdx5_rmw(SD25G_LANE_LANE_2B_LN_CFG_PI_BW_3_0_SET(params->cfg_pi_bw_3_0), in sparx5_sd25g28_apply_params()
1201 (params->cfg_dis_2ndorder), in sparx5_sd25g28_apply_params()
1206 sdx5_rmw(SD25G_LANE_LANE_2E_LN_CFG_CTLE_RSTN_SET(params->cfg_ctle_rstn), in sparx5_sd25g28_apply_params()
1212 (params->cfg_itx_ipcml_base_1_0), in sparx5_sd25g28_apply_params()
1218 (params->cfg_rx_reserve_7_0), in sparx5_sd25g28_apply_params()
1224 (params->cfg_rx_reserve_15_8), in sparx5_sd25g28_apply_params()
1229 sdx5_rmw(SD25G_LANE_LANE_0D_LN_CFG_DFECK_EN_SET(params->cfg_dfeck_en) | in sparx5_sd25g28_apply_params()
1230 SD25G_LANE_LANE_0D_LN_CFG_RXTERM_2_0_SET(params->cfg_rxterm_2_0), in sparx5_sd25g28_apply_params()
1237 (params->cfg_vga_ctrl_byp_4_0), in sparx5_sd25g28_apply_params()
1243 (params->cfg_eqr_force_3_0), in sparx5_sd25g28_apply_params()
1249 (params->cfg_eqc_force_3_0) | in sparx5_sd25g28_apply_params()
1250 SD25G_LANE_LANE_1C_LN_CFG_DFE_PD_SET(params->cfg_dfe_pd), in sparx5_sd25g28_apply_params()
1257 (params->cfg_sum_setcm_en), in sparx5_sd25g28_apply_params()
1263 (params->cfg_init_pos_iscan_6_0), in sparx5_sd25g28_apply_params()
1269 (params->cfg_init_pos_ipi_6_0), in sparx5_sd25g28_apply_params()
1274 sdx5_rmw(SD25G_LANE_LANE_18_LN_CFG_ERRAMP_PD_SET(params->cfg_erramp_pd), in sparx5_sd25g28_apply_params()
1280 (params->cfg_dfedig_m_2_0), in sparx5_sd25g28_apply_params()
1285 sdx5_rmw(SD25G_LANE_LANE_0E_LN_CFG_EN_DFEDIG_SET(params->cfg_en_dfedig), in sparx5_sd25g28_apply_params()
1290 sdx5_rmw(SD25G_LANE_LANE_40_LN_R_TX_POL_INV_SET(params->r_tx_pol_inv) | in sparx5_sd25g28_apply_params()
1291 SD25G_LANE_LANE_40_LN_R_RX_POL_INV_SET(params->r_rx_pol_inv), in sparx5_sd25g28_apply_params()
1297 sdx5_rmw(SD25G_LANE_LANE_04_LN_CFG_RX2TX_LP_EN_SET(params->cfg_rx2tx_lp_en) | in sparx5_sd25g28_apply_params()
1298 SD25G_LANE_LANE_04_LN_CFG_TX2RX_LP_EN_SET(params->cfg_tx2rx_lp_en), in sparx5_sd25g28_apply_params()
1304 sdx5_rmw(SD25G_LANE_LANE_1E_LN_CFG_RXLB_EN_SET(params->cfg_rxlb_en), in sparx5_sd25g28_apply_params()
1309 sdx5_rmw(SD25G_LANE_LANE_19_LN_CFG_TXLB_EN_SET(params->cfg_txlb_en), in sparx5_sd25g28_apply_params()
1353 return -EINVAL; in sparx5_sd25g28_apply_params()
1360 dev_err(dev, "25G PMA Reset failed: 0x%x\n", value); in sparx5_sd25g28_apply_params()
1361 return -EINVAL; in sparx5_sd25g28_apply_params()
1384 (params->cfg_alos_thr_2_0), in sparx5_sd25g28_apply_params()
1419 struct sparx5_serdes_private *priv = macro->priv; in sparx5_sd10g28_apply_params()
1420 void __iomem **regs = priv->regs; in sparx5_sd10g28_apply_params()
1421 struct device *dev = priv->dev; in sparx5_sd10g28_apply_params()
1422 u32 lane_index = macro->sidx; in sparx5_sd10g28_apply_params()
1423 u32 sd_index = macro->stpidx; in sparx5_sd10g28_apply_params()
1427 if (params->is_6g) in sparx5_sd10g28_apply_params()
1475 sdx5_rmw(SD_LANE_SD_LANE_CFG_RX_REF_SEL_SET(params->cmu_sel) | in sparx5_sd10g28_apply_params()
1476 SD_LANE_SD_LANE_CFG_TX_REF_SEL_SET(params->cmu_sel), in sparx5_sd10g28_apply_params()
1483 (params->cfg_lane_reserve_7_0), in sparx5_sd10g28_apply_params()
1489 (params->cfg_ssc_rtl_clk_sel), in sparx5_sd10g28_apply_params()
1495 (params->cfg_txrate_1_0) | in sparx5_sd10g28_apply_params()
1497 (params->cfg_rxrate_1_0), in sparx5_sd10g28_apply_params()
1504 (params->r_d_width_ctrl_2_0), in sparx5_sd10g28_apply_params()
1510 (params->cfg_pma_tx_ck_bitwidth_2_0), in sparx5_sd10g28_apply_params()
1516 (params->cfg_rxdiv_sel_2_0), in sparx5_sd10g28_apply_params()
1522 (params->r_pcs2pma_phymode_4_0), in sparx5_sd10g28_apply_params()
1527 sdx5_inst_rmw(SD10G_LANE_LANE_13_CFG_CDRCK_EN_SET(params->cfg_cdrck_en), in sparx5_sd10g28_apply_params()
1533 (params->cfg_dfeck_en) | in sparx5_sd10g28_apply_params()
1534 SD10G_LANE_LANE_23_CFG_DFE_PD_SET(params->cfg_dfe_pd) | in sparx5_sd10g28_apply_params()
1536 (params->cfg_erramp_pd), in sparx5_sd10g28_apply_params()
1544 (params->cfg_dfetap_en_5_1), in sparx5_sd10g28_apply_params()
1550 (params->cfg_pi_DFE_en), in sparx5_sd10g28_apply_params()
1555 sdx5_inst_rmw(SD10G_LANE_LANE_02_CFG_EN_ADV_SET(params->cfg_en_adv) | in sparx5_sd10g28_apply_params()
1556 SD10G_LANE_LANE_02_CFG_EN_MAIN_SET(params->cfg_en_main) | in sparx5_sd10g28_apply_params()
1557 SD10G_LANE_LANE_02_CFG_EN_DLY_SET(params->cfg_en_dly) | in sparx5_sd10g28_apply_params()
1559 (params->cfg_tap_adv_3_0), in sparx5_sd10g28_apply_params()
1567 sdx5_inst_rmw(SD10G_LANE_LANE_03_CFG_TAP_MAIN_SET(params->cfg_tap_main), in sparx5_sd10g28_apply_params()
1573 (params->cfg_tap_dly_4_0), in sparx5_sd10g28_apply_params()
1579 (params->cfg_vga_ctrl_3_0), in sparx5_sd10g28_apply_params()
1585 (params->cfg_vga_cp_2_0), in sparx5_sd10g28_apply_params()
1591 (params->cfg_eq_res_3_0), in sparx5_sd10g28_apply_params()
1596 sdx5_inst_rmw(SD10G_LANE_LANE_0D_CFG_EQR_BYP_SET(params->cfg_eq_r_byp), in sparx5_sd10g28_apply_params()
1602 (params->cfg_eq_c_force_3_0) | in sparx5_sd10g28_apply_params()
1604 (params->cfg_sum_setcm_en), in sparx5_sd10g28_apply_params()
1611 (params->cfg_en_dfedig), in sparx5_sd10g28_apply_params()
1617 (params->cfg_en_preemph), in sparx5_sd10g28_apply_params()
1623 (params->cfg_itx_ippreemp_base_1_0) | in sparx5_sd10g28_apply_params()
1625 (params->cfg_itx_ipdriver_base_2_0), in sparx5_sd10g28_apply_params()
1632 (params->cfg_ibias_tune_reserve_5_0), in sparx5_sd10g28_apply_params()
1638 (params->cfg_txswing_half), in sparx5_sd10g28_apply_params()
1644 (params->cfg_dis_2nd_order), in sparx5_sd10g28_apply_params()
1650 (params->cfg_rx_ssc_lh), in sparx5_sd10g28_apply_params()
1656 (params->cfg_pi_floop_steps_1_0), in sparx5_sd10g28_apply_params()
1662 (params->cfg_pi_ext_dac_23_16), in sparx5_sd10g28_apply_params()
1668 (params->cfg_pi_ext_dac_15_8), in sparx5_sd10g28_apply_params()
1674 (params->cfg_iscan_ext_dac_7_0), in sparx5_sd10g28_apply_params()
1680 (params->cfg_cdr_kf_gen1_2_0), in sparx5_sd10g28_apply_params()
1686 (params->r_cdr_m_gen1_7_0), in sparx5_sd10g28_apply_params()
1692 (params->cfg_pi_bw_gen1_3_0), in sparx5_sd10g28_apply_params()
1698 (params->cfg_pi_ext_dac_7_0), in sparx5_sd10g28_apply_params()
1703 sdx5_inst_rmw(SD10G_LANE_LANE_1A_CFG_PI_STEPS_SET(params->cfg_pi_steps), in sparx5_sd10g28_apply_params()
1709 (params->cfg_mp_max_3_0), in sparx5_sd10g28_apply_params()
1715 (params->cfg_rstn_dfedig), in sparx5_sd10g28_apply_params()
1721 (params->cfg_alos_thr_3_0), in sparx5_sd10g28_apply_params()
1727 (params->cfg_predrv_slewrate_1_0), in sparx5_sd10g28_apply_params()
1733 (params->cfg_itx_ipcml_base_1_0), in sparx5_sd10g28_apply_params()
1739 (params->cfg_ip_pre_base_1_0), in sparx5_sd10g28_apply_params()
1745 (params->cfg_lane_reserve_15_8), in sparx5_sd10g28_apply_params()
1751 (params->r_en_auto_cdr_rstn), in sparx5_sd10g28_apply_params()
1757 (params->cfg_oscal_afe) | in sparx5_sd10g28_apply_params()
1759 (params->cfg_pd_osdac_afe), in sparx5_sd10g28_apply_params()
1766 (params->cfg_resetb_oscal_afe[0]), in sparx5_sd10g28_apply_params()
1772 (params->cfg_resetb_oscal_afe[1]), in sparx5_sd10g28_apply_params()
1778 (params->r_tx_pol_inv) | in sparx5_sd10g28_apply_params()
1780 (params->r_rx_pol_inv), in sparx5_sd10g28_apply_params()
1787 (params->cfg_rx2tx_lp_en) | in sparx5_sd10g28_apply_params()
1789 (params->cfg_tx2rx_lp_en), in sparx5_sd10g28_apply_params()
1795 sdx5_inst_rmw(SD10G_LANE_LANE_0E_CFG_RXLB_EN_SET(params->cfg_rxlb_en) | in sparx5_sd10g28_apply_params()
1796 SD10G_LANE_LANE_0E_CFG_TXLB_EN_SET(params->cfg_txlb_en), in sparx5_sd10g28_apply_params()
1817 sdx5_rmw(SD_LANE_MISC_SD_125_RST_DIS_SET(params->fx_100), in sparx5_sd10g28_apply_params()
1822 sdx5_rmw(SD_LANE_MISC_RX_ENA_SET(params->fx_100), in sparx5_sd10g28_apply_params()
1827 sdx5_rmw(SD_LANE_MISC_MUX_ENA_SET(params->fx_100), in sparx5_sd10g28_apply_params()
1837 dev_err(dev, "10G PMA Reset failed: 0x%x\n", value); in sparx5_sd10g28_apply_params()
1838 return -EINVAL; in sparx5_sd10g28_apply_params()
1856 struct sparx5_sd25g28_media_preset media = media_presets_25g[macro->media]; in sparx5_sd25g28_config()
1872 sparx5_sd25g28_reset(macro->priv->regs, ¶ms, macro->stpidx); in sparx5_sd25g28_config()
1878 struct sparx5_sd10g28_media_preset media = media_presets_10g[macro->media]; in sparx5_sd10g28_config()
1882 .is_6g = (macro->serdestype == SPX5_SDT_6G), in sparx5_sd10g28_config()
1894 sparx5_sd10g28_reset(macro->priv->regs, macro->sidx); in sparx5_sd10g28_config()
1901 struct sparx5_serdes_private *priv = macro->priv; in sparx5_serdes_power_save()
1904 if (macro->serdestype == SPX5_SDT_6G) in sparx5_serdes_power_save()
1905 sd_inst = sdx5_inst_get(priv, TARGET_SD6G_LANE, macro->stpidx); in sparx5_serdes_power_save()
1906 else if (macro->serdestype == SPX5_SDT_10G) in sparx5_serdes_power_save()
1907 sd_inst = sdx5_inst_get(priv, TARGET_SD10G_LANE, macro->stpidx); in sparx5_serdes_power_save()
1909 sd_inst = sdx5_inst_get(priv, TARGET_SD25G_LANE, macro->stpidx); in sparx5_serdes_power_save()
1911 if (macro->serdestype == SPX5_SDT_25G) { in sparx5_serdes_power_save()
1928 struct sparx5_serdes_private *priv = macro->priv; in sparx5_serdes_clock_config()
1930 if (macro->serdesmode == SPX5_SD_MODE_100FX) { in sparx5_serdes_clock_config()
1931 u32 freq = priv->coreclock == 250000000 ? 2 : in sparx5_serdes_clock_config()
1932 priv->coreclock == 500000000 ? 1 : 0; in sparx5_serdes_clock_config()
1937 SD_LANE_MISC(macro->sidx)); in sparx5_serdes_clock_config()
1948 void __iomem **regs = priv->regs; in sparx5_cmu_apply_cfg()
1949 struct device *dev = priv->dev; in sparx5_cmu_apply_cfg()
2052 return -EINVAL; in sparx5_cmu_apply_cfg()
2081 if (!priv->cmu_enabled) { in sparx5_serdes_cmu_enable()
2085 dev_err(priv->dev, "CMU %u, error: %d\n", idx, err); in sparx5_serdes_cmu_enable()
2089 priv->cmu_enabled = true; in sparx5_serdes_cmu_enable()
2113 return -EINVAL; in sparx5_serdes_get_serdesmode()
2119 struct device *dev = macro->priv->dev; in sparx5_serdes_config()
2123 err = sparx5_serdes_cmu_enable(macro->priv); in sparx5_serdes_config()
2127 serdesmode = sparx5_serdes_get_serdesmode(macro->portmode, macro->speed); in sparx5_serdes_config()
2130 macro->sidx, in sparx5_serdes_config()
2131 phy_modes(macro->portmode)); in sparx5_serdes_config()
2134 macro->serdesmode = serdesmode; in sparx5_serdes_config()
2138 if (macro->serdestype == SPX5_SDT_25G) in sparx5_serdes_config()
2144 macro->sidx, err); in sparx5_serdes_config()
2149 static int sparx5_serdes_power_on(struct phy *phy) in sparx5_serdes_power_on() argument
2151 struct sparx5_serdes_macro *macro = phy_get_drvdata(phy); in sparx5_serdes_power_on()
2156 static int sparx5_serdes_power_off(struct phy *phy) in sparx5_serdes_power_off() argument
2158 struct sparx5_serdes_macro *macro = phy_get_drvdata(phy); in sparx5_serdes_power_off()
2163 static int sparx5_serdes_set_mode(struct phy *phy, enum phy_mode mode, int submode) in sparx5_serdes_set_mode() argument
2168 return -EINVAL; in sparx5_serdes_set_mode()
2176 macro = phy_get_drvdata(phy); in sparx5_serdes_set_mode()
2177 macro->portmode = submode; in sparx5_serdes_set_mode()
2181 return -EINVAL; in sparx5_serdes_set_mode()
2185 static int sparx5_serdes_set_media(struct phy *phy, enum phy_media media) in sparx5_serdes_set_media() argument
2187 struct sparx5_serdes_macro *macro = phy_get_drvdata(phy); in sparx5_serdes_set_media()
2189 if (media != macro->media) { in sparx5_serdes_set_media()
2190 macro->media = media; in sparx5_serdes_set_media()
2191 if (macro->serdesmode != SPX5_SD_MODE_NONE) in sparx5_serdes_set_media()
2197 static int sparx5_serdes_set_speed(struct phy *phy, int speed) in sparx5_serdes_set_speed() argument
2199 struct sparx5_serdes_macro *macro = phy_get_drvdata(phy); in sparx5_serdes_set_speed()
2201 if (macro->sidx < SPX5_SERDES_10G_START && speed > SPEED_5000) in sparx5_serdes_set_speed()
2202 return -EINVAL; in sparx5_serdes_set_speed()
2203 if (macro->sidx < SPX5_SERDES_25G_START && speed > SPEED_10000) in sparx5_serdes_set_speed()
2204 return -EINVAL; in sparx5_serdes_set_speed()
2205 if (speed != macro->speed) { in sparx5_serdes_set_speed()
2206 macro->speed = speed; in sparx5_serdes_set_speed()
2207 if (macro->serdesmode != SPX5_SD_MODE_NONE) in sparx5_serdes_set_speed()
2213 static int sparx5_serdes_reset(struct phy *phy) in sparx5_serdes_reset() argument
2215 struct sparx5_serdes_macro *macro = phy_get_drvdata(phy); in sparx5_serdes_reset()
2218 err = sparx5_serdes_cmu_enable(macro->priv); in sparx5_serdes_reset()
2221 if (macro->serdestype == SPX5_SDT_25G) in sparx5_serdes_reset()
2226 dev_err(&phy->dev, "SerDes %u, reset error: %d\n", in sparx5_serdes_reset()
2227 macro->sidx, err); in sparx5_serdes_reset()
2232 static int sparx5_serdes_validate(struct phy *phy, enum phy_mode mode, in sparx5_serdes_validate() argument
2236 struct sparx5_serdes_macro *macro = phy_get_drvdata(phy); in sparx5_serdes_validate()
2239 return -EINVAL; in sparx5_serdes_validate()
2241 if (macro->speed == 0) in sparx5_serdes_validate()
2242 return -EINVAL; in sparx5_serdes_validate()
2244 if (macro->sidx < SPX5_SERDES_10G_START && macro->speed > SPEED_5000) in sparx5_serdes_validate()
2245 return -EINVAL; in sparx5_serdes_validate()
2246 if (macro->sidx < SPX5_SERDES_25G_START && macro->speed > SPEED_10000) in sparx5_serdes_validate()
2247 return -EINVAL; in sparx5_serdes_validate()
2251 if (macro->speed != SPEED_100 && /* This is for 100BASE-FX */ in sparx5_serdes_validate()
2252 macro->speed != SPEED_1000) in sparx5_serdes_validate()
2253 return -EINVAL; in sparx5_serdes_validate()
2258 if (macro->speed >= SPEED_5000) in sparx5_serdes_validate()
2259 return -EINVAL; in sparx5_serdes_validate()
2262 if (macro->speed < SPEED_5000) in sparx5_serdes_validate()
2263 return -EINVAL; in sparx5_serdes_validate()
2266 return -EINVAL; in sparx5_serdes_validate()
2283 int idx, struct phy **phy) in sparx5_phy_create() argument
2287 *phy = devm_phy_create(priv->dev, NULL, &sparx5_serdes_ops); in sparx5_phy_create()
2288 if (IS_ERR(*phy)) in sparx5_phy_create()
2289 return PTR_ERR(*phy); in sparx5_phy_create()
2291 macro = devm_kzalloc(priv->dev, sizeof(*macro), GFP_KERNEL); in sparx5_phy_create()
2293 return -ENOMEM; in sparx5_phy_create()
2295 macro->sidx = idx; in sparx5_phy_create()
2296 macro->priv = priv; in sparx5_phy_create()
2297 macro->speed = SPEED_UNKNOWN; in sparx5_phy_create()
2299 macro->serdestype = SPX5_SDT_6G; in sparx5_phy_create()
2300 macro->stpidx = macro->sidx; in sparx5_phy_create()
2302 macro->serdestype = SPX5_SDT_10G; in sparx5_phy_create()
2303 macro->stpidx = macro->sidx - SPX5_SERDES_10G_START; in sparx5_phy_create()
2305 macro->serdestype = SPX5_SDT_25G; in sparx5_phy_create()
2306 macro->stpidx = macro->sidx - SPX5_SERDES_25G_START; in sparx5_phy_create()
2309 phy_set_drvdata(*phy, macro); in sparx5_phy_create()
2412 static struct phy *sparx5_serdes_xlate(struct device *dev, in sparx5_serdes_xlate()
2419 if (args->args_count != 1) in sparx5_serdes_xlate()
2420 return ERR_PTR(-EINVAL); in sparx5_serdes_xlate()
2422 sidx = args->args[0]; in sparx5_serdes_xlate()
2424 /* Check validity: ERR_PTR(-ENODEV) if not valid */ in sparx5_serdes_xlate()
2427 phy_get_drvdata(priv->phys[idx]); in sparx5_serdes_xlate()
2429 if (sidx != macro->sidx) in sparx5_serdes_xlate()
2432 return priv->phys[idx]; in sparx5_serdes_xlate()
2434 return ERR_PTR(-ENODEV); in sparx5_serdes_xlate()
2439 struct device_node *np = pdev->dev.of_node; in sparx5_serdes_probe()
2449 if (!np && !pdev->dev.platform_data) in sparx5_serdes_probe()
2450 return -ENODEV; in sparx5_serdes_probe()
2452 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); in sparx5_serdes_probe()
2454 return -ENOMEM; in sparx5_serdes_probe()
2457 priv->dev = &pdev->dev; in sparx5_serdes_probe()
2460 clk = devm_clk_get(priv->dev, NULL); in sparx5_serdes_probe()
2462 dev_err(priv->dev, "Failed to get coreclock\n"); in sparx5_serdes_probe()
2467 dev_err(priv->dev, "Invalid coreclock %lu\n", clock); in sparx5_serdes_probe()
2468 return -EINVAL; in sparx5_serdes_probe()
2470 priv->coreclock = clock; in sparx5_serdes_probe()
2474 dev_err(priv->dev, "Invalid resource\n"); in sparx5_serdes_probe()
2475 return -EINVAL; in sparx5_serdes_probe()
2477 iomem = devm_ioremap(priv->dev, iores->start, resource_size(iores)); in sparx5_serdes_probe()
2479 dev_err(priv->dev, "Unable to get serdes registers: %s\n", in sparx5_serdes_probe()
2480 iores->name); in sparx5_serdes_probe()
2481 return -ENOMEM; in sparx5_serdes_probe()
2486 priv->regs[iomap->id] = iomem + iomap->offset; in sparx5_serdes_probe()
2489 err = sparx5_phy_create(priv, idx, &priv->phys[idx]); in sparx5_serdes_probe()
2494 provider = devm_of_phy_provider_register(priv->dev, sparx5_serdes_xlate); in sparx5_serdes_probe()
2500 { .compatible = "microchip,sparx5-serdes" },
2508 .name = "sparx5-serdes",