Lines Matching +full:0 +full:x4a8000
30 SPX5_SD10G28_CMU_MAIN = 0,
348 .cfg_en_adv = 0,
350 .cfg_en_dly = 0,
351 .cfg_tap_adv_3_0 = 0,
353 .cfg_tap_dly_4_0 = 0,
354 .cfg_eq_c_force_3_0 = 0xf,
363 .cfg_tap_adv_3_0 = 0,
365 .cfg_tap_dly_4_0 = 0x10,
366 .cfg_eq_c_force_3_0 = 0xf,
369 .cfg_alos_thr_2_0 = 0,
372 .cfg_en_adv = 0,
374 .cfg_en_dly = 0,
375 .cfg_tap_adv_3_0 = 0,
377 .cfg_tap_dly_4_0 = 0,
378 .cfg_eq_c_force_3_0 = 0xf,
380 .cfg_eq_r_force_3_0 = 0xc,
381 .cfg_alos_thr_2_0 = 0,
388 .tx_pre_div = 0,
389 .fifo_ck_div = 0,
391 .vco_div_mode = 0,
394 .subrate = 0,
395 .com_txcal_en = 0,
396 .com_tx_reserve_msb = (0x26 << 1),
397 .com_tx_reserve_lsb = 0xf0,
398 .cfg_itx_ipcml_base = 0,
399 .tx_reserve_msb = 0xcc,
400 .tx_reserve_lsb = 0xfe,
402 .rxterm = 0,
404 .dfe_tap = 0x1f,
408 .cfg_pi_bw_3_0 = 0,
410 .tx_tap_adv = 0xc,
414 .tx_pre_div = 0,
416 .pre_divsel = 0,
419 .ck_bitwidth = 0,
420 .subrate = 0,
422 .com_tx_reserve_msb = (0x20 << 1),
423 .com_tx_reserve_lsb = 0x40,
424 .cfg_itx_ipcml_base = 0,
425 .tx_reserve_msb = 0x4c,
426 .tx_reserve_lsb = 0x44,
428 .cfg_pi_bw_3_0 = 0,
431 .dfe_tap = 0x1f,
432 .txmargin = 0,
435 .tx_tap_dly = 0,
436 .tx_tap_adv = 0,
440 .tx_pre_div = 0,
442 .pre_divsel = 0,
445 .ck_bitwidth = 0,
446 .subrate = 0,
448 .com_tx_reserve_msb = (0x20 << 1),
449 .com_tx_reserve_lsb = 0,
450 .cfg_itx_ipcml_base = 0,
451 .tx_reserve_msb = 0xe,
452 .tx_reserve_lsb = 0x80,
453 .bw = 0,
454 .rxterm = 0,
456 .dfe_enable = 0,
457 .dfe_tap = 0,
458 .tx_tap_dly = 0,
459 .tx_tap_adv = 0,
463 .tx_pre_div = 0,
464 .fifo_ck_div = 0,
465 .pre_divsel = 0,
471 .com_tx_reserve_msb = (0x26 << 1),
472 .com_tx_reserve_lsb = (0xf << 4),
474 .tx_reserve_msb = 0x8,
475 .tx_reserve_lsb = 0x8a,
476 .bw = 0,
477 .cfg_pi_bw_3_0 = 0,
479 .dfe_enable = 0,
480 .dfe_tap = 0,
481 .tx_tap_dly = 0,
482 .tx_tap_adv = 0,
486 .tx_pre_div = 0,
488 .pre_divsel = 0,
494 .com_tx_reserve_msb = (0x26 << 1),
495 .com_tx_reserve_lsb = 0xf0,
496 .cfg_itx_ipcml_base = 0,
497 .tx_reserve_msb = 0x8,
498 .tx_reserve_lsb = 0xce,
499 .bw = 0,
500 .rxterm = 0,
501 .cfg_pi_bw_3_0 = 0,
502 .dfe_enable = 0,
503 .dfe_tap = 0,
504 .tx_tap_dly = 0,
505 .tx_tap_adv = 0,
511 .cfg_en_adv = 0,
513 .cfg_en_dly = 0,
514 .cfg_tap_adv_3_0 = 0,
516 .cfg_tap_dly_4_0 = 0,
518 .cfg_vga_cp_2_0 = 0,
519 .cfg_eq_res_3_0 = 0xa,
521 .cfg_eq_c_force_3_0 = 0x8,
522 .cfg_alos_thr_3_0 = 0x3,
528 .cfg_tap_adv_3_0 = 0,
530 .cfg_tap_dly_4_0 = 0xc,
531 .cfg_vga_ctrl_3_0 = 0xa,
532 .cfg_vga_cp_2_0 = 0x4,
533 .cfg_eq_res_3_0 = 0xa,
535 .cfg_eq_c_force_3_0 = 0xF,
536 .cfg_alos_thr_3_0 = 0x3,
545 .cfg_vga_ctrl_3_0 = 0xa,
547 .cfg_eq_res_3_0 = 0xa,
549 .cfg_eq_c_force_3_0 = 0xf,
550 .cfg_alos_thr_3_0 = 0x0,
558 .rate = 0x0,
560 .dfe_tap = 0x1f,
561 .pi_bw_gen1 = 0x0,
562 .duty_cycle = 0x2,
567 .rate = 0x1,
568 .dfe_enable = 0,
569 .dfe_tap = 0,
570 .pi_bw_gen1 = 0x5,
571 .duty_cycle = 0x0,
576 .rate = 0x1,
577 .dfe_enable = 0,
578 .dfe_tap = 0,
579 .pi_bw_gen1 = 0x5,
580 .duty_cycle = 0x0,
585 .rate = 0x1,
586 .dfe_enable = 0,
587 .dfe_tap = 0,
588 .pi_bw_gen1 = 0x5,
589 .duty_cycle = 0x0,
594 .rate = 0x2,
595 .dfe_enable = 0,
596 .dfe_tap = 0,
597 .pi_bw_gen1 = 0x7,
598 .duty_cycle = 0x0,
603 .rate = 0x3,
604 .dfe_enable = 0,
605 .dfe_tap = 0,
606 .pi_bw_gen1 = 0x7,
607 .duty_cycle = 0x0,
615 case 10: return 0; in sd25g28_get_iw_setting()
624 return 0; in sd25g28_get_iw_setting()
631 case 10: return 0; in sd10g28_get_iw_setting()
640 return 0; in sd10g28_get_iw_setting()
669 return 0; in sparx5_sd10g25_get_mode_preset()
706 return 0; in sparx5_sd10g28_get_mode_preset()
723 .cfg_vco_start_code_3_0 = 0, in sparx5_sd25g28_get_params()
729 .r_multi_lane_mode = 0, in sparx5_sd25g28_get_params()
732 .cfg_dfe_pd = mode->dfe_enable == 1 ? 0 : 1, in sparx5_sd25g28_get_params()
735 .cfg_dmux_pd = 0, in sparx5_sd25g28_get_params()
737 .cfg_erramp_pd = mode->dfe_enable == 1 ? 0 : 1, in sparx5_sd25g28_get_params()
740 .cfg_pd_ctle = 0, in sparx5_sd25g28_get_params()
742 .cfg_pmad_ck_pd = 0, in sparx5_sd25g28_get_params()
743 .cfg_pd_clk = 0, in sparx5_sd25g28_get_params()
744 .cfg_pd_cml = 0, in sparx5_sd25g28_get_params()
745 .cfg_pd_driver = 0, in sparx5_sd25g28_get_params()
748 .cfg_dcdr_pd = 0, in sparx5_sd25g28_get_params()
758 .cfg_iscan_en = 0, in sparx5_sd25g28_get_params()
759 .l1_pcs_en_fast_iscan = 0, in sparx5_sd25g28_get_params()
760 .l0_cfg_bw_1_0 = 0, in sparx5_sd25g28_get_params()
761 .cfg_en_dummy = 0, in sparx5_sd25g28_get_params()
770 .cfg_phase_man_4_0 = 0, in sparx5_sd25g28_get_params()
771 .cfg_quad_man_1_0 = 0, in sparx5_sd25g28_get_params()
774 .cfg_txcal_en = 0, in sparx5_sd25g28_get_params()
778 .cfg_pi_steps_1_0 = 0, in sparx5_sd25g28_get_params()
784 .cfg_rx_reserve_7_0 = 0xbf, in sparx5_sd25g28_get_params()
785 .cfg_rx_reserve_15_8 = 0x61, in sparx5_sd25g28_get_params()
787 .cfg_fom_selm = 0, in sparx5_sd25g28_get_params()
788 .cfg_rx_sp_ctle_1_0 = 0, in sparx5_sd25g28_get_params()
789 .cfg_isel_ctle_1_0 = 0, in sparx5_sd25g28_get_params()
802 .r_d_width_ctrl_from_hwt = 0, in sparx5_sd25g28_get_params()
808 .cfg_tx2rx_lp_en = 0, in sparx5_sd25g28_get_params()
809 .cfg_txlb_en = 0, in sparx5_sd25g28_get_params()
810 .cfg_rx2tx_lp_en = 0, in sparx5_sd25g28_get_params()
811 .cfg_rxlb_en = 0, in sparx5_sd25g28_get_params()
839 .r_pcs2pma_phymode_4_0 = 0, in sparx5_sd10g28_get_params()
840 .cfg_lane_id_2_0 = 0, in sparx5_sd10g28_get_params()
843 .cfg_dfe_pd = (mode->dfe_enable == 1) ? 0 : 1, in sparx5_sd10g28_get_params()
845 .cfg_erramp_pd = (mode->dfe_enable == 1) ? 0 : 1, in sparx5_sd10g28_get_params()
848 .cfg_pd_ctle = 0, in sparx5_sd10g28_get_params()
850 .cfg_pd_rx_cktree = 0, in sparx5_sd10g28_get_params()
851 .cfg_pd_clk = 0, in sparx5_sd10g28_get_params()
852 .cfg_pd_cml = 0, in sparx5_sd10g28_get_params()
853 .cfg_pd_driver = 0, in sparx5_sd10g28_get_params()
855 .cfg_d_cdr_pd = 0, in sparx5_sd10g28_get_params()
857 .cfg_rxdet_en = 0, in sparx5_sd10g28_get_params()
858 .cfg_rxdet_str = 0, in sparx5_sd10g28_get_params()
859 .r_multi_lane_mode = 0, in sparx5_sd10g28_get_params()
873 .cfg_en_preemph = 0, in sparx5_sd10g28_get_params()
874 .cfg_itx_ippreemp_base_1_0 = 0, in sparx5_sd10g28_get_params()
878 .cfg_dis_2nd_order = 0x1, in sparx5_sd10g28_get_params()
879 .cfg_rx_ssc_lh = 0x0, in sparx5_sd10g28_get_params()
880 .cfg_pi_floop_steps_1_0 = 0x0, in sparx5_sd10g28_get_params()
882 .cfg_pi_ext_dac_15_8 = (0 << 6), in sparx5_sd10g28_get_params()
894 .cfg_pi_steps = 0, in sparx5_sd10g28_get_params()
899 .cfg_itx_ipcml_base_1_0 = 0, in sparx5_sd10g28_get_params()
900 .cfg_ip_pre_base_1_0 = 0, in sparx5_sd10g28_get_params()
904 .r_en_auto_cdr_rstn = 0, in sparx5_sd10g28_get_params()
906 .cfg_pd_osdac_afe = 0, in sparx5_sd10g28_get_params()
907 .cfg_resetb_oscal_afe[0] = 0, in sparx5_sd10g28_get_params()
909 .cfg_center_spreading = 0, in sparx5_sd10g28_get_params()
914 .cfg_tx2rx_lp_en = 0, in sparx5_sd10g28_get_params()
915 .cfg_txlb_en = 0, in sparx5_sd10g28_get_params()
916 .cfg_rx2tx_lp_en = 0, in sparx5_sd10g28_get_params()
917 .cfg_rxlb_en = 0, in sparx5_sd10g28_get_params()
936 sdx5_rmw_addr(SD_LANE_25G_SD_LANE_CFG_EXT_CFG_RST_SET(0), in sparx5_sd25g28_reset()
956 sdx5_rmw(SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX_SET(0xFF), in sparx5_sd25g28_apply_params()
1003 sdx5_rmw(SD25G_LANE_CMU_0B_CFG_VCO_CAL_RESETN_SET(0), in sparx5_sd25g28_apply_params()
1013 sdx5_rmw(SD25G_LANE_CMU_19_R_CK_RESETB_SET(0), in sparx5_sd25g28_apply_params()
1023 sdx5_rmw(SD25G_LANE_CMU_18_R_PLL_RSTN_SET(0), in sparx5_sd25g28_apply_params()
1066 sdx5_rmw(SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX_SET(0x00), in sparx5_sd25g28_apply_params()
1314 sdx5_rmw(SD25G_LANE_LANE_2E_LN_CFG_RSTN_DFEDIG_SET(0), in sparx5_sd25g28_apply_params()
1324 sdx5_rmw(SD_LANE_25G_SD_LANE_CFG_MACRO_RST_SET(0), in sparx5_sd25g28_apply_params()
1329 sdx5_rmw(SD25G_LANE_LANE_1C_LN_CFG_CDR_RSTN_SET(0), in sparx5_sd25g28_apply_params()
1343 sdx5_rmw(SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX_SET(0xff), in sparx5_sd25g28_apply_params()
1352 dev_err(dev, "25G PLL Loss of Lock: 0x%x\n", value); in sparx5_sd25g28_apply_params()
1359 if (value != 0x1) { in sparx5_sd25g28_apply_params()
1360 dev_err(dev, "25G PMA Reset failed: 0x%x\n", value); in sparx5_sd25g28_apply_params()
1363 sdx5_rmw(SD25G_LANE_CMU_2A_R_DBG_LOL_STATUS_SET(0x1), in sparx5_sd25g28_apply_params()
1368 sdx5_rmw(SD_LANE_25G_SD_SER_RST_SER_RST_SET(0x0), in sparx5_sd25g28_apply_params()
1373 sdx5_rmw(SD_LANE_25G_SD_DES_RST_DES_RST_SET(0x0), in sparx5_sd25g28_apply_params()
1378 sdx5_rmw(SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX_SET(0), in sparx5_sd25g28_apply_params()
1389 sdx5_rmw(SD25G_LANE_LANE_2E_LN_CFG_DIS_SQ_SET(0), in sparx5_sd25g28_apply_params()
1394 sdx5_rmw(SD25G_LANE_LANE_2E_LN_CFG_PD_SQ_SET(0), in sparx5_sd25g28_apply_params()
1399 return 0; in sparx5_sd25g28_apply_params()
1411 sdx5_rmw_addr(SD_LANE_SD_LANE_CFG_EXT_CFG_RST_SET(0), in sparx5_sd10g28_reset()
1437 sdx5_inst_rmw(SD10G_LANE_LANE_93_R_DWIDTHCTRL_FROM_HWT_SET(0x0) | in sparx5_sd10g28_apply_params()
1438 SD10G_LANE_LANE_93_R_REG_MANUAL_SET(0x1) | in sparx5_sd10g28_apply_params()
1439 SD10G_LANE_LANE_93_R_AUXCKSEL_FROM_HWT_SET(0x1) | in sparx5_sd10g28_apply_params()
1440 SD10G_LANE_LANE_93_R_LANE_ID_FROM_HWT_SET(0x1) | in sparx5_sd10g28_apply_params()
1441 SD10G_LANE_LANE_93_R_EN_RATECHG_CTRL_SET(0x0), in sparx5_sd10g28_apply_params()
1450 sdx5_inst_rmw(SD10G_LANE_LANE_94_R_ISCAN_REG_SET(0x1) | in sparx5_sd10g28_apply_params()
1451 SD10G_LANE_LANE_94_R_TXEQ_REG_SET(0x1) | in sparx5_sd10g28_apply_params()
1452 SD10G_LANE_LANE_94_R_MISC_REG_SET(0x1) | in sparx5_sd10g28_apply_params()
1453 SD10G_LANE_LANE_94_R_SWING_REG_SET(0x1), in sparx5_sd10g28_apply_params()
1461 sdx5_inst_rmw(SD10G_LANE_LANE_9E_R_RXEQ_REG_SET(0x1), in sparx5_sd10g28_apply_params()
1466 sdx5_inst_rmw(SD10G_LANE_LANE_A1_R_SSC_FROM_HWT_SET(0x0) | in sparx5_sd10g28_apply_params()
1467 SD10G_LANE_LANE_A1_R_CDR_FROM_HWT_SET(0x0) | in sparx5_sd10g28_apply_params()
1468 SD10G_LANE_LANE_A1_R_PCLK_GATING_FROM_HWT_SET(0x1), in sparx5_sd10g28_apply_params()
1766 (params->cfg_resetb_oscal_afe[0]), in sparx5_sd10g28_apply_params()
1802 sdx5_rmw(SD_LANE_SD_LANE_CFG_MACRO_RST_SET(0), in sparx5_sd10g28_apply_params()
1837 dev_err(dev, "10G PMA Reset failed: 0x%x\n", value); in sparx5_sd10g28_apply_params()
1841 sdx5_rmw(SD_LANE_SD_SER_RST_SER_RST_SET(0x0), in sparx5_sd10g28_apply_params()
1846 sdx5_rmw(SD_LANE_SD_DES_RST_DES_RST_SET(0x0), in sparx5_sd10g28_apply_params()
1851 return 0; in sparx5_sd10g28_apply_params()
1860 .txinvert = 0, in sparx5_sd25g28_config()
1862 .com_pll_reserve = 0xf, in sparx5_sd25g28_config()
1883 .txinvert = 0, in sparx5_sd10g28_config()
1915 SD25G_LANE_LANE_04(0)); in sparx5_serdes_power_save()
1921 SD10G_LANE_LANE_06(0)); in sparx5_serdes_power_save()
1923 return 0; in sparx5_serdes_power_save()
1932 priv->coreclock == 500000000 ? 1 : 0; in sparx5_serdes_clock_config()
1939 return 0; in sparx5_serdes_clock_config()
1957 spd10g = 0; in sparx5_cmu_apply_cfg()
1965 sdx5_inst_rmw(SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST_SET(0), in sparx5_cmu_apply_cfg()
1975 sdx5_inst_rmw(SD_CMU_CMU_45_R_DWIDTHCTRL_FROM_HWT_SET(0x1) | in sparx5_cmu_apply_cfg()
1976 SD_CMU_CMU_45_R_REFCK_SSC_EN_FROM_HWT_SET(0x1) | in sparx5_cmu_apply_cfg()
1977 SD_CMU_CMU_45_R_LINK_BUF_EN_FROM_HWT_SET(0x1) | in sparx5_cmu_apply_cfg()
1978 SD_CMU_CMU_45_R_BIAS_EN_FROM_HWT_SET(0x1) | in sparx5_cmu_apply_cfg()
1979 SD_CMU_CMU_45_R_EN_RATECHG_CTRL_SET(0x0), in sparx5_cmu_apply_cfg()
1988 sdx5_inst_rmw(SD_CMU_CMU_47_R_PCS2PMA_PHYMODE_4_0_SET(0), in sparx5_cmu_apply_cfg()
1993 sdx5_inst_rmw(SD_CMU_CMU_1B_CFG_RESERVE_7_0_SET(0), in sparx5_cmu_apply_cfg()
1998 sdx5_inst_rmw(SD_CMU_CMU_0D_CFG_JC_BYP_SET(0x1), in sparx5_cmu_apply_cfg()
2028 sdx5_inst_rmw(SD_CMU_CFG_SD_CMU_CFG_CMU_RST_SET(0), in sparx5_cmu_apply_cfg()
2035 sdx5_inst_rmw(SD_CMU_CMU_44_R_PLL_RSTN_SET(0), in sparx5_cmu_apply_cfg()
2051 dev_err(dev, "CMU PLL Loss of Lock: 0x%x\n", value); in sparx5_cmu_apply_cfg()
2054 sdx5_inst_rmw(SD_CMU_CMU_0D_CFG_PMA_TX_CK_PD_SET(0), in sparx5_cmu_apply_cfg()
2058 return 0; in sparx5_cmu_apply_cfg()
2068 spd10g = 0; in sparx5_cmu_cfg()
2079 int idx, err = 0; in sparx5_serdes_cmu_enable()
2082 for (idx = 0; idx < SPX5_CMU_MAX; idx++) { in sparx5_serdes_cmu_enable()
2128 if (serdesmode < 0) { in sparx5_serdes_config()
2179 return 0; in sparx5_serdes_set_mode()
2194 return 0; in sparx5_serdes_set_media()
2210 return 0; in sparx5_serdes_set_speed()
2241 if (macro->speed == 0) in sparx5_serdes_validate()
2268 return 0; in sparx5_serdes_validate()
2311 return 0; in sparx5_phy_create()
2315 { TARGET_SD_CMU, 0x0 }, /* 0x610808000: sd_cmu_0 */
2316 { TARGET_SD_CMU + 1, 0x8000 }, /* 0x610810000: sd_cmu_1 */
2317 { TARGET_SD_CMU + 2, 0x10000 }, /* 0x610818000: sd_cmu_2 */
2318 { TARGET_SD_CMU + 3, 0x18000 }, /* 0x610820000: sd_cmu_3 */
2319 { TARGET_SD_CMU + 4, 0x20000 }, /* 0x610828000: sd_cmu_4 */
2320 { TARGET_SD_CMU + 5, 0x28000 }, /* 0x610830000: sd_cmu_5 */
2321 { TARGET_SD_CMU + 6, 0x30000 }, /* 0x610838000: sd_cmu_6 */
2322 { TARGET_SD_CMU + 7, 0x38000 }, /* 0x610840000: sd_cmu_7 */
2323 { TARGET_SD_CMU + 8, 0x40000 }, /* 0x610848000: sd_cmu_8 */
2324 { TARGET_SD_CMU_CFG, 0x48000 }, /* 0x610850000: sd_cmu_cfg_0 */
2325 { TARGET_SD_CMU_CFG + 1, 0x50000 }, /* 0x610858000: sd_cmu_cfg_1 */
2326 { TARGET_SD_CMU_CFG + 2, 0x58000 }, /* 0x610860000: sd_cmu_cfg_2 */
2327 { TARGET_SD_CMU_CFG + 3, 0x60000 }, /* 0x610868000: sd_cmu_cfg_3 */
2328 { TARGET_SD_CMU_CFG + 4, 0x68000 }, /* 0x610870000: sd_cmu_cfg_4 */
2329 { TARGET_SD_CMU_CFG + 5, 0x70000 }, /* 0x610878000: sd_cmu_cfg_5 */
2330 { TARGET_SD_CMU_CFG + 6, 0x78000 }, /* 0x610880000: sd_cmu_cfg_6 */
2331 { TARGET_SD_CMU_CFG + 7, 0x80000 }, /* 0x610888000: sd_cmu_cfg_7 */
2332 { TARGET_SD_CMU_CFG + 8, 0x88000 }, /* 0x610890000: sd_cmu_cfg_8 */
2333 { TARGET_SD6G_LANE, 0x90000 }, /* 0x610898000: sd6g_lane_0 */
2334 { TARGET_SD6G_LANE + 1, 0x98000 }, /* 0x6108a0000: sd6g_lane_1 */
2335 { TARGET_SD6G_LANE + 2, 0xa0000 }, /* 0x6108a8000: sd6g_lane_2 */
2336 { TARGET_SD6G_LANE + 3, 0xa8000 }, /* 0x6108b0000: sd6g_lane_3 */
2337 { TARGET_SD6G_LANE + 4, 0xb0000 }, /* 0x6108b8000: sd6g_lane_4 */
2338 { TARGET_SD6G_LANE + 5, 0xb8000 }, /* 0x6108c0000: sd6g_lane_5 */
2339 { TARGET_SD6G_LANE + 6, 0xc0000 }, /* 0x6108c8000: sd6g_lane_6 */
2340 { TARGET_SD6G_LANE + 7, 0xc8000 }, /* 0x6108d0000: sd6g_lane_7 */
2341 { TARGET_SD6G_LANE + 8, 0xd0000 }, /* 0x6108d8000: sd6g_lane_8 */
2342 { TARGET_SD6G_LANE + 9, 0xd8000 }, /* 0x6108e0000: sd6g_lane_9 */
2343 { TARGET_SD6G_LANE + 10, 0xe0000 }, /* 0x6108e8000: sd6g_lane_10 */
2344 { TARGET_SD6G_LANE + 11, 0xe8000 }, /* 0x6108f0000: sd6g_lane_11 */
2345 { TARGET_SD6G_LANE + 12, 0xf0000 }, /* 0x6108f8000: sd6g_lane_12 */
2346 { TARGET_SD10G_LANE, 0xf8000 }, /* 0x610900000: sd10g_lane_0 */
2347 { TARGET_SD10G_LANE + 1, 0x100000 }, /* 0x610908000: sd10g_lane_1 */
2348 { TARGET_SD10G_LANE + 2, 0x108000 }, /* 0x610910000: sd10g_lane_2 */
2349 { TARGET_SD10G_LANE + 3, 0x110000 }, /* 0x610918000: sd10g_lane_3 */
2350 { TARGET_SD_LANE, 0x1a0000 }, /* 0x6109a8000: sd_lane_0 */
2351 { TARGET_SD_LANE + 1, 0x1a8000 }, /* 0x6109b0000: sd_lane_1 */
2352 { TARGET_SD_LANE + 2, 0x1b0000 }, /* 0x6109b8000: sd_lane_2 */
2353 { TARGET_SD_LANE + 3, 0x1b8000 }, /* 0x6109c0000: sd_lane_3 */
2354 { TARGET_SD_LANE + 4, 0x1c0000 }, /* 0x6109c8000: sd_lane_4 */
2355 { TARGET_SD_LANE + 5, 0x1c8000 }, /* 0x6109d0000: sd_lane_5 */
2356 { TARGET_SD_LANE + 6, 0x1d0000 }, /* 0x6109d8000: sd_lane_6 */
2357 { TARGET_SD_LANE + 7, 0x1d8000 }, /* 0x6109e0000: sd_lane_7 */
2358 { TARGET_SD_LANE + 8, 0x1e0000 }, /* 0x6109e8000: sd_lane_8 */
2359 { TARGET_SD_LANE + 9, 0x1e8000 }, /* 0x6109f0000: sd_lane_9 */
2360 { TARGET_SD_LANE + 10, 0x1f0000 }, /* 0x6109f8000: sd_lane_10 */
2361 { TARGET_SD_LANE + 11, 0x1f8000 }, /* 0x610a00000: sd_lane_11 */
2362 { TARGET_SD_LANE + 12, 0x200000 }, /* 0x610a08000: sd_lane_12 */
2363 { TARGET_SD_LANE + 13, 0x208000 }, /* 0x610a10000: sd_lane_13 */
2364 { TARGET_SD_LANE + 14, 0x210000 }, /* 0x610a18000: sd_lane_14 */
2365 { TARGET_SD_LANE + 15, 0x218000 }, /* 0x610a20000: sd_lane_15 */
2366 { TARGET_SD_LANE + 16, 0x220000 }, /* 0x610a28000: sd_lane_16 */
2367 { TARGET_SD_CMU + 9, 0x400000 }, /* 0x610c08000: sd_cmu_9 */
2368 { TARGET_SD_CMU + 10, 0x408000 }, /* 0x610c10000: sd_cmu_10 */
2369 { TARGET_SD_CMU + 11, 0x410000 }, /* 0x610c18000: sd_cmu_11 */
2370 { TARGET_SD_CMU + 12, 0x418000 }, /* 0x610c20000: sd_cmu_12 */
2371 { TARGET_SD_CMU + 13, 0x420000 }, /* 0x610c28000: sd_cmu_13 */
2372 { TARGET_SD_CMU_CFG + 9, 0x428000 }, /* 0x610c30000: sd_cmu_cfg_9 */
2373 { TARGET_SD_CMU_CFG + 10, 0x430000 }, /* 0x610c38000: sd_cmu_cfg_10 */
2374 { TARGET_SD_CMU_CFG + 11, 0x438000 }, /* 0x610c40000: sd_cmu_cfg_11 */
2375 { TARGET_SD_CMU_CFG + 12, 0x440000 }, /* 0x610c48000: sd_cmu_cfg_12 */
2376 { TARGET_SD_CMU_CFG + 13, 0x448000 }, /* 0x610c50000: sd_cmu_cfg_13 */
2377 { TARGET_SD10G_LANE + 4, 0x450000 }, /* 0x610c58000: sd10g_lane_4 */
2378 { TARGET_SD10G_LANE + 5, 0x458000 }, /* 0x610c60000: sd10g_lane_5 */
2379 { TARGET_SD10G_LANE + 6, 0x460000 }, /* 0x610c68000: sd10g_lane_6 */
2380 { TARGET_SD10G_LANE + 7, 0x468000 }, /* 0x610c70000: sd10g_lane_7 */
2381 { TARGET_SD10G_LANE + 8, 0x470000 }, /* 0x610c78000: sd10g_lane_8 */
2382 { TARGET_SD10G_LANE + 9, 0x478000 }, /* 0x610c80000: sd10g_lane_9 */
2383 { TARGET_SD10G_LANE + 10, 0x480000 }, /* 0x610c88000: sd10g_lane_10 */
2384 { TARGET_SD10G_LANE + 11, 0x488000 }, /* 0x610c90000: sd10g_lane_11 */
2385 { TARGET_SD25G_LANE, 0x490000 }, /* 0x610c98000: sd25g_lane_0 */
2386 { TARGET_SD25G_LANE + 1, 0x498000 }, /* 0x610ca0000: sd25g_lane_1 */
2387 { TARGET_SD25G_LANE + 2, 0x4a0000 }, /* 0x610ca8000: sd25g_lane_2 */
2388 { TARGET_SD25G_LANE + 3, 0x4a8000 }, /* 0x610cb0000: sd25g_lane_3 */
2389 { TARGET_SD25G_LANE + 4, 0x4b0000 }, /* 0x610cb8000: sd25g_lane_4 */
2390 { TARGET_SD25G_LANE + 5, 0x4b8000 }, /* 0x610cc0000: sd25g_lane_5 */
2391 { TARGET_SD25G_LANE + 6, 0x4c0000 }, /* 0x610cc8000: sd25g_lane_6 */
2392 { TARGET_SD25G_LANE + 7, 0x4c8000 }, /* 0x610cd0000: sd25g_lane_7 */
2393 { TARGET_SD_LANE + 17, 0x550000 }, /* 0x610d58000: sd_lane_17 */
2394 { TARGET_SD_LANE + 18, 0x558000 }, /* 0x610d60000: sd_lane_18 */
2395 { TARGET_SD_LANE + 19, 0x560000 }, /* 0x610d68000: sd_lane_19 */
2396 { TARGET_SD_LANE + 20, 0x568000 }, /* 0x610d70000: sd_lane_20 */
2397 { TARGET_SD_LANE + 21, 0x570000 }, /* 0x610d78000: sd_lane_21 */
2398 { TARGET_SD_LANE + 22, 0x578000 }, /* 0x610d80000: sd_lane_22 */
2399 { TARGET_SD_LANE + 23, 0x580000 }, /* 0x610d88000: sd_lane_23 */
2400 { TARGET_SD_LANE + 24, 0x588000 }, /* 0x610d90000: sd_lane_24 */
2401 { TARGET_SD_LANE_25G, 0x590000 }, /* 0x610d98000: sd_lane_25g_25 */
2402 { TARGET_SD_LANE_25G + 1, 0x598000 }, /* 0x610da0000: sd_lane_25g_26 */
2403 { TARGET_SD_LANE_25G + 2, 0x5a0000 }, /* 0x610da8000: sd_lane_25g_27 */
2404 { TARGET_SD_LANE_25G + 3, 0x5a8000 }, /* 0x610db0000: sd_lane_25g_28 */
2405 { TARGET_SD_LANE_25G + 4, 0x5b0000 }, /* 0x610db8000: sd_lane_25g_29 */
2406 { TARGET_SD_LANE_25G + 5, 0x5b8000 }, /* 0x610dc0000: sd_lane_25g_30 */
2407 { TARGET_SD_LANE_25G + 6, 0x5c0000 }, /* 0x610dc8000: sd_lane_25g_31 */
2408 { TARGET_SD_LANE_25G + 7, 0x5c8000 }, /* 0x610dd0000: sd_lane_25g_32 */
2422 sidx = args->args[0]; in sparx5_serdes_xlate()
2425 for (idx = 0; idx < SPX5_SERDES_MAX; idx++) { in sparx5_serdes_xlate()
2466 if (clock == 0) { in sparx5_serdes_probe()
2472 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); in sparx5_serdes_probe()
2483 for (idx = 0; idx < ARRAY_SIZE(sparx5_serdes_iomap); idx++) { in sparx5_serdes_probe()
2488 for (idx = 0; idx < SPX5_SERDES_MAX; idx++) { in sparx5_serdes_probe()