Lines Matching +full:0 +full:x238
17 #define PHY_OFFSET 0x1000
19 #define MTK_DP_PHY_DIG_PLL_CTL_1 (PHY_OFFSET + 0x14)
22 #define MTK_DP_PHY_DIG_BIT_RATE (PHY_OFFSET + 0x3C)
23 #define BIT_RATE_RBR 0
28 #define MTK_DP_PHY_DIG_SW_RST (PHY_OFFSET + 0x38)
29 #define DP_GLB_SW_RST_PHYD BIT(0)
31 #define MTK_DP_LANE0_DRIVING_PARAM_3 (PHY_OFFSET + 0x138)
32 #define MTK_DP_LANE1_DRIVING_PARAM_3 (PHY_OFFSET + 0x238)
33 #define MTK_DP_LANE2_DRIVING_PARAM_3 (PHY_OFFSET + 0x338)
34 #define MTK_DP_LANE3_DRIVING_PARAM_3 (PHY_OFFSET + 0x438)
58 #define XTP_LN_TX_LCTXCP1_SW0_PRE0_DEFAULT 0
67 #define XTP_LN_TX_LCTXCP1_SW1_PRE0_DEFAULT 0
70 #define XTP_LN_TX_LCTXCP1_SW2_PRE0_DEFAULT 0
77 #define XTP_LN_TX_LCTXCP1_SW3_PRE0_DEFAULT 0
106 return 0; in mtk_dp_phy_init()
138 TPLL_SSC_EN, opts->dp.ssc ? TPLL_SSC_EN : 0); in mtk_dp_phy_configure()
140 return 0; in mtk_dp_phy_configure()
148 DP_GLB_SW_RST_PHYD, 0); in mtk_dp_phy_reset()
153 return 0; in mtk_dp_phy_reset()
189 return 0; in mtk_dp_phy_probe()