128  * A lane is described by the following bitfields:
181 	unsigned lane;  member
189 		.lane = _lane,				\
199 		.lane = _lane,				\
208 	/* lane 0 */
213 	/* lane 1 */
220 	/* lane 2 */
229 	/* lane 3 */
236 	/* lane 4 */
249 	/* lane 5 */
276 			    unsigned long lane, unsigned long mode)  in mvebu_comphy_smc()  argument
281 	arm_smccc_smc(function, phys, lane, mode, 0, 0, 0, 0, &res);  in mvebu_comphy_smc()
294 static int mvebu_comphy_get_mode(bool fw_mode, int lane, int port,  in mvebu_comphy_get_mode()  argument
308 		if (conf->lane == lane &&  in mvebu_comphy_get_mode()
324 static inline int mvebu_comphy_get_mux(int lane, int port,  in mvebu_comphy_get_mux()  argument
327 	return mvebu_comphy_get_mode(false, lane, port, mode, submode);  in mvebu_comphy_get_mux()
330 static inline int mvebu_comphy_get_fw_mode(int lane, int port,  in mvebu_comphy_get_fw_mode()  argument
333 	return mvebu_comphy_get_mode(true, lane, port, mode, submode);  in mvebu_comphy_get_fw_mode()
336 static int mvebu_comphy_ethernet_init_reset(struct mvebu_comphy_lane *lane)  in mvebu_comphy_ethernet_init_reset()  argument
338 	struct mvebu_comphy_priv *priv = lane->priv;  in mvebu_comphy_ethernet_init_reset()
341 	regmap_read(priv->regmap, MVEBU_COMPHY_CONF1(lane->id), &val);  in mvebu_comphy_ethernet_init_reset()
344 	regmap_write(priv->regmap, MVEBU_COMPHY_CONF1(lane->id), val);  in mvebu_comphy_ethernet_init_reset()
347 	val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG0(lane->id));  in mvebu_comphy_ethernet_init_reset()
356 	switch (lane->submode) {  in mvebu_comphy_ethernet_init_reset()
378 			"unsupported comphy submode (%d) on lane %d\n",  in mvebu_comphy_ethernet_init_reset()
379 			lane->submode,  in mvebu_comphy_ethernet_init_reset()
380 			lane->id);  in mvebu_comphy_ethernet_init_reset()
384 	writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG0(lane->id));  in mvebu_comphy_ethernet_init_reset()
386 	if (lane->submode == PHY_INTERFACE_MODE_RXAUI) {  in mvebu_comphy_ethernet_init_reset()
389 		switch (lane->id) {  in mvebu_comphy_ethernet_init_reset()
400 				"RXAUI is not supported on comphy lane %d\n",  in mvebu_comphy_ethernet_init_reset()
401 				lane->id);  in mvebu_comphy_ethernet_init_reset()
409 	val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));  in mvebu_comphy_ethernet_init_reset()
413 	writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));  in mvebu_comphy_ethernet_init_reset()
416 	val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));  in mvebu_comphy_ethernet_init_reset()
419 	writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));  in mvebu_comphy_ethernet_init_reset()
425 	regmap_read(priv->regmap, MVEBU_COMPHY_CONF6(lane->id), &val);  in mvebu_comphy_ethernet_init_reset()
427 	regmap_write(priv->regmap, MVEBU_COMPHY_CONF6(lane->id), val);  in mvebu_comphy_ethernet_init_reset()
430 	val = readl(priv->base + MVEBU_COMPHY_MISC_CTRL0(lane->id));  in mvebu_comphy_ethernet_init_reset()
432 	if (lane->submode == PHY_INTERFACE_MODE_10GBASER)  in mvebu_comphy_ethernet_init_reset()
434 	writel(val, priv->base + MVEBU_COMPHY_MISC_CTRL0(lane->id));  in mvebu_comphy_ethernet_init_reset()
437 	val = readl(priv->base + MVEBU_COMPHY_PWRPLL_CTRL(lane->id));  in mvebu_comphy_ethernet_init_reset()
442 	writel(val, priv->base + MVEBU_COMPHY_PWRPLL_CTRL(lane->id));  in mvebu_comphy_ethernet_init_reset()
444 	val = readl(priv->base + MVEBU_COMPHY_LOOPBACK(lane->id));  in mvebu_comphy_ethernet_init_reset()
447 	writel(val, priv->base + MVEBU_COMPHY_LOOPBACK(lane->id));  in mvebu_comphy_ethernet_init_reset()
452 static int mvebu_comphy_init_plls(struct mvebu_comphy_lane *lane)  in mvebu_comphy_init_plls()  argument
454 	struct mvebu_comphy_priv *priv = lane->priv;  in mvebu_comphy_init_plls()
458 	val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG0(lane->id));  in mvebu_comphy_init_plls()
462 	writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG0(lane->id));  in mvebu_comphy_init_plls()
465 	readl_poll_timeout(priv->base + MVEBU_COMPHY_SERDES_STATUS0(lane->id),  in mvebu_comphy_init_plls()
475 	val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));  in mvebu_comphy_init_plls()
477 	writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));  in mvebu_comphy_init_plls()
480 	readl_poll_timeout(priv->base + MVEBU_COMPHY_SERDES_STATUS0(lane->id),  in mvebu_comphy_init_plls()
486 	val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));  in mvebu_comphy_init_plls()
488 	writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));  in mvebu_comphy_init_plls()
495 	struct mvebu_comphy_lane *lane = phy_get_drvdata(phy);  in mvebu_comphy_set_mode_sgmii()  local
496 	struct mvebu_comphy_priv *priv = lane->priv;  in mvebu_comphy_set_mode_sgmii()
500 	err = mvebu_comphy_ethernet_init_reset(lane);  in mvebu_comphy_set_mode_sgmii()
504 	val = readl(priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id));  in mvebu_comphy_set_mode_sgmii()
507 	writel(val, priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id));  in mvebu_comphy_set_mode_sgmii()
509 	val = readl(priv->base + MVEBU_COMPHY_DTL_CTRL(lane->id));  in mvebu_comphy_set_mode_sgmii()
511 	writel(val, priv->base + MVEBU_COMPHY_DTL_CTRL(lane->id));  in mvebu_comphy_set_mode_sgmii()
513 	regmap_read(priv->regmap, MVEBU_COMPHY_CONF1(lane->id), &val);  in mvebu_comphy_set_mode_sgmii()
516 	regmap_write(priv->regmap, MVEBU_COMPHY_CONF1(lane->id), val);  in mvebu_comphy_set_mode_sgmii()
518 	val = readl(priv->base + MVEBU_COMPHY_GEN1_S0(lane->id));  in mvebu_comphy_set_mode_sgmii()
521 	writel(val, priv->base + MVEBU_COMPHY_GEN1_S0(lane->id));  in mvebu_comphy_set_mode_sgmii()
523 	return mvebu_comphy_init_plls(lane);  in mvebu_comphy_set_mode_sgmii()
528 	struct mvebu_comphy_lane *lane = phy_get_drvdata(phy);  in mvebu_comphy_set_mode_rxaui()  local
529 	struct mvebu_comphy_priv *priv = lane->priv;  in mvebu_comphy_set_mode_rxaui()
533 	err = mvebu_comphy_ethernet_init_reset(lane);  in mvebu_comphy_set_mode_rxaui()
537 	val = readl(priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id));  in mvebu_comphy_set_mode_rxaui()
540 	writel(val, priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id));  in mvebu_comphy_set_mode_rxaui()
542 	val = readl(priv->base + MVEBU_COMPHY_DTL_CTRL(lane->id));  in mvebu_comphy_set_mode_rxaui()
544 	writel(val, priv->base + MVEBU_COMPHY_DTL_CTRL(lane->id));  in mvebu_comphy_set_mode_rxaui()
546 	val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG2(lane->id));  in mvebu_comphy_set_mode_rxaui()
548 	writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG2(lane->id));  in mvebu_comphy_set_mode_rxaui()
550 	val = readl(priv->base + MVEBU_COMPHY_DFE_RES(lane->id));  in mvebu_comphy_set_mode_rxaui()
552 	writel(val, priv->base + MVEBU_COMPHY_DFE_RES(lane->id));  in mvebu_comphy_set_mode_rxaui()
554 	val = readl(priv->base + MVEBU_COMPHY_GEN1_S0(lane->id));  in mvebu_comphy_set_mode_rxaui()
557 	writel(val, priv->base + MVEBU_COMPHY_GEN1_S0(lane->id));  in mvebu_comphy_set_mode_rxaui()
559 	val = readl(priv->base + MVEBU_COMPHY_GEN1_S1(lane->id));  in mvebu_comphy_set_mode_rxaui()
565 	writel(val, priv->base + MVEBU_COMPHY_GEN1_S1(lane->id));  in mvebu_comphy_set_mode_rxaui()
567 	val = readl(priv->base + MVEBU_COMPHY_COEF(lane->id));  in mvebu_comphy_set_mode_rxaui()
569 	writel(val, priv->base + MVEBU_COMPHY_COEF(lane->id));  in mvebu_comphy_set_mode_rxaui()
571 	val = readl(priv->base + MVEBU_COMPHY_GEN1_S4(lane->id));  in mvebu_comphy_set_mode_rxaui()
574 	writel(val, priv->base + MVEBU_COMPHY_GEN1_S4(lane->id));  in mvebu_comphy_set_mode_rxaui()
576 	return mvebu_comphy_init_plls(lane);  in mvebu_comphy_set_mode_rxaui()
581 	struct mvebu_comphy_lane *lane = phy_get_drvdata(phy);  in mvebu_comphy_set_mode_10gbaser()  local
582 	struct mvebu_comphy_priv *priv = lane->priv;  in mvebu_comphy_set_mode_10gbaser()
586 	err = mvebu_comphy_ethernet_init_reset(lane);  in mvebu_comphy_set_mode_10gbaser()
590 	val = readl(priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id));  in mvebu_comphy_set_mode_10gbaser()
593 	writel(val, priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id));  in mvebu_comphy_set_mode_10gbaser()
595 	val = readl(priv->base + MVEBU_COMPHY_DTL_CTRL(lane->id));  in mvebu_comphy_set_mode_10gbaser()
597 	writel(val, priv->base + MVEBU_COMPHY_DTL_CTRL(lane->id));  in mvebu_comphy_set_mode_10gbaser()
600 	val = readl(priv->base + MVEBU_COMPHY_SPEED_DIV(lane->id));  in mvebu_comphy_set_mode_10gbaser()
602 	writel(val, priv->base + MVEBU_COMPHY_SPEED_DIV(lane->id));  in mvebu_comphy_set_mode_10gbaser()
604 	val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG2(lane->id));  in mvebu_comphy_set_mode_10gbaser()
606 	writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG2(lane->id));  in mvebu_comphy_set_mode_10gbaser()
609 	val = readl(priv->base + MVEBU_COMPHY_DFE_RES(lane->id));  in mvebu_comphy_set_mode_10gbaser()
611 	writel(val, priv->base + MVEBU_COMPHY_DFE_RES(lane->id));  in mvebu_comphy_set_mode_10gbaser()
613 	val = readl(priv->base + MVEBU_COMPHY_GEN1_S0(lane->id));  in mvebu_comphy_set_mode_10gbaser()
618 	writel(val, priv->base + MVEBU_COMPHY_GEN1_S0(lane->id));  in mvebu_comphy_set_mode_10gbaser()
620 	val = readl(priv->base + MVEBU_COMPHY_GEN1_S2(lane->id));  in mvebu_comphy_set_mode_10gbaser()
623 	writel(val, priv->base + MVEBU_COMPHY_GEN1_S2(lane->id));  in mvebu_comphy_set_mode_10gbaser()
625 	val = readl(priv->base + MVEBU_COMPHY_TX_SLEW_RATE(lane->id));  in mvebu_comphy_set_mode_10gbaser()
628 	writel(val, priv->base + MVEBU_COMPHY_TX_SLEW_RATE(lane->id));  in mvebu_comphy_set_mode_10gbaser()
631 	val = readl(priv->base + MVEBU_COMPHY_IMP_CAL(lane->id));  in mvebu_comphy_set_mode_10gbaser()
635 	writel(val, priv->base + MVEBU_COMPHY_IMP_CAL(lane->id));  in mvebu_comphy_set_mode_10gbaser()
637 	val = readl(priv->base + MVEBU_COMPHY_GEN1_S5(lane->id));  in mvebu_comphy_set_mode_10gbaser()
639 	writel(val, priv->base + MVEBU_COMPHY_GEN1_S5(lane->id));  in mvebu_comphy_set_mode_10gbaser()
641 	val = readl(priv->base + MVEBU_COMPHY_GEN1_S1(lane->id));  in mvebu_comphy_set_mode_10gbaser()
651 	writel(val, priv->base + MVEBU_COMPHY_GEN1_S1(lane->id));  in mvebu_comphy_set_mode_10gbaser()
653 	val = readl(priv->base + MVEBU_COMPHY_COEF(lane->id));  in mvebu_comphy_set_mode_10gbaser()
655 	writel(val, priv->base + MVEBU_COMPHY_COEF(lane->id));  in mvebu_comphy_set_mode_10gbaser()
657 	val = readl(priv->base + MVEBU_COMPHY_GEN1_S4(lane->id));  in mvebu_comphy_set_mode_10gbaser()
660 	writel(val, priv->base + MVEBU_COMPHY_GEN1_S4(lane->id));  in mvebu_comphy_set_mode_10gbaser()
662 	val = readl(priv->base + MVEBU_COMPHY_GEN1_S3(lane->id));  in mvebu_comphy_set_mode_10gbaser()
664 	writel(val, priv->base + MVEBU_COMPHY_GEN1_S3(lane->id));  in mvebu_comphy_set_mode_10gbaser()
667 	val = readl(priv->base + MVEBU_COMPHY_TRAINING5(lane->id));  in mvebu_comphy_set_mode_10gbaser()
670 	writel(val, priv->base + MVEBU_COMPHY_TRAINING5(lane->id));  in mvebu_comphy_set_mode_10gbaser()
673 	val = readl(priv->base + MVEBU_COMPHY_TRAINING0(lane->id));  in mvebu_comphy_set_mode_10gbaser()
675 	writel(val, priv->base + MVEBU_COMPHY_TRAINING0(lane->id));  in mvebu_comphy_set_mode_10gbaser()
677 	val = readl(priv->base + MVEBU_COMPHY_TX_PRESET(lane->id));  in mvebu_comphy_set_mode_10gbaser()
680 	writel(val, priv->base + MVEBU_COMPHY_TX_PRESET(lane->id));  in mvebu_comphy_set_mode_10gbaser()
682 	val = readl(priv->base + MVEBU_COMPHY_FRAME_DETECT3(lane->id));  in mvebu_comphy_set_mode_10gbaser()
684 	writel(val, priv->base + MVEBU_COMPHY_FRAME_DETECT3(lane->id));  in mvebu_comphy_set_mode_10gbaser()
686 	val = readl(priv->base + MVEBU_COMPHY_TX_TRAIN_PRESET(lane->id));  in mvebu_comphy_set_mode_10gbaser()
689 	writel(val, priv->base + MVEBU_COMPHY_TX_TRAIN_PRESET(lane->id));  in mvebu_comphy_set_mode_10gbaser()
691 	val = readl(priv->base + MVEBU_COMPHY_FRAME_DETECT0(lane->id));  in mvebu_comphy_set_mode_10gbaser()
694 	writel(val, priv->base + MVEBU_COMPHY_FRAME_DETECT0(lane->id));  in mvebu_comphy_set_mode_10gbaser()
696 	val = readl(priv->base + MVEBU_COMPHY_DME(lane->id));  in mvebu_comphy_set_mode_10gbaser()
698 	writel(val, priv->base + MVEBU_COMPHY_DME(lane->id));  in mvebu_comphy_set_mode_10gbaser()
700 	val = readl(priv->base + MVEBU_COMPHY_VDD_CAL0(lane->id));  in mvebu_comphy_set_mode_10gbaser()
702 	writel(val, priv->base + MVEBU_COMPHY_VDD_CAL0(lane->id));  in mvebu_comphy_set_mode_10gbaser()
704 	val = readl(priv->base + MVEBU_SP_CALIB(lane->id));  in mvebu_comphy_set_mode_10gbaser()
708 	writel(val, priv->base + MVEBU_SP_CALIB(lane->id));  in mvebu_comphy_set_mode_10gbaser()
710 	writel(val, priv->base + MVEBU_SP_CALIB(lane->id));  in mvebu_comphy_set_mode_10gbaser()
713 	val = readl(priv->base + MVEBU_COMPHY_EXT_SELV(lane->id));  in mvebu_comphy_set_mode_10gbaser()
716 	writel(val, priv->base + MVEBU_COMPHY_EXT_SELV(lane->id));  in mvebu_comphy_set_mode_10gbaser()
718 	return mvebu_comphy_init_plls(lane);  in mvebu_comphy_set_mode_10gbaser()
723 	struct mvebu_comphy_lane *lane = phy_get_drvdata(phy);  in mvebu_comphy_power_on_legacy()  local
724 	struct mvebu_comphy_priv *priv = lane->priv;  in mvebu_comphy_power_on_legacy()
728 	mux = mvebu_comphy_get_mux(lane->id, lane->port,  in mvebu_comphy_power_on_legacy()
729 				   lane->mode, lane->submode);  in mvebu_comphy_power_on_legacy()
734 	val &= ~(0xf << MVEBU_COMPHY_PIPE_SELECTOR_PIPE(lane->id));  in mvebu_comphy_power_on_legacy()
738 	val &= ~(0xf << MVEBU_COMPHY_SELECTOR_PHY(lane->id));  in mvebu_comphy_power_on_legacy()
739 	val |= mux << MVEBU_COMPHY_SELECTOR_PHY(lane->id);  in mvebu_comphy_power_on_legacy()
742 	switch (lane->submode) {  in mvebu_comphy_power_on_legacy()
758 	val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));  in mvebu_comphy_power_on_legacy()
760 	writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));  in mvebu_comphy_power_on_legacy()
767 	struct mvebu_comphy_lane *lane = phy_get_drvdata(phy);  in mvebu_comphy_power_on()  local
768 	struct mvebu_comphy_priv *priv = lane->priv;  in mvebu_comphy_power_on()
773 	fw_mode = mvebu_comphy_get_fw_mode(lane->id, lane->port,  in mvebu_comphy_power_on()
774 					   lane->mode, lane->submode);  in mvebu_comphy_power_on()
779 	switch (lane->mode) {  in mvebu_comphy_power_on()
781 		switch (lane->submode) {  in mvebu_comphy_power_on()
783 			dev_dbg(priv->dev, "set lane %d to RXAUI mode\n",  in mvebu_comphy_power_on()
784 				lane->id);  in mvebu_comphy_power_on()
788 			dev_dbg(priv->dev, "set lane %d to 1000BASE-X mode\n",  in mvebu_comphy_power_on()
789 				lane->id);  in mvebu_comphy_power_on()
793 			dev_dbg(priv->dev, "set lane %d to 2500BASE-X mode\n",  in mvebu_comphy_power_on()
794 				lane->id);  in mvebu_comphy_power_on()
798 			dev_dbg(priv->dev, "set lane %d to 5GBASE-R mode\n",  in mvebu_comphy_power_on()
799 				lane->id);  in mvebu_comphy_power_on()
803 			dev_dbg(priv->dev, "set lane %d to 10GBASE-R mode\n",  in mvebu_comphy_power_on()
804 				lane->id);  in mvebu_comphy_power_on()
809 				lane->submode);  in mvebu_comphy_power_on()
812 		fw_param = COMPHY_FW_PARAM_ETH(fw_mode, lane->port, fw_speed);  in mvebu_comphy_power_on()
816 		dev_dbg(priv->dev, "set lane %d to USB3 mode\n", lane->id);  in mvebu_comphy_power_on()
817 		fw_param = COMPHY_FW_PARAM(fw_mode, lane->port);  in mvebu_comphy_power_on()
820 		dev_dbg(priv->dev, "set lane %d to SATA mode\n", lane->id);  in mvebu_comphy_power_on()
821 		fw_param = COMPHY_FW_PARAM(fw_mode, lane->port);  in mvebu_comphy_power_on()
824 		dev_dbg(priv->dev, "set lane %d to PCIe mode (x%d)\n", lane->id,  in mvebu_comphy_power_on()
825 			lane->submode);  in mvebu_comphy_power_on()
826 		fw_param = COMPHY_FW_PARAM_PCIE(fw_mode, lane->port,  in mvebu_comphy_power_on()
827 						lane->submode);  in mvebu_comphy_power_on()
830 		dev_err(priv->dev, "unsupported PHY mode (%d)\n", lane->mode);  in mvebu_comphy_power_on()
834 	ret = mvebu_comphy_smc(COMPHY_SIP_POWER_ON, priv->cp_phys, lane->id,  in mvebu_comphy_power_on()
845 		 lane->id, lane->mode, ret);  in mvebu_comphy_power_on()
855 	struct mvebu_comphy_lane *lane = phy_get_drvdata(phy);  in mvebu_comphy_set_mode()  local
860 	if (mvebu_comphy_get_fw_mode(lane->id, lane->port, mode, submode) < 0)  in mvebu_comphy_set_mode()
863 	lane->mode = mode;  in mvebu_comphy_set_mode()
864 	lane->submode = submode;  in mvebu_comphy_set_mode()
867 	if (mode == PHY_MODE_PCIE && !lane->submode)  in mvebu_comphy_set_mode()
868 		lane->submode = 1;  in mvebu_comphy_set_mode()
875 	struct mvebu_comphy_lane *lane = phy_get_drvdata(phy);  in mvebu_comphy_power_off_legacy()  local
876 	struct mvebu_comphy_priv *priv = lane->priv;  in mvebu_comphy_power_off_legacy()
879 	val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));  in mvebu_comphy_power_off_legacy()
883 	writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));  in mvebu_comphy_power_off_legacy()
886 	val &= ~(0xf << MVEBU_COMPHY_SELECTOR_PHY(lane->id));  in mvebu_comphy_power_off_legacy()
890 	val &= ~(0xf << MVEBU_COMPHY_PIPE_SELECTOR_PIPE(lane->id));  in mvebu_comphy_power_off_legacy()
898 	struct mvebu_comphy_lane *lane = phy_get_drvdata(phy);  in mvebu_comphy_power_off()  local
899 	struct mvebu_comphy_priv *priv = lane->priv;  in mvebu_comphy_power_off()
903 			       lane->id, 0);  in mvebu_comphy_power_off()
921 	struct mvebu_comphy_lane *lane;  in mvebu_comphy_xlate()  local
931 	lane = phy_get_drvdata(phy);  in mvebu_comphy_xlate()
932 	lane->port = args->args[0];  in mvebu_comphy_xlate()
1037 		struct mvebu_comphy_lane *lane;  in mvebu_comphy_probe()  local
1053 		lane = devm_kzalloc(&pdev->dev, sizeof(*lane), GFP_KERNEL);  in mvebu_comphy_probe()
1054 		if (!lane) {  in mvebu_comphy_probe()
1067 		lane->priv = priv;  in mvebu_comphy_probe()
1068 		lane->mode = PHY_MODE_INVALID;  in mvebu_comphy_probe()
1069 		lane->submode = PHY_INTERFACE_MODE_NA;  in mvebu_comphy_probe()
1070 		lane->id = val;  in mvebu_comphy_probe()
1071 		lane->port = -1;  in mvebu_comphy_probe()
1072 		phy_set_drvdata(phy, lane);  in mvebu_comphy_probe()