154 static inline void update_reg(struct thunderbay_emmc_phy *tbh_phy, u32 offset,  in update_reg()  function
179 		update_reg(tbh_phy, PHY_CFG_0, DLL_EN_MASK, DLL_EN_SHIFT, 0x0);  in thunderbay_emmc_phy_power()
236 		update_reg(tbh_phy, PHY_CFG_0, PWR_DOWN_MASK,  in thunderbay_emmc_phy_power()
257 		update_reg(tbh_phy, PHY_CFG_2, SEL_FREQ_MASK, SEL_FREQ_SHIFT, freqsel);  in thunderbay_emmc_phy_power()
260 		update_reg(tbh_phy, PHY_CFG_0, DLL_EN_MASK, DLL_EN_SHIFT, 0x1);  in thunderbay_emmc_phy_power()
314 	update_reg(tbh_phy, CTRL_CFG_0,  in thunderbay_emmc_phy_power_on()
316 	update_reg(tbh_phy, CTRL_CFG_0,  in thunderbay_emmc_phy_power_on()
318 	update_reg(tbh_phy, CTRL_CFG_1,  in thunderbay_emmc_phy_power_on()
320 	update_reg(tbh_phy, CTRL_CFG_1,  in thunderbay_emmc_phy_power_on()
322 	update_reg(tbh_phy, CTRL_CFG_1,  in thunderbay_emmc_phy_power_on()
324 	update_reg(tbh_phy, CTRL_CFG_1,  in thunderbay_emmc_phy_power_on()
326 	update_reg(tbh_phy, CTRL_CFG_1,  in thunderbay_emmc_phy_power_on()
331 		update_reg(tbh_phy, PHY_CFG_0, SEL_DLY_TXCLK_MASK, SEL_DLY_TXCLK_SHIFT, 0x1);  in thunderbay_emmc_phy_power_on()
332 		update_reg(tbh_phy, PHY_CFG_0, SEL_DLY_RXCLK_MASK, SEL_DLY_RXCLK_SHIFT, 0x1);  in thunderbay_emmc_phy_power_on()
333 		update_reg(tbh_phy, PHY_CFG_0, ITAP_DLY_ENA_MASK, ITAP_DLY_ENA_SHIFT, 0x0);  in thunderbay_emmc_phy_power_on()
334 		update_reg(tbh_phy, PHY_CFG_0, ITAP_DLY_SEL_MASK, ITAP_DLY_SEL_SHIFT, 0x0);  in thunderbay_emmc_phy_power_on()
335 		update_reg(tbh_phy, PHY_CFG_0, OTAP_DLY_ENA_MASK, OTAP_DLY_ENA_SHIFT, 0x0);  in thunderbay_emmc_phy_power_on()
336 		update_reg(tbh_phy, PHY_CFG_0, OTAP_DLY_SEL_MASK, OTAP_DLY_SEL_SHIFT, 0);  in thunderbay_emmc_phy_power_on()
337 		update_reg(tbh_phy, PHY_CFG_0, DLL_TRIM_ICP_MASK, DLL_TRIM_ICP_SHIFT, 0);  in thunderbay_emmc_phy_power_on()
338 		update_reg(tbh_phy, PHY_CFG_0, DR_TY_MASK, DR_TY_SHIFT, 0x1);  in thunderbay_emmc_phy_power_on()
345 			update_reg(tbh_phy, PHY_CFG_0, SEL_DLY_TXCLK_MASK,  in thunderbay_emmc_phy_power_on()
347 			update_reg(tbh_phy, PHY_CFG_0, SEL_DLY_RXCLK_MASK,  in thunderbay_emmc_phy_power_on()
349 			update_reg(tbh_phy, PHY_CFG_0, ITAP_DLY_ENA_MASK,  in thunderbay_emmc_phy_power_on()
351 			update_reg(tbh_phy, PHY_CFG_0, ITAP_DLY_SEL_MASK,  in thunderbay_emmc_phy_power_on()
353 			update_reg(tbh_phy, PHY_CFG_0, OTAP_DLY_ENA_MASK,  in thunderbay_emmc_phy_power_on()
355 			update_reg(tbh_phy, PHY_CFG_0, OTAP_DLY_SEL_MASK,  in thunderbay_emmc_phy_power_on()
357 			update_reg(tbh_phy, PHY_CFG_0, DLL_TRIM_ICP_MASK,  in thunderbay_emmc_phy_power_on()
359 			update_reg(tbh_phy, PHY_CFG_0, DR_TY_MASK,  in thunderbay_emmc_phy_power_on()
362 			update_reg(tbh_phy, PHY_CFG_2, SEL_STRB_MASK,  in thunderbay_emmc_phy_power_on()
368 			update_reg(tbh_phy, PHY_CFG_0, SEL_DLY_TXCLK_MASK,  in thunderbay_emmc_phy_power_on()
370 			update_reg(tbh_phy, PHY_CFG_0, SEL_DLY_RXCLK_MASK,  in thunderbay_emmc_phy_power_on()
372 			update_reg(tbh_phy, PHY_CFG_0, ITAP_DLY_ENA_MASK,  in thunderbay_emmc_phy_power_on()
374 			update_reg(tbh_phy, PHY_CFG_0, ITAP_DLY_SEL_MASK,  in thunderbay_emmc_phy_power_on()
376 			update_reg(tbh_phy, PHY_CFG_0, OTAP_DLY_ENA_MASK,  in thunderbay_emmc_phy_power_on()
378 			update_reg(tbh_phy, PHY_CFG_0, OTAP_DLY_SEL_MASK,  in thunderbay_emmc_phy_power_on()
380 			update_reg(tbh_phy, PHY_CFG_0, DLL_TRIM_ICP_MASK,  in thunderbay_emmc_phy_power_on()
382 			update_reg(tbh_phy, PHY_CFG_0,  in thunderbay_emmc_phy_power_on()
387 			update_reg(tbh_phy, PHY_CFG_0, SEL_DLY_TXCLK_MASK,  in thunderbay_emmc_phy_power_on()
389 			update_reg(tbh_phy, PHY_CFG_0, SEL_DLY_RXCLK_MASK,  in thunderbay_emmc_phy_power_on()
391 			update_reg(tbh_phy, PHY_CFG_0, ITAP_DLY_ENA_MASK,  in thunderbay_emmc_phy_power_on()
393 			update_reg(tbh_phy, PHY_CFG_0, ITAP_DLY_SEL_MASK,  in thunderbay_emmc_phy_power_on()
395 			update_reg(tbh_phy, PHY_CFG_0, OTAP_DLY_ENA_MASK,  in thunderbay_emmc_phy_power_on()
397 			update_reg(tbh_phy, PHY_CFG_0, OTAP_DLY_SEL_MASK,  in thunderbay_emmc_phy_power_on()
399 			update_reg(tbh_phy, PHY_CFG_0, DLL_TRIM_ICP_MASK,  in thunderbay_emmc_phy_power_on()
401 			update_reg(tbh_phy, PHY_CFG_0, DR_TY_MASK, DR_TY_SHIFT, 0x1);  in thunderbay_emmc_phy_power_on()
405 			update_reg(tbh_phy, PHY_CFG_0, SEL_DLY_TXCLK_MASK,  in thunderbay_emmc_phy_power_on()
407 			update_reg(tbh_phy, PHY_CFG_0, SEL_DLY_RXCLK_MASK,  in thunderbay_emmc_phy_power_on()
409 			update_reg(tbh_phy, PHY_CFG_0, ITAP_DLY_ENA_MASK,  in thunderbay_emmc_phy_power_on()
411 			update_reg(tbh_phy, PHY_CFG_0, ITAP_DLY_SEL_MASK,  in thunderbay_emmc_phy_power_on()
413 			update_reg(tbh_phy, PHY_CFG_0, OTAP_DLY_ENA_MASK,  in thunderbay_emmc_phy_power_on()
415 			update_reg(tbh_phy, PHY_CFG_0, OTAP_DLY_SEL_MASK,  in thunderbay_emmc_phy_power_on()
417 			update_reg(tbh_phy, PHY_CFG_0, DLL_TRIM_ICP_MASK,  in thunderbay_emmc_phy_power_on()
419 			update_reg(tbh_phy, PHY_CFG_0, DR_TY_MASK,  in thunderbay_emmc_phy_power_on()
427 	update_reg(tbh_phy, PHY_CFG_0, RETRIM_EN_MASK, RETRIM_EN_SHIFT, 0x1);  in thunderbay_emmc_phy_power_on()
428 	update_reg(tbh_phy, PHY_CFG_0, RETRIM_MASK, RETRIM_SHIFT, 0x0);  in thunderbay_emmc_phy_power_on()