1 // SPDX-License-Identifier: GPL-2.0+
11 #include <linux/mfd/syscon.h>
12 #include <linux/mfd/syscon/imx7-iomuxc-gpr.h>
19 #include <dt-bindings/phy/phy-imx8-pcie.h>
68 	reset_control_assert(imx8_phy->reset);  in imx8_pcie_phy_power_on()
70 	pad_mode = imx8_phy->refclk_pad_mode;  in imx8_pcie_phy_power_on()
72 	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,  in imx8_pcie_phy_power_on()
74 			   imx8_phy->clkreq_unused ?  in imx8_pcie_phy_power_on()
76 	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,  in imx8_pcie_phy_power_on()
79 	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,  in imx8_pcie_phy_power_on()
81 	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,  in imx8_pcie_phy_power_on()
84 	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,  in imx8_pcie_phy_power_on()
92 	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,  in imx8_pcie_phy_power_on()
100 		val = readl(imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG061);  in imx8_pcie_phy_power_on()
102 		       imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG061);  in imx8_pcie_phy_power_on()
106 		       imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG061);  in imx8_pcie_phy_power_on()
113 		       imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG062);  in imx8_pcie_phy_power_on()
115 		       imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG063);  in imx8_pcie_phy_power_on()
118 		       imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG064);  in imx8_pcie_phy_power_on()
120 		       imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG065);  in imx8_pcie_phy_power_on()
123 	/* Tune PHY de-emphasis setting to pass PCIe compliance. */  in imx8_pcie_phy_power_on()
124 	if (imx8_phy->tx_deemph_gen1)  in imx8_pcie_phy_power_on()
125 		writel(imx8_phy->tx_deemph_gen1,  in imx8_pcie_phy_power_on()
126 		       imx8_phy->base + PCIE_PHY_TRSV_REG5);  in imx8_pcie_phy_power_on()
127 	if (imx8_phy->tx_deemph_gen2)  in imx8_pcie_phy_power_on()
128 		writel(imx8_phy->tx_deemph_gen2,  in imx8_pcie_phy_power_on()
129 		       imx8_phy->base + PCIE_PHY_TRSV_REG6);  in imx8_pcie_phy_power_on()
131 	reset_control_deassert(imx8_phy->reset);  in imx8_pcie_phy_power_on()
134 	ret = readl_poll_timeout(imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG75,  in imx8_pcie_phy_power_on()
144 	return clk_prepare_enable(imx8_phy->clk);  in imx8_pcie_phy_init()
151 	clk_disable_unprepare(imx8_phy->clk);  in imx8_pcie_phy_exit()
166 	struct device *dev = &pdev->dev;  in imx8_pcie_phy_probe()
167 	struct device_node *np = dev->of_node;  in imx8_pcie_phy_probe()
173 		return -ENOMEM;  in imx8_pcie_phy_probe()
175 	/* get PHY refclk pad mode */  in imx8_pcie_phy_probe()
176 	of_property_read_u32(np, "fsl,refclk-pad-mode",  in imx8_pcie_phy_probe()
177 			     &imx8_phy->refclk_pad_mode);  in imx8_pcie_phy_probe()
179 	if (of_property_read_u32(np, "fsl,tx-deemph-gen1",  in imx8_pcie_phy_probe()
180 				 &imx8_phy->tx_deemph_gen1))  in imx8_pcie_phy_probe()
181 		imx8_phy->tx_deemph_gen1 = 0;  in imx8_pcie_phy_probe()
183 	if (of_property_read_u32(np, "fsl,tx-deemph-gen2",  in imx8_pcie_phy_probe()
184 				 &imx8_phy->tx_deemph_gen2))  in imx8_pcie_phy_probe()
185 		imx8_phy->tx_deemph_gen2 = 0;  in imx8_pcie_phy_probe()
187 	if (of_property_read_bool(np, "fsl,clkreq-unsupported"))  in imx8_pcie_phy_probe()
188 		imx8_phy->clkreq_unused = true;  in imx8_pcie_phy_probe()
190 		imx8_phy->clkreq_unused = false;  in imx8_pcie_phy_probe()
192 	imx8_phy->clk = devm_clk_get(dev, "ref");  in imx8_pcie_phy_probe()
193 	if (IS_ERR(imx8_phy->clk)) {  in imx8_pcie_phy_probe()
194 		dev_err(dev, "failed to get imx pcie phy clock\n");  in imx8_pcie_phy_probe()
195 		return PTR_ERR(imx8_phy->clk);  in imx8_pcie_phy_probe()
199 	imx8_phy->iomuxc_gpr =  in imx8_pcie_phy_probe()
200 		 syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");  in imx8_pcie_phy_probe()
201 	if (IS_ERR(imx8_phy->iomuxc_gpr)) {  in imx8_pcie_phy_probe()
203 		return PTR_ERR(imx8_phy->iomuxc_gpr);  in imx8_pcie_phy_probe()
206 	imx8_phy->reset = devm_reset_control_get_exclusive(dev, "pciephy");  in imx8_pcie_phy_probe()
207 	if (IS_ERR(imx8_phy->reset)) {  in imx8_pcie_phy_probe()
209 		return PTR_ERR(imx8_phy->reset);  in imx8_pcie_phy_probe()
213 	imx8_phy->base = devm_ioremap_resource(dev, res);  in imx8_pcie_phy_probe()
214 	if (IS_ERR(imx8_phy->base))  in imx8_pcie_phy_probe()
215 		return PTR_ERR(imx8_phy->base);  in imx8_pcie_phy_probe()
217 	imx8_phy->phy = devm_phy_create(dev, NULL, &imx8_pcie_phy_ops);  in imx8_pcie_phy_probe()
218 	if (IS_ERR(imx8_phy->phy))  in imx8_pcie_phy_probe()
219 		return PTR_ERR(imx8_phy->phy);  in imx8_pcie_phy_probe()
221 	phy_set_drvdata(imx8_phy->phy, imx8_phy);  in imx8_pcie_phy_probe()
229 	{.compatible = "fsl,imx8mm-pcie-phy",},
237 		.name	= "imx8-pcie-phy",
243 MODULE_DESCRIPTION("FSL IMX8 PCIE PHY driver");