Lines Matching +full:0 +full:x83
19 #define SATA_PCB_BANK_OFFSET 0x23c
25 #define SATA_PCB_REG_28NM_SPACE_SIZE 0x1000
30 #define SATA_PCB_REG_40NM_SPACE_SIZE 0x10
33 #define SATA_PHY_CTRL_REG_28NM_SPACE_SIZE 0x8
46 RXAEQ_MODE_OFF = 0,
81 BLOCK0_REG_BANK = 0x000,
82 BLOCK0_XGXSSTATUS = 0x81,
84 BLOCK0_SPARE = 0x8d,
85 BLOCK0_SPARE_OOB_CLK_SEL_MASK = 0x3,
86 BLOCK0_SPARE_OOB_CLK_SEL_REFBY2 = 0x1,
88 BLOCK1_REG_BANK = 0x10,
89 BLOCK1_TEST_TX = 0x83,
92 PLL_REG_BANK_0 = 0x050,
93 PLL_REG_BANK_0_PLLCONTROL_0 = 0x81,
97 PLL_CAP_CHARGE_TIME = 0x83,
98 PLL_VCO_CAL_THRESH = 0x84,
99 PLL_CAP_CONTROL = 0x85,
100 PLL_FREQ_DET_TIME = 0x86,
101 PLL_ACTRL2 = 0x8b,
102 PLL_ACTRL2_SELDIV_MASK = 0x1f,
104 PLL_ACTRL6 = 0x86,
106 PLL1_REG_BANK = 0x060,
107 PLL1_ACTRL2 = 0x82,
108 PLL1_ACTRL3 = 0x83,
109 PLL1_ACTRL4 = 0x84,
110 PLL1_ACTRL5 = 0x85,
111 PLL1_ACTRL6 = 0x86,
112 PLL1_ACTRL7 = 0x87,
113 PLL1_ACTRL8 = 0x88,
115 TX_REG_BANK = 0x070,
116 TX_ACTRL0 = 0x80,
118 TX_ACTRL5 = 0x85,
121 AEQRX_REG_BANK_0 = 0xd0,
122 AEQ_CONTROL1 = 0x81,
125 AEQ_FRC_EQ = 0x83,
126 AEQ_FRC_EQ_FORCE = BIT(0),
129 AEQRX_REG_BANK_1 = 0xe0,
130 AEQRX_SLCAL0_CTRL0 = 0x82,
131 AEQRX_SLCAL1_CTRL0 = 0x86,
133 OOB_REG_BANK = 0x150,
134 OOB1_REG_BANK = 0x160,
135 OOB_CTRL1 = 0x80,
136 OOB_CTRL1_BURST_MAX_MASK = 0xf,
138 OOB_CTRL1_BURST_MIN_MASK = 0xf,
140 OOB_CTRL1_WAKE_IDLE_MAX_MASK = 0xf,
142 OOB_CTRL1_WAKE_IDLE_MIN_MASK = 0xf,
143 OOB_CTRL1_WAKE_IDLE_MIN_SHIFT = 0,
144 OOB_CTRL2 = 0x81,
147 OOB_CTRL2_RESET_IDLE_MAX_MASK = 0x3f,
149 OOB_CTRL2_BURST_CNT_MASK = 0x3,
151 OOB_CTRL2_RESET_IDLE_MIN_MASK = 0x3f,
152 OOB_CTRL2_RESET_IDLE_MIN_SHIFT = 0,
154 TXPMD_REG_BANK = 0x1a0,
155 TXPMD_CONTROL1 = 0x81,
156 TXPMD_CONTROL1_TX_SSC_EN_FRC = BIT(0),
158 TXPMD_TX_FREQ_CTRL_CONTROL1 = 0x82,
159 TXPMD_TX_FREQ_CTRL_CONTROL2 = 0x83,
160 TXPMD_TX_FREQ_CTRL_CONTROL2_FMIN_MASK = 0x3ff,
161 TXPMD_TX_FREQ_CTRL_CONTROL3 = 0x84,
162 TXPMD_TX_FREQ_CTRL_CONTROL3_FMAX_MASK = 0x3ff,
164 RXPMD_REG_BANK = 0x1c0,
165 RXPMD_RX_CDR_CONTROL1 = 0x81,
166 RXPMD_RX_PPM_VAL_MASK = 0x1ff,
169 RXPMD_RX_CDR_CDR_PROP_BW = 0x82,
170 RXPMD_G_CDR_PROP_BW_MASK = 0x7,
171 RXPMD_G1_CDR_PROP_BW_SHIFT = 0,
174 RXPMD_RX_CDR_CDR_ACQ_INTEG_BW = 0x83,
175 RXPMD_G_CDR_ACQ_INT_BW_MASK = 0x7,
176 RXPMD_G1_CDR_ACQ_INT_BW_SHIFT = 0,
179 RXPMD_RX_CDR_CDR_LOCK_INTEG_BW = 0x84,
180 RXPMD_G_CDR_LOCK_INT_BW_MASK = 0x7,
181 RXPMD_G1_CDR_LOCK_INT_BW_SHIFT = 0,
184 RXPMD_RX_FREQ_MON_CONTROL1 = 0x87,
186 RXPMD_MON_MARGIN_VAL_MASK = 0xff,
190 PHY_CTRL_1 = 0x0,
191 PHY_CTRL_1_RESET = BIT(0),
197 u32 size = 0; in brcm_sata_ctrl_base()
244 #define STB_FMIN_VAL_DEFAULT 0x3df
245 #define STB_FMAX_VAL_DEFAULT 0x3df
246 #define STB_FMAX_VAL_SSC 0x83
275 #define AEQ_FRC_EQ_VAL_MASK 0x3f
279 u32 tmp = 0, reg = 0; in brcm_stb_sata_rxaeq_init()
283 return 0; in brcm_stb_sata_rxaeq_init()
302 return 0; in brcm_stb_sata_rxaeq_init()
317 brcm_sata_phy_wr(port, PLL1_REG_BANK, PLL1_ACTRL6, 0, 0x141); in brcm_stb_sata_16nm_ssc_init()
320 brcm_sata_phy_wr(port, PLL1_REG_BANK, PLL1_ACTRL8, 0, 0xc006); in brcm_stb_sata_16nm_ssc_init()
331 value = 0x52; in brcm_stb_sata_16nm_ssc_init()
333 value = 0; in brcm_stb_sata_16nm_ssc_init()
361 value = 0; in brcm_stb_sata_16nm_ssc_init()
374 value = 0; in brcm_stb_sata_16nm_ssc_init()
381 value = 0x51; in brcm_stb_sata_16nm_ssc_init()
383 value = 0; in brcm_stb_sata_16nm_ssc_init()
399 value = 0; in brcm_stb_sata_16nm_ssc_init()
412 port->ssc_en ? TX_ACTRL5_SSC_EN : 0); in brcm_stb_sata_16nm_ssc_init()
414 return 0; in brcm_stb_sata_16nm_ssc_init()
423 #define NS2_PLL1_ACTRL2_MAGIC 0x1df8
424 #define NS2_PLL1_ACTRL3_MAGIC 0x2b00
425 #define NS2_PLL1_ACTRL4_MAGIC 0x8824
435 val = 0x0; in brcm_ns2_sata_init()
436 val |= (0xc << OOB_CTRL1_BURST_MAX_SHIFT); in brcm_ns2_sata_init()
437 val |= (0x4 << OOB_CTRL1_BURST_MIN_SHIFT); in brcm_ns2_sata_init()
438 val |= (0x9 << OOB_CTRL1_WAKE_IDLE_MAX_SHIFT); in brcm_ns2_sata_init()
439 val |= (0x3 << OOB_CTRL1_WAKE_IDLE_MIN_SHIFT); in brcm_ns2_sata_init()
440 brcm_sata_phy_wr(port, OOB_REG_BANK, OOB_CTRL1, 0x0, val); in brcm_ns2_sata_init()
441 val = 0x0; in brcm_ns2_sata_init()
442 val |= (0x1b << OOB_CTRL2_RESET_IDLE_MAX_SHIFT); in brcm_ns2_sata_init()
443 val |= (0x2 << OOB_CTRL2_BURST_CNT_SHIFT); in brcm_ns2_sata_init()
444 val |= (0x9 << OOB_CTRL2_RESET_IDLE_MIN_SHIFT); in brcm_ns2_sata_init()
445 brcm_sata_phy_wr(port, OOB_REG_BANK, OOB_CTRL2, 0x0, val); in brcm_ns2_sata_init()
449 brcm_sata_phy_wr(port, PLL1_REG_BANK, PLL1_ACTRL2, 0x0, val); in brcm_ns2_sata_init()
451 brcm_sata_phy_wr(port, PLL1_REG_BANK, PLL1_ACTRL3, 0x0, val); in brcm_ns2_sata_init()
453 brcm_sata_phy_wr(port, PLL1_REG_BANK, PLL1_ACTRL4, 0x0, val); in brcm_ns2_sata_init()
464 writel(0x0, ctrl_base + PHY_CTRL_1); in brcm_ns2_sata_init()
485 return 0; in brcm_ns2_sata_init()
495 if (port->portnum == 0) in brcm_nsp_sata_init()
502 val = 0x0; in brcm_nsp_sata_init()
503 val |= (0x0f << OOB_CTRL1_BURST_MAX_SHIFT); in brcm_nsp_sata_init()
504 val |= (0x06 << OOB_CTRL1_BURST_MIN_SHIFT); in brcm_nsp_sata_init()
505 val |= (0x0f << OOB_CTRL1_WAKE_IDLE_MAX_SHIFT); in brcm_nsp_sata_init()
506 val |= (0x06 << OOB_CTRL1_WAKE_IDLE_MIN_SHIFT); in brcm_nsp_sata_init()
507 brcm_sata_phy_wr(port, oob_bank, OOB_CTRL1, 0x0, val); in brcm_nsp_sata_init()
509 val = 0x0; in brcm_nsp_sata_init()
510 val |= (0x2e << OOB_CTRL2_RESET_IDLE_MAX_SHIFT); in brcm_nsp_sata_init()
511 val |= (0x02 << OOB_CTRL2_BURST_CNT_SHIFT); in brcm_nsp_sata_init()
512 val |= (0x16 << OOB_CTRL2_RESET_IDLE_MIN_SHIFT); in brcm_nsp_sata_init()
513 brcm_sata_phy_wr(port, oob_bank, OOB_CTRL2, 0x0, val); in brcm_nsp_sata_init()
518 0x0c << PLL_ACTRL2_SELDIV_SHIFT); in brcm_nsp_sata_init()
521 0xff0, 0x4f0); in brcm_nsp_sata_init()
528 ~val, 0); in brcm_nsp_sata_init()
550 return 0; in brcm_nsp_sata_init()
554 #define SR_PLL0_ACTRL6_MAGIC 0xa
557 #define SR_PLL1_ACTRL2_MAGIC 0x32
558 #define SR_PLL1_ACTRL3_MAGIC 0x2
559 #define SR_PLL1_ACTRL4_MAGIC 0x3e8
568 brcm_sata_phy_wr(port, PLL1_REG_BANK, PLL1_ACTRL2, 0x0, val); in brcm_sr_sata_init()
570 brcm_sata_phy_wr(port, PLL1_REG_BANK, PLL1_ACTRL3, 0x0, val); in brcm_sr_sata_init()
572 brcm_sata_phy_wr(port, PLL1_REG_BANK, PLL1_ACTRL4, 0x0, val); in brcm_sr_sata_init()
574 /* Configure PHY PLL register bank 0 */ in brcm_sr_sata_init()
576 brcm_sata_phy_wr(port, PLL_REG_BANK_0, PLL_ACTRL6, 0x0, val); in brcm_sr_sata_init()
589 if ((val & BLOCK0_XGXSSTATUS_PLL_LOCK) == 0) { in brcm_sr_sata_init()
600 val = ((0xc << OOB_CTRL1_BURST_MAX_SHIFT) | in brcm_sr_sata_init()
601 (0x4 << OOB_CTRL1_BURST_MIN_SHIFT) | in brcm_sr_sata_init()
602 (0x8 << OOB_CTRL1_WAKE_IDLE_MAX_SHIFT) | in brcm_sr_sata_init()
603 (0x3 << OOB_CTRL1_WAKE_IDLE_MIN_SHIFT)); in brcm_sr_sata_init()
604 brcm_sata_phy_wr(port, OOB_REG_BANK, OOB_CTRL1, 0x0, val); in brcm_sr_sata_init()
605 val = ((0x1b << OOB_CTRL2_RESET_IDLE_MAX_SHIFT) | in brcm_sr_sata_init()
606 (0x2 << OOB_CTRL2_BURST_CNT_SHIFT) | in brcm_sr_sata_init()
607 (0x9 << OOB_CTRL2_RESET_IDLE_MIN_SHIFT)); in brcm_sr_sata_init()
608 brcm_sata_phy_wr(port, OOB_REG_BANK, OOB_CTRL2, 0x0, val); in brcm_sr_sata_init()
610 return 0; in brcm_sr_sata_init()
619 brcm_sata_phy_wr(port, PLL1_REG_BANK, PLL1_ACTRL7, 0, 0x873); in brcm_dsl_sata_init()
621 brcm_sata_phy_wr(port, PLL1_REG_BANK, PLL1_ACTRL6, 0, 0xc000); in brcm_dsl_sata_init()
624 0, 0x3089); in brcm_dsl_sata_init()
628 0, 0x3088); in brcm_dsl_sata_init()
632 0, 0x3000); in brcm_dsl_sata_init()
635 0, 0x3000); in brcm_dsl_sata_init()
638 brcm_sata_phy_wr(port, PLL_REG_BANK_0, PLL_CAP_CHARGE_TIME, 0, 0x32); in brcm_dsl_sata_init()
640 brcm_sata_phy_wr(port, PLL_REG_BANK_0, PLL_VCO_CAL_THRESH, 0, 0xa); in brcm_dsl_sata_init()
642 brcm_sata_phy_wr(port, PLL_REG_BANK_0, PLL_FREQ_DET_TIME, 0, 0x64); in brcm_dsl_sata_init()
664 return 0; in brcm_dsl_sata_init()
716 rc = 0; in brcm_sata_phy_calibrate()
758 int ret, count = 0; in brcm_sata_phy_probe()
760 if (of_get_child_count(dn) == 0) in brcm_sata_phy_probe()
841 return 0; in brcm_sata_phy_probe()