Lines Matching refs:C
105 #define C(x) PERF_COUNT_HW_CACHE_##x macro
109 [C(L1D)] = {
110 [C(OP_READ)] = {
111 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
112 C(OP_READ), C(L1D), SBI_PMU_EVENT_TYPE_CACHE, 0}},
113 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
114 C(OP_READ), C(L1D), SBI_PMU_EVENT_TYPE_CACHE, 0}},
116 [C(OP_WRITE)] = {
117 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
118 C(OP_WRITE), C(L1D), SBI_PMU_EVENT_TYPE_CACHE, 0}},
119 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
120 C(OP_WRITE), C(L1D), SBI_PMU_EVENT_TYPE_CACHE, 0}},
122 [C(OP_PREFETCH)] = {
123 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
124 C(OP_PREFETCH), C(L1D), SBI_PMU_EVENT_TYPE_CACHE, 0}},
125 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
126 C(OP_PREFETCH), C(L1D), SBI_PMU_EVENT_TYPE_CACHE, 0}},
129 [C(L1I)] = {
130 [C(OP_READ)] = {
131 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
132 C(OP_READ), C(L1I), SBI_PMU_EVENT_TYPE_CACHE, 0}},
133 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS), C(OP_READ),
134 C(L1I), SBI_PMU_EVENT_TYPE_CACHE, 0}},
136 [C(OP_WRITE)] = {
137 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
138 C(OP_WRITE), C(L1I), SBI_PMU_EVENT_TYPE_CACHE, 0}},
139 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
140 C(OP_WRITE), C(L1I), SBI_PMU_EVENT_TYPE_CACHE, 0}},
142 [C(OP_PREFETCH)] = {
143 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
144 C(OP_PREFETCH), C(L1I), SBI_PMU_EVENT_TYPE_CACHE, 0}},
145 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
146 C(OP_PREFETCH), C(L1I), SBI_PMU_EVENT_TYPE_CACHE, 0}},
149 [C(LL)] = {
150 [C(OP_READ)] = {
151 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
152 C(OP_READ), C(LL), SBI_PMU_EVENT_TYPE_CACHE, 0}},
153 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
154 C(OP_READ), C(LL), SBI_PMU_EVENT_TYPE_CACHE, 0}},
156 [C(OP_WRITE)] = {
157 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
158 C(OP_WRITE), C(LL), SBI_PMU_EVENT_TYPE_CACHE, 0}},
159 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
160 C(OP_WRITE), C(LL), SBI_PMU_EVENT_TYPE_CACHE, 0}},
162 [C(OP_PREFETCH)] = {
163 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
164 C(OP_PREFETCH), C(LL), SBI_PMU_EVENT_TYPE_CACHE, 0}},
165 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
166 C(OP_PREFETCH), C(LL), SBI_PMU_EVENT_TYPE_CACHE, 0}},
169 [C(DTLB)] = {
170 [C(OP_READ)] = {
171 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
172 C(OP_READ), C(DTLB), SBI_PMU_EVENT_TYPE_CACHE, 0}},
173 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
174 C(OP_READ), C(DTLB), SBI_PMU_EVENT_TYPE_CACHE, 0}},
176 [C(OP_WRITE)] = {
177 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
178 C(OP_WRITE), C(DTLB), SBI_PMU_EVENT_TYPE_CACHE, 0}},
179 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
180 C(OP_WRITE), C(DTLB), SBI_PMU_EVENT_TYPE_CACHE, 0}},
182 [C(OP_PREFETCH)] = {
183 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
184 C(OP_PREFETCH), C(DTLB), SBI_PMU_EVENT_TYPE_CACHE, 0}},
185 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
186 C(OP_PREFETCH), C(DTLB), SBI_PMU_EVENT_TYPE_CACHE, 0}},
189 [C(ITLB)] = {
190 [C(OP_READ)] = {
191 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
192 C(OP_READ), C(ITLB), SBI_PMU_EVENT_TYPE_CACHE, 0}},
193 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
194 C(OP_READ), C(ITLB), SBI_PMU_EVENT_TYPE_CACHE, 0}},
196 [C(OP_WRITE)] = {
197 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
198 C(OP_WRITE), C(ITLB), SBI_PMU_EVENT_TYPE_CACHE, 0}},
199 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
200 C(OP_WRITE), C(ITLB), SBI_PMU_EVENT_TYPE_CACHE, 0}},
202 [C(OP_PREFETCH)] = {
203 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
204 C(OP_PREFETCH), C(ITLB), SBI_PMU_EVENT_TYPE_CACHE, 0}},
205 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
206 C(OP_PREFETCH), C(ITLB), SBI_PMU_EVENT_TYPE_CACHE, 0}},
209 [C(BPU)] = {
210 [C(OP_READ)] = {
211 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
212 C(OP_READ), C(BPU), SBI_PMU_EVENT_TYPE_CACHE, 0}},
213 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
214 C(OP_READ), C(BPU), SBI_PMU_EVENT_TYPE_CACHE, 0}},
216 [C(OP_WRITE)] = {
217 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
218 C(OP_WRITE), C(BPU), SBI_PMU_EVENT_TYPE_CACHE, 0}},
219 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
220 C(OP_WRITE), C(BPU), SBI_PMU_EVENT_TYPE_CACHE, 0}},
222 [C(OP_PREFETCH)] = {
223 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
224 C(OP_PREFETCH), C(BPU), SBI_PMU_EVENT_TYPE_CACHE, 0}},
225 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
226 C(OP_PREFETCH), C(BPU), SBI_PMU_EVENT_TYPE_CACHE, 0}},
229 [C(NODE)] = {
230 [C(OP_READ)] = {
231 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
232 C(OP_READ), C(NODE), SBI_PMU_EVENT_TYPE_CACHE, 0}},
233 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
234 C(OP_READ), C(NODE), SBI_PMU_EVENT_TYPE_CACHE, 0}},
236 [C(OP_WRITE)] = {
237 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
238 C(OP_WRITE), C(NODE), SBI_PMU_EVENT_TYPE_CACHE, 0}},
239 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
240 C(OP_WRITE), C(NODE), SBI_PMU_EVENT_TYPE_CACHE, 0}},
242 [C(OP_PREFETCH)] = {
243 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
244 C(OP_PREFETCH), C(NODE), SBI_PMU_EVENT_TYPE_CACHE, 0}},
245 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
246 C(OP_PREFETCH), C(NODE), SBI_PMU_EVENT_TYPE_CACHE, 0}},