74 u64 riscv_pmu_ctr_get_width_mask(struct perf_event *event)  in riscv_pmu_ctr_get_width_mask()  argument
77 	struct riscv_pmu *rvpmu = to_riscv_pmu(event->pmu);  in riscv_pmu_ctr_get_width_mask()
78 	struct hw_perf_event *hwc = &event->hw;  in riscv_pmu_ctr_get_width_mask()
97 u64 riscv_pmu_event_update(struct perf_event *event)  in riscv_pmu_event_update()  argument
99 	struct riscv_pmu *rvpmu = to_riscv_pmu(event->pmu);  in riscv_pmu_event_update()
100 	struct hw_perf_event *hwc = &event->hw;  in riscv_pmu_event_update()
108 	cmask = riscv_pmu_ctr_get_width_mask(event);  in riscv_pmu_event_update()
112 		new_raw_count = rvpmu->ctr_read(event);  in riscv_pmu_event_update()
118 	local64_add(delta, &event->count);  in riscv_pmu_event_update()
124 void riscv_pmu_stop(struct perf_event *event, int flags)  in riscv_pmu_stop()  argument
126 	struct hw_perf_event *hwc = &event->hw;  in riscv_pmu_stop()
127 	struct riscv_pmu *rvpmu = to_riscv_pmu(event->pmu);  in riscv_pmu_stop()
133 			rvpmu->ctr_stop(event, 0);  in riscv_pmu_stop()
136 		riscv_pmu_event_update(event);  in riscv_pmu_stop()
141 int riscv_pmu_event_set_period(struct perf_event *event)  in riscv_pmu_event_set_period()  argument
143 	struct hw_perf_event *hwc = &event->hw;  in riscv_pmu_event_set_period()
147 	uint64_t max_period = riscv_pmu_ctr_get_width_mask(event);  in riscv_pmu_event_set_period()
177 void riscv_pmu_start(struct perf_event *event, int flags)  in riscv_pmu_start()  argument
179 	struct hw_perf_event *hwc = &event->hw;  in riscv_pmu_start()
180 	struct riscv_pmu *rvpmu = to_riscv_pmu(event->pmu);  in riscv_pmu_start()
181 	uint64_t max_period = riscv_pmu_ctr_get_width_mask(event);  in riscv_pmu_start()
184 	if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED)))  in riscv_pmu_start()
188 		WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));  in riscv_pmu_start()
191 	riscv_pmu_event_set_period(event);  in riscv_pmu_start()
193 	rvpmu->ctr_start(event, init_val);  in riscv_pmu_start()
194 	perf_event_update_userpage(event);  in riscv_pmu_start()
197 static int riscv_pmu_add(struct perf_event *event, int flags)  in riscv_pmu_add()  argument
199 	struct riscv_pmu *rvpmu = to_riscv_pmu(event->pmu);  in riscv_pmu_add()
201 	struct hw_perf_event *hwc = &event->hw;  in riscv_pmu_add()
204 	idx = rvpmu->ctr_get_idx(event);  in riscv_pmu_add()
209 	cpuc->events[idx] = event;  in riscv_pmu_add()
213 		riscv_pmu_start(event, PERF_EF_RELOAD);  in riscv_pmu_add()
216 	perf_event_update_userpage(event);  in riscv_pmu_add()
221 static void riscv_pmu_del(struct perf_event *event, int flags)  in riscv_pmu_del()  argument
223 	struct riscv_pmu *rvpmu = to_riscv_pmu(event->pmu);  in riscv_pmu_del()
225 	struct hw_perf_event *hwc = &event->hw;  in riscv_pmu_del()
227 	riscv_pmu_stop(event, PERF_EF_UPDATE);  in riscv_pmu_del()
231 		rvpmu->ctr_stop(event, RISCV_PMU_STOP_FLAG_RESET);  in riscv_pmu_del()
234 		rvpmu->ctr_clear_idx(event);  in riscv_pmu_del()
235 	perf_event_update_userpage(event);  in riscv_pmu_del()
239 static void riscv_pmu_read(struct perf_event *event)  in riscv_pmu_read()  argument
241 	riscv_pmu_event_update(event);  in riscv_pmu_read()
244 static int riscv_pmu_event_init(struct perf_event *event)  in riscv_pmu_event_init()  argument
246 	struct hw_perf_event *hwc = &event->hw;  in riscv_pmu_event_init()
247 	struct riscv_pmu *rvpmu = to_riscv_pmu(event->pmu);  in riscv_pmu_event_init()
253 	mapped_event = rvpmu->event_map(event, &event_config);  in riscv_pmu_event_init()
255 		pr_debug("event %x:%llx not supported\n", event->attr.type,  in riscv_pmu_event_init()
256 			 event->attr.config);  in riscv_pmu_event_init()
270 	if (!is_sampling_event(event)) {  in riscv_pmu_event_init()
277 		cmask = riscv_pmu_ctr_get_width_mask(event);  in riscv_pmu_event_init()