31 #define L2PMCR_NUM_EV_MASK      0x1F
33 #define L2PMCR                  0x400
34 #define L2PMCNTENCLR            0x403
35 #define L2PMCNTENSET            0x404
36 #define L2PMINTENCLR            0x405
37 #define L2PMINTENSET            0x406
38 #define L2PMOVSCLR              0x407
39 #define L2PMOVSSET              0x408
40 #define L2PMCCNTCR              0x409
41 #define L2PMCCNTR               0x40A
42 #define L2PMCCNTSR              0x40C
43 #define L2PMRESR                0x410
44 #define IA_L2PMXEVCNTCR_BASE    0x420
45 #define IA_L2PMXEVCNTR_BASE     0x421
46 #define IA_L2PMXEVFILTER_BASE   0x423
47 #define IA_L2PMXEVTYPER_BASE    0x424
49 #define IA_L2_REG_OFFSET        0x10
51 #define L2PMXEVFILTER_SUFILTER_ALL      0x000E0000
52 #define L2PMXEVFILTER_ORGFILTER_IDINDEP 0x00000004
53 #define L2PMXEVFILTER_ORGFILTER_ALL     0x00000003
58 #define L2PMRESR_GROUP_MASK     GENMASK(7, 0)
61 #define L2CYCLE_CTR_RAW_CODE    0xFE
63 #define L2PMCR_RESET_ALL        0x6
64 #define L2PMCR_COUNTERS_ENABLE  0x1
65 #define L2PMCR_COUNTERS_DISABLE 0x0
69 #define L2_EVT_MASK             0x00000FFF
70 #define L2_EVT_CODE_MASK        0x00000FF0
71 #define L2_EVT_GRP_MASK         0x0000000F
73 #define L2_EVT_GRP_SHIFT        0
89 #define L2_EVENT_CYCLES                    0xfe
90 #define L2_EVENT_DCACHE_OPS                0x400
91 #define L2_EVENT_ICACHE_OPS                0x401
92 #define L2_EVENT_TLBI                      0x402
93 #define L2_EVENT_BARRIERS                  0x403
94 #define L2_EVENT_TOTAL_READS               0x405
95 #define L2_EVENT_TOTAL_WRITES              0x406
96 #define L2_EVENT_TOTAL_REQUESTS            0x407
97 #define L2_EVENT_LDREX                     0x420
98 #define L2_EVENT_STREX                     0x421
99 #define L2_EVENT_CLREX                     0x422
129  * Events are specified as 0xCCG, where CC is 2 hex digits specifying
314 		delta &= 0xffffffff;  in l2_cache_event_update()
456 	if (event->cpu < 0) {  in l2_cache_event_init()
463 	     ((event->attr.config & ~L2_EVT_MASK) != 0)) &&  in l2_cache_event_init()
538 	return 0;  in l2_cache_event_init()
549 	hwc->state = 0;  in l2_cache_event_start()
556 		cluster_pmu_set_evccntcr(0);  in l2_cache_event_start()
562 		cluster_pmu_set_evcntcr(idx, 0);  in l2_cache_event_start()
592 	int err = 0;  in l2_cache_event_add()
598 	if (idx < 0)  in l2_cache_event_add()
604 	local64_set(&hwc->prev_count, 0);  in l2_cache_event_add()
658 PMU_FORMAT_ATTR(l2_group,  "config:0-3");
659 PMU_FORMAT_ATTR(event,     "config:0-11");
679 	return sysfs_emit(page, "event=0x%02llx\n", pmu_attr->id);  in l2cache_pmu_event_show()
780 			return 0;  in l2cache_pmu_online_cpu()
786 		return 0;  in l2cache_pmu_online_cpu()
799 	return 0;  in l2cache_pmu_online_cpu()
812 		return 0;  in l2cache_pmu_offline_cpu()
816 		return 0;  in l2cache_pmu_offline_cpu()
828 		return 0;  in l2cache_pmu_offline_cpu()
836 	return 0;  in l2cache_pmu_offline_cpu()
863 	irq = platform_get_irq(sdev, 0);  in l2_cache_pmu_probe_cluster()
864 	if (irq < 0)  in l2_cache_pmu_probe_cluster()
888 	return 0;  in l2_cache_pmu_probe_cluster()
928 	l2_counter_present_mask = GENMASK(l2cache_pmu->num_counters - 2, 0) |  in l2_cache_pmu_probe()
939 	if (l2cache_pmu->num_pmus == 0) {  in l2_cache_pmu_probe()
976 	return 0;  in l2_cache_pmu_remove()