Lines Matching refs:fld
957 int fld; in __arm_spe_pmu_dev_probe() local
962 fld = cpuid_feature_extract_unsigned_field(read_cpuid(ID_AA64DFR0_EL1), in __arm_spe_pmu_dev_probe()
964 if (!fld) { in __arm_spe_pmu_dev_probe()
967 fld, smp_processor_id()); in __arm_spe_pmu_dev_probe()
970 spe_pmu->pmsver = (u16)fld; in __arm_spe_pmu_dev_probe()
981 fld = reg >> SYS_PMBIDR_EL1_ALIGN_SHIFT & SYS_PMBIDR_EL1_ALIGN_MASK; in __arm_spe_pmu_dev_probe()
982 spe_pmu->align = 1 << fld; in __arm_spe_pmu_dev_probe()
985 fld, smp_processor_id()); in __arm_spe_pmu_dev_probe()
1010 fld = reg >> SYS_PMSIDR_EL1_INTERVAL_SHIFT & SYS_PMSIDR_EL1_INTERVAL_MASK; in __arm_spe_pmu_dev_probe()
1011 switch (fld) { in __arm_spe_pmu_dev_probe()
1035 fld); in __arm_spe_pmu_dev_probe()
1042 fld = reg >> SYS_PMSIDR_EL1_MAXSIZE_SHIFT & SYS_PMSIDR_EL1_MAXSIZE_MASK; in __arm_spe_pmu_dev_probe()
1043 spe_pmu->max_record_sz = 1 << fld; in __arm_spe_pmu_dev_probe()
1046 fld, smp_processor_id()); in __arm_spe_pmu_dev_probe()
1050 fld = reg >> SYS_PMSIDR_EL1_COUNTSIZE_SHIFT & SYS_PMSIDR_EL1_COUNTSIZE_MASK; in __arm_spe_pmu_dev_probe()
1051 switch (fld) { in __arm_spe_pmu_dev_probe()
1054 fld); in __arm_spe_pmu_dev_probe()