Lines Matching +full:dt +full:- +full:node
1 // SPDX-License-Identifier: GPL-2.0-only
112 #define CCN_TYPE_RND_1P 0x18 /* RN-D = RN-I + DVM */
120 #define CCN_NUM_XP_WATCHPOINTS 2 /* See DT.dbg_id.num_watchpoints */
121 #define CCN_NUM_PMU_EVENT_COUNTERS 8 /* See DT.dbg_id.num_pmucntr */
143 struct arm_ccn_dt, pmu), struct arm_ccn, dt)
164 struct hlist_node node; member
178 struct arm_ccn_component *node; member
183 struct arm_ccn_dt dt; member
187 static int arm_ccn_node_to_xp(int node) in arm_ccn_node_to_xp() argument
189 return node / CCN_NUM_XP_PORTS; in arm_ccn_node_to_xp()
192 static int arm_ccn_node_to_xp_port(int node) in arm_ccn_node_to_xp_port() argument
194 return node % CCN_NUM_XP_PORTS; in arm_ccn_node_to_xp_port()
224 return sysfs_emit(buf, "%s\n", (char *)ea->var); in arm_ccn_pmu_format_show()
232 static CCN_FORMAT_ATTR(node, "config:0-7");
233 static CCN_FORMAT_ATTR(xp, "config:0-7");
234 static CCN_FORMAT_ATTR(type, "config:8-15");
235 static CCN_FORMAT_ATTR(event, "config:16-23");
236 static CCN_FORMAT_ATTR(port, "config:24-25");
237 static CCN_FORMAT_ATTR(bus, "config:24-25");
238 static CCN_FORMAT_ATTR(vc, "config:26-28");
239 static CCN_FORMAT_ATTR(dir, "config:29-29");
240 static CCN_FORMAT_ATTR(mask, "config:30-33");
241 static CCN_FORMAT_ATTR(cmp_l, "config1:0-62");
242 static CCN_FORMAT_ATTR(cmp_h, "config2:0-59");
279 * Events defined in TRM for MN, HN-I and SBSX are actually watchpoints set on
309 * RN-I & RN-D (RN-D = RN-I + DVM) nodes have different type ID depending
331 res = sysfs_emit(buf, "type=0x%x", event->type); in arm_ccn_pmu_event_show()
332 if (event->event) in arm_ccn_pmu_event_show()
333 res += sysfs_emit_at(buf, res, ",event=0x%x", event->event); in arm_ccn_pmu_event_show()
334 if (event->def) in arm_ccn_pmu_event_show()
335 res += sysfs_emit_at(buf, res, ",%s", event->def); in arm_ccn_pmu_event_show()
336 if (event->mask) in arm_ccn_pmu_event_show()
337 res += sysfs_emit_at(buf, res, ",mask=0x%x", event->mask); in arm_ccn_pmu_event_show()
340 switch (event->type) { in arm_ccn_pmu_event_show()
345 if (event->event == CCN_EVENT_WATCHPOINT) in arm_ccn_pmu_event_show()
353 res += sysfs_emit_at(buf, res, ",node=%d", ccn->mn_id); in arm_ccn_pmu_event_show()
356 res += sysfs_emit_at(buf, res, ",node=?"); in arm_ccn_pmu_event_show()
375 if (event->type == CCN_TYPE_SBAS && !ccn->sbas_present) in arm_ccn_pmu_events_is_visible()
377 if (event->type == CCN_TYPE_SBSX && !ccn->sbsx_present) in arm_ccn_pmu_events_is_visible()
380 return attr->mode; in arm_ccn_pmu_events_is_visible()
456 i = isdigit(name[0]) ? name[0] - '0' : 0xa + tolower(name[0]) - 'a'; in arm_ccn_pmu_get_cmp_mask()
460 return &ccn->dt.cmp_mask[i].l; in arm_ccn_pmu_get_cmp_mask()
462 return &ccn->dt.cmp_mask[i].h; in arm_ccn_pmu_get_cmp_mask()
472 u64 *mask = arm_ccn_pmu_get_cmp_mask(ccn, attr->attr.name); in arm_ccn_pmu_cmp_mask_show()
474 return mask ? sysfs_emit(buf, "0x%016llx\n", *mask) : -EINVAL; in arm_ccn_pmu_cmp_mask_show()
481 u64 *mask = arm_ccn_pmu_get_cmp_mask(ccn, attr->attr.name); in arm_ccn_pmu_cmp_mask_store()
482 int err = -EINVAL; in arm_ccn_pmu_cmp_mask_store()
550 return cpumap_print_to_pagebuf(true, buf, cpumask_of(ccn->dt.cpu)); in arm_ccn_pmu_cpumask_show()
597 return -EAGAIN; in arm_ccn_pmu_alloc_bit()
603 /* All RN-I and RN-D nodes have identical PMUs */
633 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu); in arm_ccn_pmu_event_alloc()
634 struct hw_perf_event *hw = &event->hw; in arm_ccn_pmu_event_alloc()
639 node_xp = CCN_CONFIG_NODE(event->attr.config); in arm_ccn_pmu_event_alloc()
640 type = CCN_CONFIG_TYPE(event->attr.config); in arm_ccn_pmu_event_alloc()
641 event_id = CCN_CONFIG_EVENT(event->attr.config); in arm_ccn_pmu_event_alloc()
646 ccn->dt.pmu_counters_mask)) in arm_ccn_pmu_event_alloc()
647 return -EAGAIN; in arm_ccn_pmu_event_alloc()
649 hw->idx = CCN_IDX_PMU_CYCLE_COUNTER; in arm_ccn_pmu_event_alloc()
650 ccn->dt.pmu_counters[CCN_IDX_PMU_CYCLE_COUNTER].event = event; in arm_ccn_pmu_event_alloc()
656 hw->idx = arm_ccn_pmu_alloc_bit(ccn->dt.pmu_counters_mask, in arm_ccn_pmu_event_alloc()
658 if (hw->idx < 0) { in arm_ccn_pmu_event_alloc()
659 dev_dbg(ccn->dev, "No more counters available!\n"); in arm_ccn_pmu_event_alloc()
660 return -EAGAIN; in arm_ccn_pmu_event_alloc()
664 source = &ccn->xp[node_xp]; in arm_ccn_pmu_event_alloc()
666 source = &ccn->node[node_xp]; in arm_ccn_pmu_event_alloc()
667 ccn->dt.pmu_counters[hw->idx].source = source; in arm_ccn_pmu_event_alloc()
671 bit = arm_ccn_pmu_alloc_bit(source->xp.dt_cmp_mask, in arm_ccn_pmu_event_alloc()
674 bit = arm_ccn_pmu_alloc_bit(source->pmu_events_mask, in arm_ccn_pmu_event_alloc()
677 dev_dbg(ccn->dev, "No more event sources/watchpoints on node/XP %d!\n", in arm_ccn_pmu_event_alloc()
679 clear_bit(hw->idx, ccn->dt.pmu_counters_mask); in arm_ccn_pmu_event_alloc()
680 return -EAGAIN; in arm_ccn_pmu_event_alloc()
682 hw->config_base = bit; in arm_ccn_pmu_event_alloc()
684 ccn->dt.pmu_counters[hw->idx].event = event; in arm_ccn_pmu_event_alloc()
691 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu); in arm_ccn_pmu_event_release()
692 struct hw_perf_event *hw = &event->hw; in arm_ccn_pmu_event_release()
694 if (hw->idx == CCN_IDX_PMU_CYCLE_COUNTER) { in arm_ccn_pmu_event_release()
695 clear_bit(CCN_IDX_PMU_CYCLE_COUNTER, ccn->dt.pmu_counters_mask); in arm_ccn_pmu_event_release()
698 ccn->dt.pmu_counters[hw->idx].source; in arm_ccn_pmu_event_release()
700 if (CCN_CONFIG_TYPE(event->attr.config) == CCN_TYPE_XP && in arm_ccn_pmu_event_release()
701 CCN_CONFIG_EVENT(event->attr.config) == in arm_ccn_pmu_event_release()
703 clear_bit(hw->config_base, source->xp.dt_cmp_mask); in arm_ccn_pmu_event_release()
705 clear_bit(hw->config_base, source->pmu_events_mask); in arm_ccn_pmu_event_release()
706 clear_bit(hw->idx, ccn->dt.pmu_counters_mask); in arm_ccn_pmu_event_release()
709 ccn->dt.pmu_counters[hw->idx].source = NULL; in arm_ccn_pmu_event_release()
710 ccn->dt.pmu_counters[hw->idx].event = NULL; in arm_ccn_pmu_event_release()
716 struct hw_perf_event *hw = &event->hw; in arm_ccn_pmu_event_init()
722 if (event->attr.type != event->pmu->type) in arm_ccn_pmu_event_init()
723 return -ENOENT; in arm_ccn_pmu_event_init()
725 ccn = pmu_to_arm_ccn(event->pmu); in arm_ccn_pmu_event_init()
727 if (hw->sample_period) { in arm_ccn_pmu_event_init()
728 dev_dbg(ccn->dev, "Sampling not supported!\n"); in arm_ccn_pmu_event_init()
729 return -EOPNOTSUPP; in arm_ccn_pmu_event_init()
733 dev_dbg(ccn->dev, "Can't exclude execution levels!\n"); in arm_ccn_pmu_event_init()
734 return -EINVAL; in arm_ccn_pmu_event_init()
737 if (event->cpu < 0) { in arm_ccn_pmu_event_init()
738 dev_dbg(ccn->dev, "Can't provide per-task data!\n"); in arm_ccn_pmu_event_init()
739 return -EOPNOTSUPP; in arm_ccn_pmu_event_init()
745 * but can lead to issues for off-core PMUs, like CCN, where each in arm_ccn_pmu_event_init()
750 event->cpu = ccn->dt.cpu; in arm_ccn_pmu_event_init()
752 node_xp = CCN_CONFIG_NODE(event->attr.config); in arm_ccn_pmu_event_init()
753 type = CCN_CONFIG_TYPE(event->attr.config); in arm_ccn_pmu_event_init()
754 event_id = CCN_CONFIG_EVENT(event->attr.config); in arm_ccn_pmu_event_init()
756 /* Validate node/xp vs topology */ in arm_ccn_pmu_event_init()
759 if (node_xp != ccn->mn_id) { in arm_ccn_pmu_event_init()
760 dev_dbg(ccn->dev, "Invalid MN ID %d!\n", node_xp); in arm_ccn_pmu_event_init()
761 return -EINVAL; in arm_ccn_pmu_event_init()
765 if (node_xp >= ccn->num_xps) { in arm_ccn_pmu_event_init()
766 dev_dbg(ccn->dev, "Invalid XP ID %d!\n", node_xp); in arm_ccn_pmu_event_init()
767 return -EINVAL; in arm_ccn_pmu_event_init()
773 if (node_xp >= ccn->num_nodes) { in arm_ccn_pmu_event_init()
774 dev_dbg(ccn->dev, "Invalid node ID %d!\n", node_xp); in arm_ccn_pmu_event_init()
775 return -EINVAL; in arm_ccn_pmu_event_init()
777 if (!arm_ccn_pmu_type_eq(type, ccn->node[node_xp].type)) { in arm_ccn_pmu_event_init()
778 dev_dbg(ccn->dev, "Invalid type 0x%x for node %d!\n", in arm_ccn_pmu_event_init()
780 return -EINVAL; in arm_ccn_pmu_event_init()
789 u32 port = CCN_CONFIG_PORT(event->attr.config); in arm_ccn_pmu_event_init()
790 u32 vc = CCN_CONFIG_VC(event->attr.config); in arm_ccn_pmu_event_init()
792 if (!arm_ccn_pmu_type_eq(type, e->type)) in arm_ccn_pmu_event_init()
794 if (event_id != e->event) in arm_ccn_pmu_event_init()
796 if (e->num_ports && port >= e->num_ports) { in arm_ccn_pmu_event_init()
797 dev_dbg(ccn->dev, "Invalid port %d for node/XP %d!\n", in arm_ccn_pmu_event_init()
799 return -EINVAL; in arm_ccn_pmu_event_init()
801 if (e->num_vcs && vc >= e->num_vcs) { in arm_ccn_pmu_event_init()
802 dev_dbg(ccn->dev, "Invalid vc %d for node/XP %d!\n", in arm_ccn_pmu_event_init()
804 return -EINVAL; in arm_ccn_pmu_event_init()
809 dev_dbg(ccn->dev, "Invalid event 0x%x for node/XP %d!\n", in arm_ccn_pmu_event_init()
811 return -EINVAL; in arm_ccn_pmu_event_init()
814 /* Watchpoint-based event for a node is actually set on XP */ in arm_ccn_pmu_event_init()
822 arm_ccn_pmu_config_set(&event->attr.config, in arm_ccn_pmu_event_init()
829 * periodically read when a hrtimer aka cpu-clock leader triggers). in arm_ccn_pmu_event_init()
831 if (event->group_leader->pmu != event->pmu && in arm_ccn_pmu_event_init()
832 !is_software_event(event->group_leader)) in arm_ccn_pmu_event_init()
833 return -EINVAL; in arm_ccn_pmu_event_init()
835 for_each_sibling_event(sibling, event->group_leader) { in arm_ccn_pmu_event_init()
836 if (sibling->pmu != event->pmu && in arm_ccn_pmu_event_init()
838 return -EINVAL; in arm_ccn_pmu_event_init()
850 res = readq(ccn->dt.base + CCN_DT_PMCCNTR); in arm_ccn_pmu_read_counter()
853 writel(0x1, ccn->dt.base + CCN_DT_PMSR_REQ); in arm_ccn_pmu_read_counter()
854 while (!(readl(ccn->dt.base + CCN_DT_PMSR) & 0x1)) in arm_ccn_pmu_read_counter()
856 writel(0x1, ccn->dt.base + CCN_DT_PMSR_CLR); in arm_ccn_pmu_read_counter()
857 res = readl(ccn->dt.base + CCN_DT_PMCCNTRSR + 4) & 0xff; in arm_ccn_pmu_read_counter()
859 res |= readl(ccn->dt.base + CCN_DT_PMCCNTRSR); in arm_ccn_pmu_read_counter()
862 res = readl(ccn->dt.base + CCN_DT_PMEVCNT(idx)); in arm_ccn_pmu_read_counter()
870 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu); in arm_ccn_pmu_event_update()
871 struct hw_perf_event *hw = &event->hw; in arm_ccn_pmu_event_update()
875 prev_count = local64_read(&hw->prev_count); in arm_ccn_pmu_event_update()
876 new_count = arm_ccn_pmu_read_counter(ccn, hw->idx); in arm_ccn_pmu_event_update()
877 } while (local64_xchg(&hw->prev_count, new_count) != prev_count); in arm_ccn_pmu_event_update()
879 mask = (1LLU << (hw->idx == CCN_IDX_PMU_CYCLE_COUNTER ? 40 : 32)) - 1; in arm_ccn_pmu_event_update()
881 local64_add((new_count - prev_count) & mask, &event->count); in arm_ccn_pmu_event_update()
886 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu); in arm_ccn_pmu_xp_dt_config()
887 struct hw_perf_event *hw = &event->hw; in arm_ccn_pmu_xp_dt_config()
892 if (hw->idx == CCN_IDX_PMU_CYCLE_COUNTER) in arm_ccn_pmu_xp_dt_config()
895 if (CCN_CONFIG_TYPE(event->attr.config) == CCN_TYPE_XP) in arm_ccn_pmu_xp_dt_config()
896 xp = &ccn->xp[CCN_CONFIG_XP(event->attr.config)]; in arm_ccn_pmu_xp_dt_config()
898 xp = &ccn->xp[arm_ccn_node_to_xp( in arm_ccn_pmu_xp_dt_config()
899 CCN_CONFIG_NODE(event->attr.config))]; in arm_ccn_pmu_xp_dt_config()
902 dt_cfg = hw->event_base; in arm_ccn_pmu_xp_dt_config()
906 spin_lock(&ccn->dt.config_lock); in arm_ccn_pmu_xp_dt_config()
908 val = readl(xp->base + CCN_XP_DT_CONFIG); in arm_ccn_pmu_xp_dt_config()
910 CCN_XP_DT_CONFIG__DT_CFG__SHIFT(hw->idx)); in arm_ccn_pmu_xp_dt_config()
911 val |= dt_cfg << CCN_XP_DT_CONFIG__DT_CFG__SHIFT(hw->idx); in arm_ccn_pmu_xp_dt_config()
912 writel(val, xp->base + CCN_XP_DT_CONFIG); in arm_ccn_pmu_xp_dt_config()
914 spin_unlock(&ccn->dt.config_lock); in arm_ccn_pmu_xp_dt_config()
919 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu); in arm_ccn_pmu_event_start()
920 struct hw_perf_event *hw = &event->hw; in arm_ccn_pmu_event_start()
922 local64_set(&event->hw.prev_count, in arm_ccn_pmu_event_start()
923 arm_ccn_pmu_read_counter(ccn, hw->idx)); in arm_ccn_pmu_event_start()
924 hw->state = 0; in arm_ccn_pmu_event_start()
926 /* Set the DT bus input, engaging the counter */ in arm_ccn_pmu_event_start()
932 struct hw_perf_event *hw = &event->hw; in arm_ccn_pmu_event_stop()
934 /* Disable counting, setting the DT bus to pass-through mode */ in arm_ccn_pmu_event_stop()
940 hw->state |= PERF_HES_STOPPED; in arm_ccn_pmu_event_stop()
945 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu); in arm_ccn_pmu_xp_watchpoint_config()
946 struct hw_perf_event *hw = &event->hw; in arm_ccn_pmu_xp_watchpoint_config()
948 ccn->dt.pmu_counters[hw->idx].source; in arm_ccn_pmu_xp_watchpoint_config()
949 unsigned long wp = hw->config_base; in arm_ccn_pmu_xp_watchpoint_config()
951 u64 cmp_l = event->attr.config1; in arm_ccn_pmu_xp_watchpoint_config()
952 u64 cmp_h = event->attr.config2; in arm_ccn_pmu_xp_watchpoint_config()
953 u64 mask_l = ccn->dt.cmp_mask[CCN_CONFIG_MASK(event->attr.config)].l; in arm_ccn_pmu_xp_watchpoint_config()
954 u64 mask_h = ccn->dt.cmp_mask[CCN_CONFIG_MASK(event->attr.config)].h; in arm_ccn_pmu_xp_watchpoint_config()
956 hw->event_base = CCN_XP_DT_CONFIG__DT_CFG__WATCHPOINT(wp); in arm_ccn_pmu_xp_watchpoint_config()
959 val = readl(source->base + CCN_XP_DT_INTERFACE_SEL); in arm_ccn_pmu_xp_watchpoint_config()
962 val |= CCN_CONFIG_DIR(event->attr.config) << in arm_ccn_pmu_xp_watchpoint_config()
966 val |= CCN_CONFIG_PORT(event->attr.config) << in arm_ccn_pmu_xp_watchpoint_config()
970 val |= CCN_CONFIG_VC(event->attr.config) << in arm_ccn_pmu_xp_watchpoint_config()
972 writel(val, source->base + CCN_XP_DT_INTERFACE_SEL); in arm_ccn_pmu_xp_watchpoint_config()
975 writel(cmp_l & 0xffffffff, source->base + CCN_XP_DT_CMP_VAL_L(wp)); in arm_ccn_pmu_xp_watchpoint_config()
977 source->base + CCN_XP_DT_CMP_VAL_L(wp) + 4); in arm_ccn_pmu_xp_watchpoint_config()
978 writel(cmp_h & 0xffffffff, source->base + CCN_XP_DT_CMP_VAL_H(wp)); in arm_ccn_pmu_xp_watchpoint_config()
980 source->base + CCN_XP_DT_CMP_VAL_H(wp) + 4); in arm_ccn_pmu_xp_watchpoint_config()
983 writel(mask_l & 0xffffffff, source->base + CCN_XP_DT_CMP_MASK_L(wp)); in arm_ccn_pmu_xp_watchpoint_config()
985 source->base + CCN_XP_DT_CMP_MASK_L(wp) + 4); in arm_ccn_pmu_xp_watchpoint_config()
986 writel(mask_h & 0xffffffff, source->base + CCN_XP_DT_CMP_MASK_H(wp)); in arm_ccn_pmu_xp_watchpoint_config()
988 source->base + CCN_XP_DT_CMP_MASK_H(wp) + 4); in arm_ccn_pmu_xp_watchpoint_config()
993 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu); in arm_ccn_pmu_xp_event_config()
994 struct hw_perf_event *hw = &event->hw; in arm_ccn_pmu_xp_event_config()
996 ccn->dt.pmu_counters[hw->idx].source; in arm_ccn_pmu_xp_event_config()
999 hw->event_base = CCN_XP_DT_CONFIG__DT_CFG__XP_PMU_EVENT(hw->config_base); in arm_ccn_pmu_xp_event_config()
1001 id = (CCN_CONFIG_VC(event->attr.config) << 4) | in arm_ccn_pmu_xp_event_config()
1002 (CCN_CONFIG_BUS(event->attr.config) << 3) | in arm_ccn_pmu_xp_event_config()
1003 (CCN_CONFIG_EVENT(event->attr.config) << 0); in arm_ccn_pmu_xp_event_config()
1005 val = readl(source->base + CCN_XP_PMU_EVENT_SEL); in arm_ccn_pmu_xp_event_config()
1007 CCN_XP_PMU_EVENT_SEL__ID__SHIFT(hw->config_base)); in arm_ccn_pmu_xp_event_config()
1008 val |= id << CCN_XP_PMU_EVENT_SEL__ID__SHIFT(hw->config_base); in arm_ccn_pmu_xp_event_config()
1009 writel(val, source->base + CCN_XP_PMU_EVENT_SEL); in arm_ccn_pmu_xp_event_config()
1014 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu); in arm_ccn_pmu_node_event_config()
1015 struct hw_perf_event *hw = &event->hw; in arm_ccn_pmu_node_event_config()
1017 ccn->dt.pmu_counters[hw->idx].source; in arm_ccn_pmu_node_event_config()
1018 u32 type = CCN_CONFIG_TYPE(event->attr.config); in arm_ccn_pmu_node_event_config()
1021 port = arm_ccn_node_to_xp_port(CCN_CONFIG_NODE(event->attr.config)); in arm_ccn_pmu_node_event_config()
1022 hw->event_base = CCN_XP_DT_CONFIG__DT_CFG__DEVICE_PMU_EVENT(port, in arm_ccn_pmu_node_event_config()
1023 hw->config_base); in arm_ccn_pmu_node_event_config()
1040 /* Set the event id for the pre-allocated counter */ in arm_ccn_pmu_node_event_config()
1041 val = readl(source->base + CCN_HNF_PMU_EVENT_SEL); in arm_ccn_pmu_node_event_config()
1043 CCN_HNF_PMU_EVENT_SEL__ID__SHIFT(hw->config_base)); in arm_ccn_pmu_node_event_config()
1044 val |= CCN_CONFIG_EVENT(event->attr.config) << in arm_ccn_pmu_node_event_config()
1045 CCN_HNF_PMU_EVENT_SEL__ID__SHIFT(hw->config_base); in arm_ccn_pmu_node_event_config()
1046 writel(val, source->base + CCN_HNF_PMU_EVENT_SEL); in arm_ccn_pmu_node_event_config()
1051 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu); in arm_ccn_pmu_event_config()
1052 struct hw_perf_event *hw = &event->hw; in arm_ccn_pmu_event_config()
1056 if (hw->idx == CCN_IDX_PMU_CYCLE_COUNTER) in arm_ccn_pmu_event_config()
1059 if (CCN_CONFIG_TYPE(event->attr.config) == CCN_TYPE_XP) in arm_ccn_pmu_event_config()
1060 xp = CCN_CONFIG_XP(event->attr.config); in arm_ccn_pmu_event_config()
1062 xp = arm_ccn_node_to_xp(CCN_CONFIG_NODE(event->attr.config)); in arm_ccn_pmu_event_config()
1064 spin_lock(&ccn->dt.config_lock); in arm_ccn_pmu_event_config()
1066 /* Set the DT bus "distance" register */ in arm_ccn_pmu_event_config()
1067 offset = (hw->idx / 4) * 4; in arm_ccn_pmu_event_config()
1068 val = readl(ccn->dt.base + CCN_DT_ACTIVE_DSM + offset); in arm_ccn_pmu_event_config()
1070 CCN_DT_ACTIVE_DSM__DSM_ID__SHIFT(hw->idx % 4)); in arm_ccn_pmu_event_config()
1071 val |= xp << CCN_DT_ACTIVE_DSM__DSM_ID__SHIFT(hw->idx % 4); in arm_ccn_pmu_event_config()
1072 writel(val, ccn->dt.base + CCN_DT_ACTIVE_DSM + offset); in arm_ccn_pmu_event_config()
1074 if (CCN_CONFIG_TYPE(event->attr.config) == CCN_TYPE_XP) { in arm_ccn_pmu_event_config()
1075 if (CCN_CONFIG_EVENT(event->attr.config) == in arm_ccn_pmu_event_config()
1084 spin_unlock(&ccn->dt.config_lock); in arm_ccn_pmu_event_config()
1089 return bitmap_weight(ccn->dt.pmu_counters_mask, in arm_ccn_pmu_active_counters()
1096 struct hw_perf_event *hw = &event->hw; in arm_ccn_pmu_event_add()
1097 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu); in arm_ccn_pmu_event_add()
1105 * event->cpu (this is the same one as presented in "cpumask" in arm_ccn_pmu_event_add()
1108 if (!ccn->irq && arm_ccn_pmu_active_counters(ccn) == 1) in arm_ccn_pmu_event_add()
1109 hrtimer_start(&ccn->dt.hrtimer, arm_ccn_pmu_timer_period(), in arm_ccn_pmu_event_add()
1114 hw->state = PERF_HES_STOPPED; in arm_ccn_pmu_event_add()
1124 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu); in arm_ccn_pmu_event_del()
1130 if (!ccn->irq && arm_ccn_pmu_active_counters(ccn) == 0) in arm_ccn_pmu_event_del()
1131 hrtimer_cancel(&ccn->dt.hrtimer); in arm_ccn_pmu_event_del()
1143 u32 val = readl(ccn->dt.base + CCN_DT_PMCR); in arm_ccn_pmu_enable()
1145 writel(val, ccn->dt.base + CCN_DT_PMCR); in arm_ccn_pmu_enable()
1152 u32 val = readl(ccn->dt.base + CCN_DT_PMCR); in arm_ccn_pmu_disable()
1154 writel(val, ccn->dt.base + CCN_DT_PMCR); in arm_ccn_pmu_disable()
1157 static irqreturn_t arm_ccn_pmu_overflow_handler(struct arm_ccn_dt *dt) in arm_ccn_pmu_overflow_handler() argument
1159 u32 pmovsr = readl(dt->base + CCN_DT_PMOVSR); in arm_ccn_pmu_overflow_handler()
1165 writel(pmovsr, dt->base + CCN_DT_PMOVSR_CLR); in arm_ccn_pmu_overflow_handler()
1170 struct perf_event *event = dt->pmu_counters[idx].event; in arm_ccn_pmu_overflow_handler()
1187 struct arm_ccn_dt *dt = container_of(hrtimer, struct arm_ccn_dt, in arm_ccn_pmu_timer_handler() local
1192 arm_ccn_pmu_overflow_handler(dt); in arm_ccn_pmu_timer_handler()
1200 static int arm_ccn_pmu_offline_cpu(unsigned int cpu, struct hlist_node *node) in arm_ccn_pmu_offline_cpu() argument
1202 struct arm_ccn_dt *dt = hlist_entry_safe(node, struct arm_ccn_dt, node); in arm_ccn_pmu_offline_cpu() local
1203 struct arm_ccn *ccn = container_of(dt, struct arm_ccn, dt); in arm_ccn_pmu_offline_cpu()
1206 if (cpu != dt->cpu) in arm_ccn_pmu_offline_cpu()
1211 perf_pmu_migrate_context(&dt->pmu, cpu, target); in arm_ccn_pmu_offline_cpu()
1212 dt->cpu = target; in arm_ccn_pmu_offline_cpu()
1213 if (ccn->irq) in arm_ccn_pmu_offline_cpu()
1214 WARN_ON(irq_set_affinity(ccn->irq, cpumask_of(dt->cpu))); in arm_ccn_pmu_offline_cpu()
1226 /* Initialize DT subsystem */ in arm_ccn_pmu_init()
1227 ccn->dt.base = ccn->base + CCN_REGION_SIZE; in arm_ccn_pmu_init()
1228 spin_lock_init(&ccn->dt.config_lock); in arm_ccn_pmu_init()
1229 writel(CCN_DT_PMOVSR_CLR__MASK, ccn->dt.base + CCN_DT_PMOVSR_CLR); in arm_ccn_pmu_init()
1230 writel(CCN_DT_CTL__DT_EN, ccn->dt.base + CCN_DT_CTL); in arm_ccn_pmu_init()
1232 ccn->dt.base + CCN_DT_PMCR); in arm_ccn_pmu_init()
1233 writel(0x1, ccn->dt.base + CCN_DT_PMSR_CLR); in arm_ccn_pmu_init()
1234 for (i = 0; i < ccn->num_xps; i++) { in arm_ccn_pmu_init()
1235 writel(0, ccn->xp[i].base + CCN_XP_DT_CONFIG); in arm_ccn_pmu_init()
1241 ccn->xp[i].base + CCN_XP_DT_CONTROL); in arm_ccn_pmu_init()
1243 ccn->dt.cmp_mask[CCN_IDX_MASK_ANY].l = ~0; in arm_ccn_pmu_init()
1244 ccn->dt.cmp_mask[CCN_IDX_MASK_ANY].h = ~0; in arm_ccn_pmu_init()
1245 ccn->dt.cmp_mask[CCN_IDX_MASK_EXACT].l = 0; in arm_ccn_pmu_init()
1246 ccn->dt.cmp_mask[CCN_IDX_MASK_EXACT].h = 0; in arm_ccn_pmu_init()
1247 ccn->dt.cmp_mask[CCN_IDX_MASK_ORDER].l = ~0; in arm_ccn_pmu_init()
1248 ccn->dt.cmp_mask[CCN_IDX_MASK_ORDER].h = ~(0x1 << 15); in arm_ccn_pmu_init()
1249 ccn->dt.cmp_mask[CCN_IDX_MASK_OPCODE].l = ~0; in arm_ccn_pmu_init()
1250 ccn->dt.cmp_mask[CCN_IDX_MASK_OPCODE].h = ~(0x1f << 9); in arm_ccn_pmu_init()
1253 ccn->dt.id = ida_alloc(&arm_ccn_pmu_ida, GFP_KERNEL); in arm_ccn_pmu_init()
1254 if (ccn->dt.id == 0) { in arm_ccn_pmu_init()
1257 name = devm_kasprintf(ccn->dev, GFP_KERNEL, "ccn_%d", in arm_ccn_pmu_init()
1258 ccn->dt.id); in arm_ccn_pmu_init()
1260 err = -ENOMEM; in arm_ccn_pmu_init()
1266 ccn->dt.pmu = (struct pmu) { in arm_ccn_pmu_init()
1282 if (!ccn->irq) { in arm_ccn_pmu_init()
1283 dev_info(ccn->dev, "No access to interrupts, using timer.\n"); in arm_ccn_pmu_init()
1284 hrtimer_init(&ccn->dt.hrtimer, CLOCK_MONOTONIC, in arm_ccn_pmu_init()
1286 ccn->dt.hrtimer.function = arm_ccn_pmu_timer_handler; in arm_ccn_pmu_init()
1290 ccn->dt.cpu = raw_smp_processor_id(); in arm_ccn_pmu_init()
1293 if (ccn->irq) { in arm_ccn_pmu_init()
1294 err = irq_set_affinity(ccn->irq, cpumask_of(ccn->dt.cpu)); in arm_ccn_pmu_init()
1296 dev_err(ccn->dev, "Failed to set interrupt affinity!\n"); in arm_ccn_pmu_init()
1302 &ccn->dt.node); in arm_ccn_pmu_init()
1304 err = perf_pmu_register(&ccn->dt.pmu, name, -1); in arm_ccn_pmu_init()
1312 &ccn->dt.node); in arm_ccn_pmu_init()
1315 ida_free(&arm_ccn_pmu_ida, ccn->dt.id); in arm_ccn_pmu_init()
1316 for (i = 0; i < ccn->num_xps; i++) in arm_ccn_pmu_init()
1317 writel(0, ccn->xp[i].base + CCN_XP_DT_CONTROL); in arm_ccn_pmu_init()
1318 writel(0, ccn->dt.base + CCN_DT_PMCR); in arm_ccn_pmu_init()
1327 &ccn->dt.node); in arm_ccn_pmu_cleanup()
1328 for (i = 0; i < ccn->num_xps; i++) in arm_ccn_pmu_cleanup()
1329 writel(0, ccn->xp[i].base + CCN_XP_DT_CONTROL); in arm_ccn_pmu_cleanup()
1330 writel(0, ccn->dt.base + CCN_DT_PMCR); in arm_ccn_pmu_cleanup()
1331 perf_pmu_unregister(&ccn->dt.pmu); in arm_ccn_pmu_cleanup()
1332 ida_free(&arm_ccn_pmu_ida, ccn->dt.id); in arm_ccn_pmu_cleanup()
1346 val = readl(ccn->base + CCN_MN_OLY_COMP_LIST_63_0 + in arm_ccn_for_each_valid_region()
1351 base = ccn->base + region * CCN_REGION_SIZE; in arm_ccn_for_each_valid_region()
1370 if (type == CCN_TYPE_XP && id >= ccn->num_xps) in arm_ccn_get_nodes_num()
1371 ccn->num_xps = id + 1; in arm_ccn_get_nodes_num()
1372 else if (id >= ccn->num_nodes) in arm_ccn_get_nodes_num()
1373 ccn->num_nodes = id + 1; in arm_ccn_get_nodes_num()
1383 dev_dbg(ccn->dev, "Region %d: id=%u, type=0x%02x\n", region, id, type); in arm_ccn_init_nodes()
1387 ccn->mn_id = id; in arm_ccn_init_nodes()
1392 component = &ccn->xp[id]; in arm_ccn_init_nodes()
1395 ccn->sbsx_present = 1; in arm_ccn_init_nodes()
1396 component = &ccn->node[id]; in arm_ccn_init_nodes()
1399 ccn->sbas_present = 1; in arm_ccn_init_nodes()
1402 component = &ccn->node[id]; in arm_ccn_init_nodes()
1406 component->base = base; in arm_ccn_init_nodes()
1407 component->type = type; in arm_ccn_init_nodes()
1417 dev_err(ccn->dev, "Error reported in %08x%08x%08x%08x%08x%08x.\n", in arm_ccn_error_handler()
1420 dev_err(ccn->dev, "Disabling interrupt generation for all errors.\n"); in arm_ccn_error_handler()
1422 ccn->base + CCN_MN_ERRINT_STATUS); in arm_ccn_error_handler()
1437 err_or = err_sig_val[0] = readl(ccn->base + CCN_MN_ERR_SIG_VAL_63_0); in arm_ccn_irq_handler()
1440 res = arm_ccn_pmu_overflow_handler(&ccn->dt); in arm_ccn_irq_handler()
1445 err_sig_val[i] = readl(ccn->base + in arm_ccn_irq_handler()
1454 ccn->base + CCN_MN_ERRINT_STATUS); in arm_ccn_irq_handler()
1466 ccn = devm_kzalloc(&pdev->dev, sizeof(*ccn), GFP_KERNEL); in arm_ccn_probe()
1468 return -ENOMEM; in arm_ccn_probe()
1469 ccn->dev = &pdev->dev; in arm_ccn_probe()
1472 ccn->base = devm_platform_ioremap_resource(pdev, 0); in arm_ccn_probe()
1473 if (IS_ERR(ccn->base)) in arm_ccn_probe()
1474 return PTR_ERR(ccn->base); in arm_ccn_probe()
1482 ccn->base + CCN_MN_ERRINT_STATUS); in arm_ccn_probe()
1483 if (readl(ccn->base + CCN_MN_ERRINT_STATUS) & in arm_ccn_probe()
1487 ccn->base + CCN_MN_ERRINT_STATUS); in arm_ccn_probe()
1488 err = devm_request_irq(ccn->dev, irq, arm_ccn_irq_handler, in arm_ccn_probe()
1490 dev_name(ccn->dev), ccn); in arm_ccn_probe()
1494 ccn->irq = irq; in arm_ccn_probe()
1504 ccn->node = devm_kcalloc(ccn->dev, ccn->num_nodes, sizeof(*ccn->node), in arm_ccn_probe()
1506 ccn->xp = devm_kcalloc(ccn->dev, ccn->num_xps, sizeof(*ccn->node), in arm_ccn_probe()
1508 if (!ccn->node || !ccn->xp) in arm_ccn_probe()
1509 return -ENOMEM; in arm_ccn_probe()
1528 { .compatible = "arm,ccn-502", },
1529 { .compatible = "arm,ccn-504", },
1530 { .compatible = "arm,ccn-512", },
1537 .name = "arm-ccn",