Lines Matching full:pmu
10 tristate "ARM CCI PMU driver"
14 Support for PMU events monitoring on the ARM CCI (Cache Coherent
41 PMU (perf) driver supporting the ARM CCN (Cache Coherent Network)
45 tristate "Arm CMN-600 PMU support"
48 Support for PMU events monitoring on the Arm CMN-600 Coherent Mesh
53 bool "ARM PMU framework"
61 bool "RISC-V PMU framework"
65 systems. This provides the core PMU framework that abstracts common
66 PMU functionalities in a core library so that different PMU drivers
71 bool "RISC-V legacy PMU implementation"
81 bool "RISC-V PMU based on SBI PMU extension"
85 using SBI PMU extension on RISC-V based systems. This option provides
104 tristate "ARM DynamIQ Shared Unit (DSU) PMU"
109 system, control logic. The PMU allows counting various events related
121 bool "Qualcomm Technologies L2-cache PMU"
125 Provides support for the L2 cache performance monitor unit (PMU)
127 Adds the L2 cache PMU into the perf events subsystem for
131 bool "Qualcomm Technologies L3-cache PMU"
135 Provides support for the L3 cache performance monitor unit (PMU)
137 Adds the L3 cache PMU into the perf events subsystem for
141 tristate "Cavium ThunderX2 SoC PMU UNCORE"
147 The SoC has PMU support in its L3 cache controller (L3C) and
152 bool "APM X-Gene SoC PMU"
166 tristate "Enable PMU support for the ARM DMC-620 memory controller"
169 Support for PMU events monitoring on the ARM DMC-620 memory
173 tristate "Marvell CN10K LLC-TAD PMU"
180 bool "Apple M1 CPU PMU support"
187 tristate "Alibaba T-Head Yitian 710 DDR Sub-system Driveway PMU driver"
190 Support for Driveway PMU events monitoring on Yitian 710 DDR
196 tristate "Enable MARVELL CN10K DRAM Subsystem(DSS) PMU Support"