44 	MRPC_IDLE = 0,
171 		memset(stdev->dma_mrpc->data, 0xFF, SWITCHTEC_MRPC_PAYLOAD_SIZE);  in mrpc_cmd_submit()
199 	return 0;  in mrpc_queue_cmd()
213 	stdev->mrpc_busy = 0;  in mrpc_cleanup_cmd()
239 	stuser->return_code = 0;  in mrpc_complete_cmd()
249 	if (stuser->return_code != 0)  in mrpc_complete_cmd()
354 	buf[len + 1] = 0;  in io_string_show()
356 	for (i = len - 1; i > 0; i--) {  in io_string_show()
360 		buf[i + 1] = 0;  in io_string_show()
481 	return 0;  in switchtec_dev_open()
490 	return 0;  in switchtec_dev_release()
503 	return 0;  in lock_mutex_and_test_alive()
588 		if (rc < 0)  in switchtec_dev_read()
639 	__poll_t ret = 0;  in switchtec_dev_poll()
661 	struct switchtec_ioctl_flash_info info = {0};  in ioctl_flash_info()
677 	return 0;  in ioctl_flash_info()
724 		set_fw_info_part(info, &fi->vendor[0]);  in flash_part_info_gen3()
754 	return 0;  in flash_part_info_gen3()
831 		set_fw_info_part(info, &fi->vendor[0]);  in flash_part_info_gen4()
858 	return 0;  in flash_part_info_gen4()
865 	struct switchtec_ioctl_flash_part_info info = {0};  in ioctl_flash_part_info()
885 	return 0;  in ioctl_flash_part_info()
896 	int ret = 0;  in ioctl_event_summary()
906 	for (i = 0; i < stdev->partition_count; i++) {  in ioctl_event_summary()
911 	for (i = 0; i < stdev->pff_csr_count; i++) {  in ioctl_event_summary()
997 	if (event_id < 0 || event_id >= SWITCHTEC_IOCTL_MAX_EVENTS)  in event_hdr_addr()
1005 		else if (index < 0 || index >= stdev->partition_count)  in event_hdr_addr()
1008 		if (index < 0 || index >= stdev->pff_csr_count)  in event_hdr_addr()
1030 	for (i = 0; i < ARRAY_SIZE(ctl->data); i++)  in event_ctl()
1034 	ctl->count = (hdr >> 5) & 0xFF;  in event_ctl()
1058 	ctl->flags = 0;  in event_ctl()
1068 	return 0;  in event_ctl()
1099 		for (ctl.index = 0; ctl.index < nr_idxs; ctl.index++) {  in ioctl_event_ctl()
1102 			if (ret < 0 && ret != -EOPNOTSUPP)  in ioctl_event_ctl()
1107 		if (ret < 0)  in ioctl_event_ctl()
1114 	return 0;  in ioctl_event_ctl()
1129 	for (part = 0; part < stdev->partition_count; part++) {  in ioctl_pff_to_port()
1135 			p.port = 0;  in ioctl_pff_to_port()
1139 		reg = ioread32(&pcfg->vep_pff_inst_id) & 0xFF;  in ioctl_pff_to_port()
1145 		for (i = 0; i < ARRAY_SIZE(pcfg->dsp_pff_inst_id); i++) {  in ioctl_pff_to_port()
1161 	return 0;  in ioctl_pff_to_port()
1181 	case 0:  in ioctl_port_to_pff()
1185 		p.pff = ioread32(&pcfg->vep_pff_inst_id) & 0xFF;  in ioctl_port_to_pff()
1199 	return 0;  in ioctl_port_to_pff()
1273 	int occurred = 0;  in check_link_state_events()
1275 	for (idx = 0; idx < stdev->pff_csr_count; idx++) {  in check_link_state_events()
1278 		count = (reg >> 5) & 0xFF;  in check_link_state_events()
1294 	for (idx = 0; idx < stdev->pff_csr_count; idx++) {  in enable_link_state_events()
1313 		iowrite32(0, &stdev->mmio_mrpc->dma_en);  in stdev_release()
1315 		writeq(0, &stdev->mmio_mrpc->dma_addr);  in stdev_release()
1365 	stdev->mrpc_busy = 0;  in stdev_create()
1370 	atomic_set(&stdev->event_cnt, 0);  in stdev_create()
1380 	if (minor < 0) {  in stdev_create()
1409 		return 0;  in mask_event()
1412 		return 0;  in mask_event()
1424 	int count = 0;  in mask_all_events()
1427 		for (idx = 0; idx < stdev->partition_count; idx++)  in mask_all_events()
1430 		for (idx = 0; idx < stdev->pff_csr_count; idx++) {  in mask_all_events()
1437 		count += mask_event(stdev, eid, 0);  in mask_all_events()
1448 	int eid, event_count = 0;  in switchtec_event_isr()
1460 	for (eid = 0; eid < SWITCHTEC_IOCTL_MAX_EVENTS; eid++) {  in switchtec_event_isr()
1507 	if (nvecs < 0)  in switchtec_init_isr()
1511 	if (event_irq < 0 || event_irq >= nvecs)  in switchtec_init_isr()
1515 	if (event_irq < 0)  in switchtec_init_isr()
1519 				switchtec_event_isr, 0,  in switchtec_init_isr()
1529 	if (dma_mrpc_irq < 0 || dma_mrpc_irq >= nvecs)  in switchtec_init_isr()
1533 	if (dma_mrpc_irq < 0)  in switchtec_init_isr()
1537 				switchtec_dma_mrpc_isr, 0,  in switchtec_init_isr()
1549 	for (i = 0; i < SWITCHTEC_MAX_PFF_CSR; i++) {  in init_pff()
1561 	reg = ioread32(&pcfg->vep_pff_inst_id) & 0xFF;  in init_pff()
1565 	for (i = 0; i < ARRAY_SIZE(pcfg->dsp_pff_inst_id); i++) {  in init_pff()
1590 	res_start = pci_resource_start(pdev, 0);  in switchtec_init_pci()
1591 	res_len = pci_resource_len(pdev, 0);  in switchtec_init_pci()
1635 		return 0;  in switchtec_init_pci()
1637 	if (ioread32(&stdev->mmio_mrpc->dma_ver) == 0)  in switchtec_init_pci()
1638 		return 0;  in switchtec_init_pci()
1647 	return 0;  in switchtec_init_pci()
1689 	return 0;  in switchtec_pci_probe()
1719 		.class_mask = 0xFFFFFFFF, \
1728 		.class_mask = 0xFFFFFFFF, \
1733 	SWITCHTEC_PCI_DEVICE(0x8531, SWITCHTEC_GEN3),  //PFX 24xG3
1734 	SWITCHTEC_PCI_DEVICE(0x8532, SWITCHTEC_GEN3),  //PFX 32xG3
1735 	SWITCHTEC_PCI_DEVICE(0x8533, SWITCHTEC_GEN3),  //PFX 48xG3
1736 	SWITCHTEC_PCI_DEVICE(0x8534, SWITCHTEC_GEN3),  //PFX 64xG3
1737 	SWITCHTEC_PCI_DEVICE(0x8535, SWITCHTEC_GEN3),  //PFX 80xG3
1738 	SWITCHTEC_PCI_DEVICE(0x8536, SWITCHTEC_GEN3),  //PFX 96xG3
1739 	SWITCHTEC_PCI_DEVICE(0x8541, SWITCHTEC_GEN3),  //PSX 24xG3
1740 	SWITCHTEC_PCI_DEVICE(0x8542, SWITCHTEC_GEN3),  //PSX 32xG3
1741 	SWITCHTEC_PCI_DEVICE(0x8543, SWITCHTEC_GEN3),  //PSX 48xG3
1742 	SWITCHTEC_PCI_DEVICE(0x8544, SWITCHTEC_GEN3),  //PSX 64xG3
1743 	SWITCHTEC_PCI_DEVICE(0x8545, SWITCHTEC_GEN3),  //PSX 80xG3
1744 	SWITCHTEC_PCI_DEVICE(0x8546, SWITCHTEC_GEN3),  //PSX 96xG3
1745 	SWITCHTEC_PCI_DEVICE(0x8551, SWITCHTEC_GEN3),  //PAX 24XG3
1746 	SWITCHTEC_PCI_DEVICE(0x8552, SWITCHTEC_GEN3),  //PAX 32XG3
1747 	SWITCHTEC_PCI_DEVICE(0x8553, SWITCHTEC_GEN3),  //PAX 48XG3
1748 	SWITCHTEC_PCI_DEVICE(0x8554, SWITCHTEC_GEN3),  //PAX 64XG3
1749 	SWITCHTEC_PCI_DEVICE(0x8555, SWITCHTEC_GEN3),  //PAX 80XG3
1750 	SWITCHTEC_PCI_DEVICE(0x8556, SWITCHTEC_GEN3),  //PAX 96XG3
1751 	SWITCHTEC_PCI_DEVICE(0x8561, SWITCHTEC_GEN3),  //PFXL 24XG3
1752 	SWITCHTEC_PCI_DEVICE(0x8562, SWITCHTEC_GEN3),  //PFXL 32XG3
1753 	SWITCHTEC_PCI_DEVICE(0x8563, SWITCHTEC_GEN3),  //PFXL 48XG3
1754 	SWITCHTEC_PCI_DEVICE(0x8564, SWITCHTEC_GEN3),  //PFXL 64XG3
1755 	SWITCHTEC_PCI_DEVICE(0x8565, SWITCHTEC_GEN3),  //PFXL 80XG3
1756 	SWITCHTEC_PCI_DEVICE(0x8566, SWITCHTEC_GEN3),  //PFXL 96XG3
1757 	SWITCHTEC_PCI_DEVICE(0x8571, SWITCHTEC_GEN3),  //PFXI 24XG3
1758 	SWITCHTEC_PCI_DEVICE(0x8572, SWITCHTEC_GEN3),  //PFXI 32XG3
1759 	SWITCHTEC_PCI_DEVICE(0x8573, SWITCHTEC_GEN3),  //PFXI 48XG3
1760 	SWITCHTEC_PCI_DEVICE(0x8574, SWITCHTEC_GEN3),  //PFXI 64XG3
1761 	SWITCHTEC_PCI_DEVICE(0x8575, SWITCHTEC_GEN3),  //PFXI 80XG3
1762 	SWITCHTEC_PCI_DEVICE(0x8576, SWITCHTEC_GEN3),  //PFXI 96XG3
1763 	SWITCHTEC_PCI_DEVICE(0x4000, SWITCHTEC_GEN4),  //PFX 100XG4
1764 	SWITCHTEC_PCI_DEVICE(0x4084, SWITCHTEC_GEN4),  //PFX 84XG4
1765 	SWITCHTEC_PCI_DEVICE(0x4068, SWITCHTEC_GEN4),  //PFX 68XG4
1766 	SWITCHTEC_PCI_DEVICE(0x4052, SWITCHTEC_GEN4),  //PFX 52XG4
1767 	SWITCHTEC_PCI_DEVICE(0x4036, SWITCHTEC_GEN4),  //PFX 36XG4
1768 	SWITCHTEC_PCI_DEVICE(0x4028, SWITCHTEC_GEN4),  //PFX 28XG4
1769 	SWITCHTEC_PCI_DEVICE(0x4100, SWITCHTEC_GEN4),  //PSX 100XG4
1770 	SWITCHTEC_PCI_DEVICE(0x4184, SWITCHTEC_GEN4),  //PSX 84XG4
1771 	SWITCHTEC_PCI_DEVICE(0x4168, SWITCHTEC_GEN4),  //PSX 68XG4
1772 	SWITCHTEC_PCI_DEVICE(0x4152, SWITCHTEC_GEN4),  //PSX 52XG4
1773 	SWITCHTEC_PCI_DEVICE(0x4136, SWITCHTEC_GEN4),  //PSX 36XG4
1774 	SWITCHTEC_PCI_DEVICE(0x4128, SWITCHTEC_GEN4),  //PSX 28XG4
1775 	SWITCHTEC_PCI_DEVICE(0x4200, SWITCHTEC_GEN4),  //PAX 100XG4
1776 	SWITCHTEC_PCI_DEVICE(0x4284, SWITCHTEC_GEN4),  //PAX 84XG4
1777 	SWITCHTEC_PCI_DEVICE(0x4268, SWITCHTEC_GEN4),  //PAX 68XG4
1778 	SWITCHTEC_PCI_DEVICE(0x4252, SWITCHTEC_GEN4),  //PAX 52XG4
1779 	SWITCHTEC_PCI_DEVICE(0x4236, SWITCHTEC_GEN4),  //PAX 36XG4
1780 	SWITCHTEC_PCI_DEVICE(0x4228, SWITCHTEC_GEN4),  //PAX 28XG4
1781 	SWITCHTEC_PCI_DEVICE(0x4352, SWITCHTEC_GEN4),  //PFXA 52XG4
1782 	SWITCHTEC_PCI_DEVICE(0x4336, SWITCHTEC_GEN4),  //PFXA 36XG4
1783 	SWITCHTEC_PCI_DEVICE(0x4328, SWITCHTEC_GEN4),  //PFXA 28XG4
1784 	SWITCHTEC_PCI_DEVICE(0x4452, SWITCHTEC_GEN4),  //PSXA 52XG4
1785 	SWITCHTEC_PCI_DEVICE(0x4436, SWITCHTEC_GEN4),  //PSXA 36XG4
1786 	SWITCHTEC_PCI_DEVICE(0x4428, SWITCHTEC_GEN4),  //PSXA 28XG4
1787 	SWITCHTEC_PCI_DEVICE(0x4552, SWITCHTEC_GEN4),  //PAXA 52XG4
1788 	SWITCHTEC_PCI_DEVICE(0x4536, SWITCHTEC_GEN4),  //PAXA 36XG4
1789 	SWITCHTEC_PCI_DEVICE(0x4528, SWITCHTEC_GEN4),  //PAXA 28XG4
1790 	{0}
1805 	rc = alloc_chrdev_region(&switchtec_devt, 0, max_devices,  in switchtec_init()
1822 	return 0;  in switchtec_init()