Lines Matching +full:iproc +full:- +full:msi
1 // SPDX-License-Identifier: GPL-2.0
3 * This file contains work-arounds for many known PCI hardware bugs.
5 * should be handled in arch-specific code.
20 #include <linux/isa-dma.h> /* isa_dma_bridge_buggy */
64 if ((f->class == (u32) (dev->class >> f->class_shift) || in pci_do_fixups()
65 f->class == (u32) PCI_ANY_ID) && in pci_do_fixups()
66 (f->vendor == dev->vendor || in pci_do_fixups()
67 f->vendor == (u16) PCI_ANY_ID) && in pci_do_fixups()
68 (f->device == dev->device || in pci_do_fixups()
69 f->device == (u16) PCI_ANY_ID)) { in pci_do_fixups()
72 hook = offset_to_ptr(&f->hook_offset); in pci_do_fixups()
74 hook = f->hook; in pci_do_fixups()
200 * key system devices. For devices that need to have mmio decoding always-on,
201 * we need to set the dev->mmio_always_on bit.
205 dev->mmio_always_on = 1; in quirk_mmio_always_on()
246 * contacts at VIA ask them for me please -- Alan
291 /* Chipsets where PCI->PCI transfers vanish or hang */
329 * Made according to a Windows driver-based patch by George E. Breese;
331 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for the info on
350 * 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; in quirk_vialatency()
354 if (p->revision < 0x40 || p->revision > 0x42) in quirk_vialatency()
362 if (p->revision < 0x10 || p->revision > 0x12) in quirk_vialatency()
454 dev->cfg_size = 0xA0; in quirk_citrine()
464 dev->cfg_size = 0x600; in quirk_nfp6000()
477 struct resource *r = &dev->resource[i]; in quirk_extend_bar_to_page()
479 if (r->flags & IORESOURCE_MEM && resource_size(r) < PAGE_SIZE) { in quirk_extend_bar_to_page()
480 r->end = PAGE_SIZE - 1; in quirk_extend_bar_to_page()
481 r->start = 0; in quirk_extend_bar_to_page()
482 r->flags |= IORESOURCE_UNSET; in quirk_extend_bar_to_page()
492 * If it's needed, re-allocate the region.
496 struct resource *r = &dev->resource[0]; in quirk_s3_64M()
498 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) { in quirk_s3_64M()
499 r->flags |= IORESOURCE_UNSET; in quirk_s3_64M()
500 r->start = 0; in quirk_s3_64M()
501 r->end = 0x3ffffff; in quirk_s3_64M()
512 struct resource *res = dev->resource + pos; in quirk_io()
519 res->name = pci_name(dev); in quirk_io()
520 res->flags = region & ~PCI_BASE_ADDRESS_IO_MASK; in quirk_io()
521 res->flags |= in quirk_io()
523 region &= ~(size - 1); in quirk_io()
527 bus_region.end = region + size - 1; in quirk_io()
528 pcibios_bus_to_resource(dev->bus, res, &bus_region); in quirk_io()
540 * CS553x's ISA PCI BARs may also be read-only (ref:
541 * https://bugzilla.kernel.org/show_bug.cgi?id=85991 - Comment #4 forward).
562 struct resource *res = dev->resource + nr; in quirk_io_region()
565 region &= ~(size - 1); in quirk_io_region()
570 res->name = pci_name(dev); in quirk_io_region()
571 res->flags = IORESOURCE_IO; in quirk_io_region()
575 bus_region.end = region + size - 1; in quirk_io_region()
576 pcibios_bus_to_resource(dev->bus, res, &bus_region); in quirk_io_region()
584 * between 0x3b0->0x3bb or read 0x3d3
608 u32 class = pdev->class; in quirk_amd_nl_class()
611 pdev->class = PCI_CLASS_SERIAL_USB_DEVICE; in quirk_amd_nl_class()
612 …pci_info(pdev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhc… in quirk_amd_nl_class()
613 class, pdev->class); in quirk_amd_nl_class()
621 * devices should use dwc3-haps driver. Change these devices' class code to
622 * PCI_CLASS_SERIAL_USB_DEVICE to prevent the xhci-pci driver from claiming
627 u32 class = pdev->class; in quirk_synopsys_haps()
629 switch (pdev->device) { in quirk_synopsys_haps()
633 pdev->class = PCI_CLASS_SERIAL_USB_DEVICE; in quirk_synopsys_haps()
634 …pci_info(pdev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhc… in quirk_synopsys_haps()
635 class, pdev->class); in quirk_synopsys_haps()
682 base &= -size; in piix4_io_quirk()
683 pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1); in piix4_io_quirk()
708 base &= -size; in piix4_mem_quirk()
709 pci_info(dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1); in piix4_mem_quirk()
761 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
835 base &= ~(size-1); in ich6_lpc_generic_decode()
841 pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base+size-1); in ich6_lpc_generic_decode()
849 /* ICH6-specific generic IO decode */ in quirk_ich6_lpc()
868 /* IO base in bits 15:2, mask in bits 23:18, both are dword-based */ in ich7_lpc_generic_decode()
880 /* ICH7-10 has the same common LPC generic IO decode registers */
912 if (dev->revision & 0x10) in quirk_vt82c586_acpi()
929 "vt82c686 HW-mon"); in quirk_vt82c686_acpi()
948 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast
949 * back-to-back: Disable fast back-to-back on the secondary bus segment
956 pci_warn(dev, "TI XIO2000a quirk detected; secondary bus fast back-to-back transfers disabled\n"); in quirk_xio2000a()
957 list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) { in quirk_xio2000a()
971 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
974 * TODO: When we have device-specific interrupt routers, this code will go
984 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */ in quirk_via_ioapic()
996 * VIA 8237: Some BIOSes don't set the 'Bypass APIC De-Assert Message' Bit.
1008 pci_info(dev, "Bypassing VIA 8237 APIC De-Assert Message\n"); in quirk_via_vt8237_bypass_apic_deassert()
1016 * The AMD IO-APIC can hang the box when an APIC IRQ is masked.
1026 if (dev->revision >= 0x02) { in quirk_amd_ioapic()
1038 /* Fix for improper SR-IOV configuration on Cavium cn88xx RNM device */ in quirk_cavium_sriov_rnm_link()
1039 if (dev->subsystem_device == 0xa118) in quirk_cavium_sriov_rnm_link()
1040 dev->sriov->link = dev->devfn; in quirk_cavium_sriov_rnm_link()
1047 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
1051 if (dev->subordinate && dev->revision <= 0x12) { in quirk_amd_8131_mmrbc()
1052 pci_info(dev, "AMD8131 rev %x detected; disabling PCI-X MMRBC\n", in quirk_amd_8131_mmrbc()
1053 dev->revision); in quirk_amd_8131_mmrbc()
1054 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC; in quirk_amd_8131_mmrbc()
1064 * -jgarzik
1074 d->irq = irq; in quirk_via_acpi()
1080 static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18;
1085 switch (dev->device) { in quirk_via_bridge()
1092 via_vlink_dev_lo = PCI_SLOT(dev->devfn); in quirk_via_bridge()
1093 via_vlink_dev_hi = PCI_SLOT(dev->devfn); in quirk_via_bridge()
1120 * quirk_via_vlink - VIA VLink IRQ number update
1135 if (via_vlink_dev_lo == -1) in quirk_via_vlink()
1138 new_irq = dev->irq; in quirk_via_vlink()
1145 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi || in quirk_via_vlink()
1146 PCI_SLOT(dev->devfn) < via_vlink_dev_lo) in quirk_via_vlink()
1171 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device); in quirk_vt82c598_id()
1214 * DreamWorks-provided workaround for Dunord I-3000 problem
1222 struct resource *r = &dev->resource[1]; in quirk_dunord()
1224 r->flags |= IORESOURCE_UNSET; in quirk_dunord()
1225 r->start = 0; in quirk_dunord()
1226 r->end = 0xffffff; in quirk_dunord()
1231 * i82380FB mobile docking controller: its PCI-to-PCI bridge is subtractive
1233 * Unfortunately, the ProgIf value is wrong - 0x80 instead of 0x01.
1237 dev->transparent = 1; in quirk_transparent_bridge()
1272 if (pdev->revision != 0x04) /* Only C0 requires this */ in quirk_disable_pxb()
1286 /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */ in quirk_amd_ide_mode()
1297 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI; in quirk_amd_ide_mode()
1317 pdev->class &= ~5; in quirk_svwks_csb5ide()
1324 /* Intel 82801CAM ICH3-M datasheet says IDE modes must be the same */
1334 pdev->class &= ~5; in quirk_ide_samemode()
1343 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3; in quirk_no_ata_d3()
1359 * This was originally an Alpha-specific thing, but it really fits here.
1360 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
1364 dev->class = PCI_CLASS_BRIDGE_EISA << 8; in quirk_eisa_bridge()
1377 * becomes necessary to do this tweak in two steps -- the chosen trigger
1378 * is either the Host bridge (preferred) or on-board VGA controller.
1391 * the DSDT and double-check that there is no code accessing the SMBus.
1397 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { in asus_hides_smbus_hostbridge()
1398 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB) in asus_hides_smbus_hostbridge()
1399 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1400 case 0x8025: /* P4B-LX */ in asus_hides_smbus_hostbridge()
1406 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) in asus_hides_smbus_hostbridge()
1407 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1408 case 0x80b1: /* P4GE-V */ in asus_hides_smbus_hostbridge()
1410 case 0x8093: /* P4B533-V */ in asus_hides_smbus_hostbridge()
1413 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB) in asus_hides_smbus_hostbridge()
1414 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1418 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0) in asus_hides_smbus_hostbridge()
1419 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1423 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH) in asus_hides_smbus_hostbridge()
1424 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1425 case 0x80c9: /* PU-DLS */ in asus_hides_smbus_hostbridge()
1428 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB) in asus_hides_smbus_hostbridge()
1429 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1435 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) in asus_hides_smbus_hostbridge()
1436 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1441 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) in asus_hides_smbus_hostbridge()
1442 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1443 case 0x80f2: /* P4P800-X */ in asus_hides_smbus_hostbridge()
1446 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB) in asus_hides_smbus_hostbridge()
1447 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1452 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) { in asus_hides_smbus_hostbridge()
1453 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) in asus_hides_smbus_hostbridge()
1454 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1459 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) in asus_hides_smbus_hostbridge()
1460 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1466 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB) in asus_hides_smbus_hostbridge()
1467 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1471 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) { in asus_hides_smbus_hostbridge()
1472 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) in asus_hides_smbus_hostbridge()
1473 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1477 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) { in asus_hides_smbus_hostbridge()
1478 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) in asus_hides_smbus_hostbridge()
1479 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1483 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3) in asus_hides_smbus_hostbridge()
1484 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1485 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */ in asus_hides_smbus_hostbridge()
1488 * its on-board VGA controller */ in asus_hides_smbus_hostbridge()
1491 else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2) in asus_hides_smbus_hostbridge()
1492 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1497 * subvendor/subdevice IDs and on-board VGA in asus_hides_smbus_hostbridge()
1503 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC) in asus_hides_smbus_hostbridge()
1504 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1508 * its on-board VGA controller */ in asus_hides_smbus_hostbridge()
1660 dev->device = devid; in quirk_sis_503()
1670 * -- bjd
1677 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { in asus_hides_ac97_lpc()
1678 if (dev->device == PCI_DEVICE_ID_VIA_8237) in asus_hides_ac97_lpc()
1711 if (PCI_FUNC(pdev->devfn)) in quirk_jmicron_ata()
1717 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */ in quirk_jmicron_ata()
1720 switch (pdev->device) { in quirk_jmicron_ata()
1752 pdev->hdr_type = hdr & 0x7f; in quirk_jmicron_ata()
1753 pdev->multifunction = !!(hdr & 0x80); in quirk_jmicron_ata()
1756 pdev->class = class >> 8; in quirk_jmicron_ata()
1781 if (dev->multifunction) { in quirk_jmicron_async_suspend()
1782 device_disable_async_suspend(&dev->dev); in quirk_jmicron_async_suspend()
1783 pci_info(dev, "async suspend disabled to avoid multi-function power-on ordering issue\n"); in quirk_jmicron_async_suspend()
1796 if ((pdev->class >> 8) != 0xff00) in quirk_alder_ioapic()
1800 * The first BAR is the location of the IO-APIC... we must in quirk_alder_ioapic()
1805 insert_resource(&iomem_resource, &pdev->resource[0]); in quirk_alder_ioapic()
1812 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i])); in quirk_alder_ioapic()
1819 pci_info(dev, "avoiding MSI to work around a hardware defect\n"); in quirk_no_msi()
1820 dev->no_msi = 1; in quirk_no_msi()
1831 pdev->no_msi = 1; in quirk_pcie_mch()
1842 * SMMU stall feature, by setting dma-can-stall for ACPI platforms.
1845 * break the PCI requirement for free-flowing writes and may lead to
1847 * be fault-tolerant, so there's no ACPI binding to describe anything else,
1854 PROPERTY_ENTRY_BOOL("dma-can-stall"), in quirk_huawei_pcie_sva()
1858 if (pdev->revision != 0x21 && pdev->revision != 0x30) in quirk_huawei_pcie_sva()
1861 pdev->pasid_no_tlp = 1; in quirk_huawei_pcie_sva()
1864 * Set the dma-can-stall property on ACPI platforms. Device tree in quirk_huawei_pcie_sva()
1867 if (!pdev->dev.of_node && in quirk_huawei_pcie_sva()
1868 device_create_managed_software_node(&pdev->dev, properties, NULL)) in quirk_huawei_pcie_sva()
1879 * It's possible for the MSI to get corrupted if SHPC and ACPI are used
1880 * together on certain PXH-based systems.
1884 dev->no_msi = 1; in quirk_pcie_pxh()
1885 pci_warn(dev, "PXH quirk detected; SHPC device MSI disabled\n"); in quirk_pcie_pxh()
1900 dev->no_d1d2 = 1; in quirk_intel_pcie_pm()
1926 if (dev->d3hot_delay >= delay) in quirk_d3hot_delay()
1929 dev->d3hot_delay = delay; in quirk_d3hot_delay()
1930 pci_info(dev, "extending delay after power-on from D3hot to %d msec\n", in quirk_d3hot_delay()
1931 dev->d3hot_delay); in quirk_d3hot_delay()
1936 if (dev->subsystem_vendor == PCI_VENDOR_ID_APPLE && in quirk_radeon_pm()
1937 dev->subsystem_device == 0x00e2) in quirk_radeon_pm()
1948 * remain on in D3hot state. The D3hot-to-D0 transition then requires an
1963 pr_info("%s detected: disable boot interrupt reroute\n", d->ident); in dmi_disable_ioapicreroute()
1974 .ident = "ASUSTek Computer INC. M2N-LR",
1977 DMI_MATCH(DMI_PRODUCT_NAME, "M2N-LR"),
1995 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT; in quirk_reroute_to_boot_interrupts_intel()
1997 dev->vendor, dev->device); in quirk_reroute_to_boot_interrupts_intel()
2022 * IO-APIC1 on 6300ESB generates boot interrupts, see Intel order no
2023 * 300641-004US, section 5.7.3.
2025 * Core IO on Xeon E5 1600/2600/4600, see Intel order no 326509-003.
2026 * Core IO on Xeon E5 v2, see Intel order no 329188-003.
2027 * Core IO on Xeon E7 v2, see Intel order no 329595-002.
2028 * Core IO on Xeon E5 v3, see Intel order no 330784-003.
2029 * Core IO on Xeon E7 v3, see Intel order no 332315-001US.
2030 * Core IO on Xeon E5 v4, see Intel order no 333810-002US.
2031 * Core IO on Xeon E7 v4, see Intel order no 332315-001US.
2032 * Core IO on Xeon D-1500, see Intel order no 332051-001.
2049 switch (dev->device) { in quirk_disable_intel_boot_interrupt()
2060 case 0x6f28: /* Xeon D-1500 */ in quirk_disable_intel_boot_interrupt()
2072 dev->vendor, dev->device); in quirk_disable_intel_boot_interrupt()
2075 * Device 29 Func 5 Device IDs of IO-APIC
2111 /* Disable boot interrupts on HT-1000 */
2137 dev->vendor, dev->device); in quirk_disable_broadcom_boot_interrupt()
2146 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode
2160 if ((dev->revision == AMD_813X_REV_B1) || in quirk_disable_amd_813x_boot_interrupt()
2161 (dev->revision == AMD_813X_REV_B2)) in quirk_disable_amd_813x_boot_interrupt()
2169 dev->vendor, dev->device); in quirk_disable_amd_813x_boot_interrupt()
2188 dev->vendor, dev->device); in quirk_disable_amd_8111_boot_interrupt()
2193 dev->vendor, dev->device); in quirk_disable_amd_8111_boot_interrupt()
2200 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
2202 * Re-allocate the region if needed...
2206 struct resource *r = &dev->resource[0]; in quirk_tc86c001_ide()
2208 if (r->start & 0x8) { in quirk_tc86c001_ide()
2209 r->flags |= IORESOURCE_UNSET; in quirk_tc86c001_ide()
2210 r->start = 0; in quirk_tc86c001_ide()
2211 r->end = 0xf; in quirk_tc86c001_ide()
2223 * Re-allocate the regions to a 256-byte boundary if necessary.
2230 if (dev->revision >= 2) in quirk_plx_pci9050()
2235 struct resource *r = &dev->resource[bar]; in quirk_plx_pci9050()
2236 pci_info(dev, "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n", in quirk_plx_pci9050()
2238 r->flags |= IORESOURCE_UNSET; in quirk_plx_pci9050()
2239 r->start = 0; in quirk_plx_pci9050()
2240 r->end = 0xff; in quirk_plx_pci9050()
2259 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4; in quirk_netmos()
2260 unsigned int num_serial = dev->subsystem_device & 0xf; in quirk_netmos()
2272 switch (dev->device) { in quirk_netmos()
2275 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM && in quirk_netmos()
2276 dev->subsystem_device == 0x0299) in quirk_netmos()
2285 dev->device, num_parallel, num_serial); in quirk_netmos()
2286 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) | in quirk_netmos()
2287 (dev->class & 0xff); in quirk_netmos()
2300 switch (dev->device) { in quirk_e100_interrupt()
2325 * re-enable them when it's ready. in quirk_e100_interrupt()
2336 if (dev->pm_cap) { in quirk_e100_interrupt()
2337 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); in quirk_e100_interrupt()
2391 * ASM1083/1085 PCIe-PCI bridge devices cause AER timeout errors on the
2398 * Some Pericom PCIe-to-PCI bridges in reverse mode need the PCIe Retrain
2407 dev->clear_retrain_link = 1; in quirk_enable_clear_retrain_link()
2416 u32 class = dev->class; in fixup_rev1_53c810()
2425 dev->class = PCI_CLASS_STORAGE_SCSI << 8; in fixup_rev1_53c810()
2426 pci_info(dev, "NCR 53c810 rev 1 PCI class overridden (%#08x -> %#08x)\n", in fixup_rev1_53c810()
2427 class, dev->class); in fixup_rev1_53c810()
2440 dev->io_window_1k = 1; in quirk_p64h2_1k_io()
2474 * VT6212L is found -- the CX700 core itself also contains a USB in quirk_via_cx700_pci_parking_caching()
2484 * p should contain the first (internal) VT6212L -- see if we have in quirk_via_cx700_pci_parking_caching()
2506 /* Set PCI Master Bus time-out to "1x16 PCLK" */ in quirk_via_cx700_pci_parking_caching()
2538 * DRBs - this is where we expose device 6.
2539 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
2557 * Some chipsets do not support MSI. We cannot easily rely on setting
2561 * MSI globally.
2566 pci_warn(dev, "MSI quirk detected; MSI disabled\n"); in quirk_disable_all_msi()
2578 /* Disable MSI on chipsets that are known to not support it */
2581 if (dev->subordinate) { in quirk_disable_msi()
2582 pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n"); in quirk_disable_msi()
2583 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; in quirk_disable_msi()
2600 apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0)); in quirk_amd_780_apc_msi()
2602 if (apc_bridge->device == 0x9602) in quirk_amd_780_apc_msi()
2612 * MSI capability is found and enabled.
2619 while (pos && ttl--) { in msi_ht_cap_enabled()
2624 pci_info(dev, "Found %s HT MSI Mapping\n", in msi_ht_cap_enabled()
2636 /* Check the HyperTransport MSI mapping to know whether MSI is enabled or not */
2646 * The nVidia CK804 chipset may have 2 HT MSI mappings. MSI is supported
2647 * if the MSI capability is set in any of these mappings.
2654 * Check HT MSI cap on this chipset and the root one. A single one in quirk_nvidia_ck804_msi_ht_cap()
2655 * having MSI is enough to be sure that MSI is supported. in quirk_nvidia_ck804_msi_ht_cap()
2657 pdev = pci_get_slot(dev->bus, 0); in quirk_nvidia_ck804_msi_ht_cap()
2667 /* Force enable MSI mapping capability on HT bridges */
2673 while (pos && ttl--) { in ht_enable_msi_mapping()
2678 pci_info(dev, "Enabling HT MSI Mapping\n"); in ht_enable_msi_mapping()
2694 * The P5N32-SLI motherboards from Asus have a problem with MSI
2695 * for the MCP55 NIC. It is not yet determined whether the MSI problem
2696 * also affects other devices. As for now, turn off MSI for this device.
2703 (strstr(board_name, "P5N32-SLI PREMIUM") || in nvenet_msi_disable()
2704 strstr(board_name, "P5N32-E SLI"))) { in nvenet_msi_disable()
2705 pci_info(dev, "Disabling MSI for MCP55 NIC on P5N32-SLI\n"); in nvenet_msi_disable()
2706 dev->no_msi = 1; in nvenet_msi_disable()
2714 * PCIe spec r6.0 sec 6.1.4.3 says that if MSI/MSI-X is enabled, the device
2715 * can't use INTx interrupts. Tegra's PCIe Root Ports don't generate MSI
2717 * generated. Though Tegra's PCIe Root Ports can generate MSI interrupts
2719 * INTx and MSI/MSI-X, it is required to disable MSI interrupts to avoid port
2724 dev->no_msi = 1; in pci_quirk_nvidia_tegra_disable_rp_msi()
2812 /* Check if there is HT MSI cap or enabled on this device */ in ht_check_msi_mapping()
2814 while (pos && ttl--) { in ht_check_msi_mapping()
2842 dev_no = host_bridge->devfn >> 3; in host_bridge_with_leaf()
2844 dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0)); in host_bridge_with_leaf()
2900 dev_no = dev->devfn >> 3; in nv_ht_enable_msi_mapping()
2901 for (i = dev_no; i >= 0; i--) { in nv_ht_enable_msi_mapping()
2902 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0)); in nv_ht_enable_msi_mapping()
2937 while (pos && ttl--) { in ht_disable_msi_mapping()
2942 pci_info(dev, "Disabling HT MSI Mapping\n"); in ht_disable_msi_mapping()
2961 /* check if there is HT MSI cap or enabled on this device */ in __nv_msi_ht_cap_quirk()
2964 /* no HT MSI CAP */ in __nv_msi_ht_cap_quirk()
2969 * HT MSI mapping should be disabled on devices that are below in __nv_msi_ht_cap_quirk()
2970 * a non-Hypertransport host bridge. Locate the host bridge... in __nv_msi_ht_cap_quirk()
2972 host_bridge = pci_get_domain_bus_and_slot(pci_domain_nr(dev->bus), 0, in __nv_msi_ht_cap_quirk()
2992 /* HT MSI is not enabled */ in __nv_msi_ht_cap_quirk()
2996 /* Host bridge is not to HT, disable HT MSI mapping on this device */ in __nv_msi_ht_cap_quirk()
3019 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; in quirk_msi_intx_disable_bug()
3027 * SB700 MSI issue will be fixed at HW level from revision A21; in quirk_msi_intx_disable_ati_bug()
3036 if ((p->revision < 0x3B) && (p->revision >= 0x30)) in quirk_msi_intx_disable_ati_bug()
3037 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; in quirk_msi_intx_disable_ati_bug()
3043 /* AR816X/AR817X/E210X MSI is fixed at HW level from revision 0x18 */ in quirk_msi_intx_disable_qca_bug()
3044 if (dev->revision < 0x18) { in quirk_msi_intx_disable_qca_bug()
3046 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; in quirk_msi_intx_disable_qca_bug()
3110 * Amazon's Annapurna Labs 1c36:0031 Root Ports don't support MSI-X, so it
3113 * Notice that this quirk also disables MSI (which may work, but hasn't been
3114 * tested), since currently there is no standard way to disable only MSI-X.
3121 dev->no_msi = 1; in quirk_al_msi_disable()
3122 pci_warn(dev, "Disabling MSI/MSI-X\n"); in quirk_al_msi_disable()
3130 * pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For some PCI-PCI
3137 dev->is_hotplug_bridge = 1; in quirk_hotplug_bridge()
3154 * MMC controller - so the SDHCI driver never sees them.
3178 if (PCI_FUNC(dev->devfn)) in ricoh_mmc_fixup_rl5c476()
3209 if (PCI_FUNC(dev->devfn)) in ricoh_mmc_fixup_r5c832()
3216 * 0x150 - SD2.0 mode enable for changing base clock in ricoh_mmc_fixup_r5c832()
3218 * 0xe1 - Base clock frequency in ricoh_mmc_fixup_r5c832()
3219 * 0x32 - 50Mhz new clock frequency in ricoh_mmc_fixup_r5c832()
3220 * 0xf9 - Key register for 0x150 in ricoh_mmc_fixup_r5c832()
3221 * 0xfc - key register for 0xe1 in ricoh_mmc_fixup_r5c832()
3223 if (dev->device == PCI_DEVICE_ID_RICOH_R5CE822 || in ricoh_mmc_fixup_r5c832()
3224 dev->device == PCI_DEVICE_ID_RICOH_R5CE823) { in ricoh_mmc_fixup_r5c832()
3261 * This is a quirk for masking VT-d spec-defined errors to platform error
3264 * on the RAS config settings of the platform) when a VT-d fault happens.
3267 * VT-d spec-related errors are already handled by the VT-d OS code, so no
3283 u32 class = dev->class; in fixup_ti816x_class()
3286 dev->class = PCI_CLASS_MULTIMEDIA_VIDEO << 8; in fixup_ti816x_class()
3287 pci_info(dev, "PCI class overridden (%#08x -> %#08x)\n", in fixup_ti816x_class()
3288 class, dev->class); in fixup_ti816x_class()
3299 dev->pcie_mpss = 1; /* 256 bytes */ in fixup_mpss_256()
3314 * coalescing must be disabled. Unfortunately, it cannot be re-enabled because
3350 /* Intel 5000 series memory controllers and ports 2-7 */
3365 /* Intel 5100 series memory controllers and ports 2-7 */
3392 dev->resource[2].end = dev->resource[2].start + ((u64) 1 << val) - 1; in quirk_intel_ntb()
3398 dev->resource[4].end = dev->resource[4].start + ((u64) 1 << val) - 1; in quirk_intel_ntb()
3407 * and the interrupt ends up -somewhere-.
3447 dev->d3hot_delay = 0; in quirk_remove_d3hot_delay()
3453 /* Lynxpoint-H PCH devices do not need 10ms d3hot_delay */
3483 dev->broken_intx_masking = 1; in quirk_broken_intx_masking()
3496 * RTL8110SC - Fails under PCI device assignment using DisINTx masking.
3503 * DisINTx can be set but the interrupt status bit is non-functional.
3543 * Check ConnectX-4/LX FW version to see if it supports legacy interrupts.
3559 if (pdev->device == mellanox_broken_intx_devs[i]) { in mellanox_check_broken_intx_masking()
3560 pdev->broken_intx_masking = 1; in mellanox_check_broken_intx_masking()
3566 * Getting here means Connect-IB cards and up. Connect-IB has no INTx in mellanox_check_broken_intx_masking()
3569 if (pdev->device == PCI_DEVICE_ID_MELLANOX_CONNECTIB) in mellanox_check_broken_intx_masking()
3572 if (pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4 && in mellanox_check_broken_intx_masking()
3573 pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) in mellanox_check_broken_intx_masking()
3576 /* For ConnectX-4 and ConnectX-4LX, need to check FW support */ in mellanox_check_broken_intx_masking()
3584 pci_warn(pdev, "Can't map ConnectX-4 initialization segment\n"); in mellanox_check_broken_intx_masking()
3596 …pci_warn(pdev, "ConnectX-4: FW %u.%u.%u doesn't support INTx masking, disabling. Please upgrade FW… in mellanox_check_broken_intx_masking()
3597 fw_major, fw_minor, fw_subminor, pdev->device == in mellanox_check_broken_intx_masking()
3599 pdev->broken_intx_masking = 1; in mellanox_check_broken_intx_masking()
3612 dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET; in quirk_no_bus_reset()
3621 if ((dev->device & 0xffc0) == 0x2340) in quirk_nvidia_no_bus_reset()
3629 * The device will throw a Link Down error on AER-capable systems and
3664 if (!pci_is_root_bus(dev->bus)) in quirk_no_pm_reset()
3665 dev->dev_flags |= PCI_DEV_FLAGS_NO_PM_RESET; in quirk_no_pm_reset()
3669 * Some AMD/ATI GPUS (HD8570 - Oland) report that a D3hot->D0 transition
3670 * causes a reset (i.e., they advertise NoSoftRst-). This transition seems
3680 * Thunderbolt controllers with broken MSI hotplug signaling:
3686 if (pdev->is_hotplug_bridge && in quirk_thunderbolt_hotplug_msi()
3687 (pdev->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C || in quirk_thunderbolt_hotplug_msi()
3688 pdev->revision <= 1)) in quirk_thunderbolt_hotplug_msi()
3689 pdev->no_msi = 1; in quirk_thunderbolt_hotplug_msi()
3736 bridge = ACPI_HANDLE(&dev->dev); in quirk_apple_poweroff_thunderbolt()
3767 * Following are device-specific reset methods which can be used to
3768 * reset a single function if other methods (e.g. FLR, PM D0->D3) are
3774 * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf in reset_intel_82599_sfp_virtfn()
3804 return -ENOMEM; in reset_ivb_igd()
3835 /* Device-specific reset method for Chelsio T4-based adapters */
3842 * If this isn't a Chelsio T4-based device, return -ENOTTY indicating in reset_chelsio_generic_dev()
3843 * that we have no device-specific reset method. in reset_chelsio_generic_dev()
3845 if ((dev->device & 0xf000) != 0x4000) in reset_chelsio_generic_dev()
3846 return -ENOTTY; in reset_chelsio_generic_dev()
3872 * T4 also suffers a Head-Of-Line blocking problem if MSI-X interrupts in reset_chelsio_generic_dev()
3873 * are disabled when an MSI-X interrupt message needs to be delivered. in reset_chelsio_generic_dev()
3874 * So we briefly re-enable MSI-X interrupts for the duration of the in reset_chelsio_generic_dev()
3876 * MSI-X state. in reset_chelsio_generic_dev()
3878 pci_read_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, &msix_flags); in reset_chelsio_generic_dev()
3880 pci_write_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, in reset_chelsio_generic_dev()
3903 * FLR where config space reads from the device return -1. We seem to be
3920 if (dev->class != PCI_CLASS_STORAGE_EXPRESS || in nvme_disable_and_flr()
3922 return -ENOTTY; in nvme_disable_and_flr()
3929 return -ENOTTY; in nvme_disable_and_flr()
4007 /* Device-specific reset method for Huawei Intelligent NIC virtual functions */
4019 return -ENOTTY; in reset_hinic_vf_dev()
4025 return -ENOTTY; in reset_hinic_vf_dev()
4081 * These device-specific reset methods are here rather than in a driver
4089 for (i = pci_dev_reset_methods; i->reset; i++) { in pci_dev_specific_reset()
4090 if ((i->vendor == dev->vendor || in pci_dev_specific_reset()
4091 i->vendor == (u16)PCI_ANY_ID) && in pci_dev_specific_reset()
4092 (i->device == dev->device || in pci_dev_specific_reset()
4093 i->device == (u16)PCI_ANY_ID)) in pci_dev_specific_reset()
4094 return i->reset(dev, probe); in pci_dev_specific_reset()
4097 return -ENOTTY; in pci_dev_specific_reset()
4102 if (PCI_FUNC(dev->devfn) != 0) in quirk_dma_func0_alias()
4103 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 0), 1); in quirk_dma_func0_alias()
4116 if (PCI_FUNC(dev->devfn) != 1) in quirk_dma_func1_alias()
4117 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 1), 1); in quirk_dma_func1_alias()
4173 DECLARE_PCI_FIXUP_HEADER(0x1c28, /* Lite-On */
4183 * processor. To software, this appears as a PCIe-to-PCI/X bridge with a
4208 pci_add_dma_alias(dev, id->driver_data, 1); in quirk_fixed_dma_alias()
4213 * A few PCIe-to-PCI bridges fail to expose a PCIe capability, resulting in
4218 * is for a non-root, non-PCIe bridge where the upstream device is PCIe and
4219 * is not a PCIe-to-PCI bridge, then @pdev is actually a PCIe-to-PCI bridge.
4223 if (!pci_is_root_bus(pdev->bus) && in quirk_use_pcie_bridge_dma_alias()
4224 pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE && in quirk_use_pcie_bridge_dma_alias()
4225 !pci_is_pcie(pdev) && pci_is_pcie(pdev->bus->self) && in quirk_use_pcie_bridge_dma_alias()
4226 pci_pcie_type(pdev->bus->self) != PCI_EXP_TYPE_PCI_BRIDGE) in quirk_use_pcie_bridge_dma_alias()
4227 pdev->dev_flags |= PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS; in quirk_use_pcie_bridge_dma_alias()
4244 * when IOMMU is enabled. Following devfns have to match RIT-LUT table
4257 * Intel Visual Compute Accelerator (VCA) is a family of PCIe add-in devices
4292 pdev->dev_flags |= PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT; in quirk_bridge_cavm_thrx2_pcie_root()
4300 * Intersil/Techwell TW686[4589]-based video capture cards have an empty (zero)
4305 u32 class = pdev->class; in quirk_tw686x_class()
4308 pdev->class = (PCI_CLASS_MULTIMEDIA_OTHER << 8) | 0x01; in quirk_tw686x_class()
4309 pci_info(pdev, "TW686x PCI class overridden (%#08x -> %#08x)\n", in quirk_tw686x_class()
4310 class, pdev->class); in quirk_tw686x_class()
4328 dev->dev_flags |= PCI_DEV_FLAGS_NO_RELAXED_ORDERING; in quirk_relaxedordering_disable()
4415 * If a non-compliant device generates a completion with a different
4417 * seems non-compliant based on sec 2.3.2), or it may handle it as a
4421 * If the non-compliant device generates completions with zero attributes
4443 dev_name(&pdev->dev)); in quirk_disable_root_port_attributes()
4461 if ((pdev->device & 0xff00) == 0x5400) in quirk_chelsio_T5_disable_root_port_attributes()
4468 * pci_acs_ctrl_enabled - compare desired ACS controls with those provided
4486 * AMD has indicated that the devices below do not support peer-to-peer
4489 * peer-to-peer between functions can claim to support a subset of ACS.
4517 if (!dev->multifunction || !pci_is_root_bus(dev->bus)) in pci_quirk_amd_sb_acs()
4518 return -ENODEV; in pci_quirk_amd_sb_acs()
4523 return -ENODEV; in pci_quirk_amd_sb_acs()
4532 return -ENODEV; in pci_quirk_amd_sb_acs()
4541 switch (dev->device) { in pci_quirk_cavium_acs_match()
4558 return -ENOTTY; in pci_quirk_cavium_acs()
4575 * X-Gene Root Ports matching this quirk do not allow peer-to-peer in pci_quirk_xgene_acs()
4585 * But the implementation could block peer-to-peer transactions between them
4586 * and provide ACS-like functionality.
4593 return -ENOTTY; in pci_quirk_zhaoxin_pcie_ports_acs()
4595 switch (dev->device) { in pci_quirk_zhaoxin_pcie_ports_acs()
4607 * Many Intel PCH Root Ports do provide ACS-like features to disable peer
4622 /* Lynxpoint-H PCH */
4625 /* Lynxpoint-LP PCH */
4644 /* Filter out a few obvious non-matches first */ in pci_quirk_intel_pch_acs_match()
4649 if (pci_quirk_intel_pch_acs_ids[i] == dev->device) in pci_quirk_intel_pch_acs_match()
4658 return -ENOTTY; in pci_quirk_intel_pch_acs()
4660 if (dev->dev_flags & PCI_DEV_FLAGS_ACS_ENABLED_QUIRK) in pci_quirk_intel_pch_acs()
4668 * These QCOM Root Ports do provide ACS-like features to disable peer
4672 * Hardware doesn't support peer-to-peer and each Root Port is a Root
4698 return -ENOTTY; in pci_quirk_al_acs()
4702 * but do include ACS-like functionality. The hardware doesn't support in pci_quirk_al_acs()
4703 * peer-to-peer transactions via the root port and each has a unique in pci_quirk_al_acs()
4723 * 0xa110-0xa11f Sunrise Point-H PCI Express Root Port #{0-16}
4724 * 0xa167-0xa16a Sunrise Point-H PCI Express Root Port #{17-20}
4732 * Hub, Specification Update, January 2017, Revision 001, Document# 335194-001,
4736 * 0xa290-0xa29f PCI Express Root port #{0-16}
4737 * 0xa2e7-0xa2ee PCI Express Root port #{17-24}
4743 * August 2017, Revision 002, Document#: 334660-002)[6]
4746 * Quad Core Platforms, Vol 1 of 2, August 2017, Document#: 334658-003)[7]
4748 * 0x9d10-0x9d1b PCI Express Root port #{1-12}
4750 * [1] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-2.html
4751 * [2] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-1.html
4752 * [3] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-spec-update.html
4753 * [4] https://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-spec-update.html
4754 * [5] https://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-datasheet-vol-1.html
4755 …ww.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-…
4756 …tel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-datas…
4763 switch (dev->device) { in pci_quirk_intel_spt_pch_acs_match()
4781 return -ENOTTY; in pci_quirk_intel_spt_pch_acs()
4783 pos = dev->acs_cap; in pci_quirk_intel_spt_pch_acs()
4785 return -ENOTTY; in pci_quirk_intel_spt_pch_acs()
4802 * in their ACS capability if they support peer-to-peer transactions. in pci_quirk_mf_endpoint_acs()
4804 * perform peer-to-peer with other functions, allowing us to mask out in pci_quirk_mf_endpoint_acs()
4816 * addresses. Refer to Intel VT-d specification, r3.1, sec 3.16, in pci_quirk_rciep_acs()
4817 * "Root-Complex Peer to Peer Considerations". in pci_quirk_rciep_acs()
4820 return -ENOTTY; in pci_quirk_rciep_acs()
4829 * iProc PAXB Root Ports don't advertise an ACS capability, but in pci_quirk_brcm_acs()
4830 * they do not allow peer-to-peer transactions between Root Ports. in pci_quirk_brcm_acs()
4900 /* 82571 (Quads omitted due to non-ACS switch) */
4917 { 0x19a2, 0x710, pci_quirk_mf_endpoint_acs }, /* Emulex BE3-R */
4918 { 0x10df, 0x720, pci_quirk_mf_endpoint_acs }, /* Emulex Skyhawk-R */
4921 /* Cavium multi-function devices */
4925 /* APM X-Gene */
4936 /* Broadcom multi-function device */
4944 /* Zhaoxin multi-function devices */
4949 /* LX2xx0A : without security features + CAN-FD */
4953 /* LX2xx0C : security features + CAN-FD */
4965 /* LX2xx2A : without security features + CAN-FD */
4969 /* LX2xx2C : security features + CAN-FD */
4987 * pci_dev_specific_acs_enabled - check whether device provides ACS controls
4992 * -ENOTTY: No quirk applies to this device; we can't tell whether the
5004 * or control to indicate their support here. Multi-function express in pci_dev_specific_acs_enabled()
5005 * devices which do not allow internal peer-to-peer between functions, in pci_dev_specific_acs_enabled()
5008 for (i = pci_dev_acs_enabled; i->acs_enabled; i++) { in pci_dev_specific_acs_enabled()
5009 if ((i->vendor == dev->vendor || in pci_dev_specific_acs_enabled()
5010 i->vendor == (u16)PCI_ANY_ID) && in pci_dev_specific_acs_enabled()
5011 (i->device == dev->device || in pci_dev_specific_acs_enabled()
5012 i->device == (u16)PCI_ANY_ID)) { in pci_dev_specific_acs_enabled()
5013 ret = i->acs_enabled(dev, acs_flags); in pci_dev_specific_acs_enabled()
5019 return -ENOTTY; in pci_dev_specific_acs_enabled()
5031 /* Backbone Peer Non-Posted Disable */
5051 pci_bus_read_config_dword(dev->bus, PCI_DEVFN(31, 0), in pci_quirk_enable_intel_lpc_acs()
5054 return -EINVAL; in pci_quirk_enable_intel_lpc_acs()
5059 return -ENOMEM; in pci_quirk_enable_intel_lpc_acs()
5063 * therefore read-only. If both posted and non-posted peer cycles are in pci_quirk_enable_intel_lpc_acs()
5111 * if dev->external_facing || dev->untrusted
5116 return -ENOTTY; in pci_quirk_enable_intel_pch_acs()
5125 dev->dev_flags |= PCI_DEV_FLAGS_ACS_ENABLED_QUIRK; in pci_quirk_enable_intel_pch_acs()
5138 return -ENOTTY; in pci_quirk_enable_intel_spt_pch_acs()
5140 pos = dev->acs_cap; in pci_quirk_enable_intel_spt_pch_acs()
5142 return -ENOTTY; in pci_quirk_enable_intel_spt_pch_acs()
5152 if (pci_ats_disabled() || dev->external_facing || dev->untrusted) in pci_quirk_enable_intel_spt_pch_acs()
5168 return -ENOTTY; in pci_quirk_disable_intel_spt_pch_acs_redir()
5170 pos = dev->acs_cap; in pci_quirk_disable_intel_spt_pch_acs_redir()
5172 return -ENOTTY; in pci_quirk_disable_intel_spt_pch_acs_redir()
5208 if ((p->vendor == dev->vendor || in pci_dev_specific_enable_acs()
5209 p->vendor == (u16)PCI_ANY_ID) && in pci_dev_specific_enable_acs()
5210 (p->device == dev->device || in pci_dev_specific_enable_acs()
5211 p->device == (u16)PCI_ANY_ID) && in pci_dev_specific_enable_acs()
5212 p->enable_acs) { in pci_dev_specific_enable_acs()
5213 ret = p->enable_acs(dev); in pci_dev_specific_enable_acs()
5219 return -ENOTTY; in pci_dev_specific_enable_acs()
5229 if ((p->vendor == dev->vendor || in pci_dev_specific_disable_acs_redir()
5230 p->vendor == (u16)PCI_ANY_ID) && in pci_dev_specific_disable_acs_redir()
5231 (p->device == dev->device || in pci_dev_specific_disable_acs_redir()
5232 p->device == (u16)PCI_ANY_ID) && in pci_dev_specific_disable_acs_redir()
5233 p->disable_acs_redir) { in pci_dev_specific_disable_acs_redir()
5234 ret = p->disable_acs_redir(dev); in pci_dev_specific_disable_acs_redir()
5240 return -ENOTTY; in pci_dev_specific_disable_acs_redir()
5246 * Next Capability pointer in the MSI Capability Structure should point to
5258 if (pdev->pcie_cap || pci_find_capability(pdev, PCI_CAP_ID_EXP)) in quirk_intel_qat_vf_cap()
5261 /* Bail if MSI Capability Structure is not found for some reason */ in quirk_intel_qat_vf_cap()
5267 * Bail if Next Capability pointer in the MSI Capability Structure in quirk_intel_qat_vf_cap()
5278 * Open-code some of set_pcie_port_type() and pci_cfg_space_size_ext() in quirk_intel_qat_vf_cap()
5291 pdev->pcie_cap = pos; in quirk_intel_qat_vf_cap()
5293 pdev->pcie_flags_reg = reg16; in quirk_intel_qat_vf_cap()
5295 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD; in quirk_intel_qat_vf_cap()
5297 pdev->cfg_size = PCI_CFG_SPACE_EXP_SIZE; in quirk_intel_qat_vf_cap()
5300 pdev->cfg_size = PCI_CFG_SPACE_SIZE; in quirk_intel_qat_vf_cap()
5310 state->cap.cap_nr = PCI_CAP_ID_EXP; in quirk_intel_qat_vf_cap()
5311 state->cap.cap_extended = 0; in quirk_intel_qat_vf_cap()
5312 state->cap.size = size; in quirk_intel_qat_vf_cap()
5313 cap = (u16 *)&state->cap.data[0]; in quirk_intel_qat_vf_cap()
5321 hlist_add_head(&state->next, &pdev->saved_cap_space); in quirk_intel_qat_vf_cap()
5338 dev->dev_flags |= PCI_DEV_FLAGS_NO_FLR_RESET; in quirk_no_flr()
5348 struct pci_host_bridge *bridge = pci_find_host_bridge(pdev->bus); in quirk_no_ext_tags()
5353 bridge->no_ext_tags = 1; in quirk_no_ext_tags()
5356 pci_walk_bus(bridge->bus, pci_configure_extended_tags, NULL); in quirk_no_ext_tags()
5374 if (pdev->device == 0x15d8) { in quirk_amd_harvest_no_ats()
5375 if (pdev->revision == 0xcf && in quirk_amd_harvest_no_ats()
5376 pdev->subsystem_vendor == 0xea50 && in quirk_amd_harvest_no_ats()
5377 (pdev->subsystem_device == 0xce19 || in quirk_amd_harvest_no_ats()
5378 pdev->subsystem_device == 0xcc10 || in quirk_amd_harvest_no_ats()
5379 pdev->subsystem_device == 0xcc08)) in quirk_amd_harvest_no_ats()
5387 pdev->ats_cap = 0; in quirk_amd_harvest_no_ats()
5412 /* Freescale PCIe doesn't support MSI in RC mode */
5416 pdev->no_msi = 1; in quirk_fsl_no_msi()
5421 * Although not allowed by the spec, some multi-function devices have
5434 if (PCI_FUNC(pdev->devfn) != consumer) in pci_create_device_link()
5437 supplier_pdev = pci_get_domain_bus_and_slot(pci_domain_nr(pdev->bus), in pci_create_device_link()
5438 pdev->bus->number, in pci_create_device_link()
5439 PCI_DEVFN(PCI_SLOT(pdev->devfn), supplier)); in pci_create_device_link()
5440 if (!supplier_pdev || (supplier_pdev->class >> class_shift) != class) { in pci_create_device_link()
5445 if (device_link_add(&pdev->dev, &supplier_pdev->dev, in pci_create_device_link()
5453 pm_runtime_allow(&pdev->dev); in pci_create_device_link()
5486 * Create device link for GPUs with integrated Type-C UCSI controller
5513 if (gpu->device < PCI_DEVICE_ID_NVIDIA_GEFORCE_320M) in quirk_nvidia_hda()
5524 /* The GPU becomes a multi-function device when the HDA is enabled */ in quirk_nvidia_hda()
5526 gpu->multifunction = !!(hdr_type & 0x80); in quirk_nvidia_hda()
5537 * Validation. Here's the text of IDT 89H32H8G3-YC, erratum #36:
5539 * Item #36 - Downstream port applies ACS Source Validation to Completions
5552 * write, so we do config reads until we receive a non-Config Request Retry
5563 struct pci_dev *bridge = bus->self; in pci_idt_bus_quirk()
5565 pos = bridge->acs_cap; in pci_idt_bus_quirk()
5577 /* Write Vendor ID (read-only) so the endpoint latches its bus/dev */ in pci_idt_bus_quirk()
5581 /* Re-enable ACS_SV if it was previously enabled */ in pci_idt_bus_quirk()
5621 partition = ioread8(&mmio_ntb->partition_id); in quirk_switchtec_ntb_dma_alias()
5623 partition_map = ioread32(&mmio_ntb->ep_map); in quirk_switchtec_ntb_dma_alias()
5624 partition_map |= ((u64) ioread32(&mmio_ntb->ep_map + 4)) << 32; in quirk_switchtec_ntb_dma_alias()
5639 table_sz = ioread16(&mmio_peer_ctrl->req_id_table_size); in quirk_switchtec_ntb_dma_alias()
5656 rid_entry = ioread32(&mmio_peer_ctrl->req_id_table[te]); in quirk_switchtec_ntb_dma_alias()
5766 if (pdev->subsystem_vendor != PCI_VENDOR_ID_LENOVO || in quirk_reset_lenovo_thinkpad_p50_nvgpu()
5767 pdev->subsystem_device != 0x222e || in quirk_reset_lenovo_thinkpad_p50_nvgpu()
5810 dev->pme_support &= ~(PCI_PM_CAP_PME_D0 >> PCI_PM_CAP_PME_SHIFT); in pci_fixup_no_d0_pme()
5820 * These devices also advertise MSI, but documentation (PI7C9X440SL.pdf)
5821 * says "The MSI Function is not implemented on this device" in chapters
5822 * 7.3.27, 7.3.29-7.3.31.
5827 pci_info(dev, "MSI is not implemented on this device, disabling it\n"); in pci_fixup_no_msi_no_pme()
5828 dev->no_msi = 1; in pci_fixup_no_msi_no_pme()
5831 dev->pme_support = 0; in pci_fixup_no_msi_no_pme()
5838 pdev->class = (PCI_CLASS_SYSTEM_OTHER << 8) | pdev->class; in apex_pci_fixup_class()
5844 * Pericom PI7C9X2G404/PI7C9X2G304/PI7C9X2G303 switch erratum E5 -
5864 if (!pdev->acs_cap) in pci_fixup_pericom_acs_store_forward()
5866 pci_read_config_word(pdev, pdev->acs_cap + PCI_ACS_CTRL, &val); in pci_fixup_pericom_acs_store_forward()
5876 pci_info(upstream, "Setting PI7C9X2Gxxx store-forward mode to avoid ACS erratum\n"); in pci_fixup_pericom_acs_store_forward()
5900 pdev->dev_flags |= PCI_DEV_FLAGS_HAS_MSI_MASKING; in nvidia_ion_ahci_fixup()
5907 dev->rom_bar_overlap = 1; in rom_bar_overlap_defect()
5924 u32 l1_lat = FIELD_GET(PCI_EXP_DEVCAP_L1, dev->devcap); in aspm_l1_acceptable_latency()
5927 dev->devcap |= FIELD_PREP(PCI_EXP_DEVCAP_L1, 7); in aspm_l1_acceptable_latency()
5979 dev->dpc_rp_log_size = 4; in dpc_log_size()