Lines Matching +full:parent +full:- +full:child
1 // SPDX-License-Identifier: GPL-2.0
49 struct pcie_link_state *parent; /* pointer to the parent Link state */ member
101 struct pci_dev *child; in pci_function_0() local
103 list_for_each_entry(child, &linkbus->devices, bus_list) in pci_function_0()
104 if (PCI_FUNC(child->devfn) == 0) in pci_function_0()
105 return child; in pci_function_0()
122 return link->aspm_default; in policy_to_aspm_state()
138 return link->clkpm_default; in policy_to_clkpm_state()
145 struct pci_dev *child; in pcie_set_clkpm_nocheck() local
146 struct pci_bus *linkbus = link->pdev->subordinate; in pcie_set_clkpm_nocheck()
149 list_for_each_entry(child, &linkbus->devices, bus_list) in pcie_set_clkpm_nocheck()
150 pcie_capability_clear_and_set_word(child, PCI_EXP_LNKCTL, in pcie_set_clkpm_nocheck()
153 link->clkpm_enabled = !!enable; in pcie_set_clkpm_nocheck()
162 if (!link->clkpm_capable || link->clkpm_disable) in pcie_set_clkpm()
165 if (link->clkpm_enabled == enable) in pcie_set_clkpm()
175 struct pci_dev *child; in pcie_clkpm_cap_init() local
176 struct pci_bus *linkbus = link->pdev->subordinate; in pcie_clkpm_cap_init()
179 list_for_each_entry(child, &linkbus->devices, bus_list) { in pcie_clkpm_cap_init()
180 pcie_capability_read_dword(child, PCI_EXP_LNKCAP, ®32); in pcie_clkpm_cap_init()
186 pcie_capability_read_word(child, PCI_EXP_LNKCTL, ®16); in pcie_clkpm_cap_init()
190 link->clkpm_enabled = enabled; in pcie_clkpm_cap_init()
191 link->clkpm_default = enabled; in pcie_clkpm_cap_init()
192 link->clkpm_capable = capable; in pcie_clkpm_cap_init()
193 link->clkpm_disable = blacklist ? 1 : 0; in pcie_clkpm_cap_init()
198 struct pci_dev *parent = link->pdev; in pcie_retrain_link() local
202 pcie_capability_read_word(parent, PCI_EXP_LNKCTL, ®16); in pcie_retrain_link()
204 pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16); in pcie_retrain_link()
205 if (parent->clear_retrain_link) { in pcie_retrain_link()
212 pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16); in pcie_retrain_link()
218 pcie_capability_read_word(parent, PCI_EXP_LNKSTA, ®16); in pcie_retrain_link()
235 struct pci_dev *child, *parent = link->pdev; in pcie_aspm_configure_common_clock() local
236 struct pci_bus *linkbus = parent->subordinate; in pcie_aspm_configure_common_clock()
241 child = list_entry(linkbus->devices.next, struct pci_dev, bus_list); in pcie_aspm_configure_common_clock()
242 BUG_ON(!pci_is_pcie(child)); in pcie_aspm_configure_common_clock()
245 pcie_capability_read_word(child, PCI_EXP_LNKSTA, ®16); in pcie_aspm_configure_common_clock()
250 pcie_capability_read_word(parent, PCI_EXP_LNKSTA, ®16); in pcie_aspm_configure_common_clock()
255 pcie_capability_read_word(parent, PCI_EXP_LNKCTL, ®16); in pcie_aspm_configure_common_clock()
259 list_for_each_entry(child, &linkbus->devices, bus_list) { in pcie_aspm_configure_common_clock()
260 pcie_capability_read_word(child, PCI_EXP_LNKCTL, in pcie_aspm_configure_common_clock()
269 pci_info(parent, "ASPM: current common clock configuration is inconsistent, reconfiguring\n"); in pcie_aspm_configure_common_clock()
273 list_for_each_entry(child, &linkbus->devices, bus_list) { in pcie_aspm_configure_common_clock()
274 pcie_capability_read_word(child, PCI_EXP_LNKCTL, ®16); in pcie_aspm_configure_common_clock()
275 child_reg[PCI_FUNC(child->devfn)] = reg16; in pcie_aspm_configure_common_clock()
280 pcie_capability_write_word(child, PCI_EXP_LNKCTL, reg16); in pcie_aspm_configure_common_clock()
284 pcie_capability_read_word(parent, PCI_EXP_LNKCTL, ®16); in pcie_aspm_configure_common_clock()
290 pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16); in pcie_aspm_configure_common_clock()
296 pci_err(parent, "ASPM: Could not configure common clock\n"); in pcie_aspm_configure_common_clock()
297 list_for_each_entry(child, &linkbus->devices, bus_list) in pcie_aspm_configure_common_clock()
298 pcie_capability_write_word(child, PCI_EXP_LNKCTL, in pcie_aspm_configure_common_clock()
299 child_reg[PCI_FUNC(child->devfn)]); in pcie_aspm_configure_common_clock()
300 pcie_capability_write_word(parent, PCI_EXP_LNKCTL, parent_reg); in pcie_aspm_configure_common_clock()
317 return -1U; in calc_l0s_acceptable()
335 return -1U; in calc_l1_acceptable()
367 * LTR_L1.2_THRESHOLD_Value ("value") is a 10-bit field with max in encode_l12_threshold()
403 if ((endpoint->current_state != PCI_D0) && in pcie_aspm_check_latency()
404 (endpoint->current_state != PCI_UNKNOWN)) in pcie_aspm_check_latency()
407 link = endpoint->bus->self->link_state; in pcie_aspm_check_latency()
410 encoding = (endpoint->devcap & PCI_EXP_DEVCAP_L0S) >> 6; in pcie_aspm_check_latency()
414 encoding = (endpoint->devcap & PCI_EXP_DEVCAP_L1) >> 9; in pcie_aspm_check_latency()
418 struct pci_dev *dev = pci_function_0(link->pdev->subordinate); in pcie_aspm_check_latency()
421 pcie_capability_read_dword(link->pdev, PCI_EXP_LNKCAP, in pcie_aspm_check_latency()
431 if ((link->aspm_capable & ASPM_STATE_L0S_UP) && in pcie_aspm_check_latency()
433 link->aspm_capable &= ~ASPM_STATE_L0S_UP; in pcie_aspm_check_latency()
436 if ((link->aspm_capable & ASPM_STATE_L0S_DW) && in pcie_aspm_check_latency()
438 link->aspm_capable &= ~ASPM_STATE_L0S_DW; in pcie_aspm_check_latency()
453 if ((link->aspm_capable & ASPM_STATE_L1) && in pcie_aspm_check_latency()
455 link->aspm_capable &= ~ASPM_STATE_L1; in pcie_aspm_check_latency()
458 link = link->parent; in pcie_aspm_check_latency()
475 u16 l1ss = dev->l1ss; in aspm_program_l1ss()
502 struct pci_dev *child = link->downstream, *parent = link->pdev; in aspm_calc_l1ss_info() local
508 if (!(link->aspm_support & ASPM_STATE_L1_2_MASK)) in aspm_calc_l1ss_info()
522 if (calc_l1ss_pwron(parent, scale1, val1) > in aspm_calc_l1ss_info()
523 calc_l1ss_pwron(child, scale2, val2)) { in aspm_calc_l1ss_info()
525 t_power_on = calc_l1ss_pwron(parent, scale1, val1); in aspm_calc_l1ss_info()
528 t_power_on = calc_l1ss_pwron(child, scale2, val2); in aspm_calc_l1ss_info()
537 * Based on PCIe r3.1, sec 5.5.3.3.1, Figures 5-16 and 5-17, and in aspm_calc_l1ss_info()
538 * Table 5-11. T(POWER_OFF) is at most 2us and T(L1.2) is at in aspm_calc_l1ss_info()
546 pci_read_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1, &pctl1); in aspm_calc_l1ss_info()
547 pci_read_config_dword(parent, parent->l1ss + PCI_L1SS_CTL2, &pctl2); in aspm_calc_l1ss_info()
548 pci_read_config_dword(child, child->l1ss + PCI_L1SS_CTL1, &cctl1); in aspm_calc_l1ss_info()
549 pci_read_config_dword(child, child->l1ss + PCI_L1SS_CTL2, &cctl2); in aspm_calc_l1ss_info()
561 aspm_program_l1ss(parent, pctl1, ctl2); in aspm_calc_l1ss_info()
569 aspm_program_l1ss(child, cctl1, ctl2); in aspm_calc_l1ss_info()
574 struct pci_dev *child = link->downstream, *parent = link->pdev; in aspm_l1ss_init() local
578 if (!parent->l1ss || !child->l1ss) in aspm_l1ss_init()
582 pci_read_config_dword(parent, parent->l1ss + PCI_L1SS_CAP, in aspm_l1ss_init()
584 pci_read_config_dword(child, child->l1ss + PCI_L1SS_CAP, in aspm_l1ss_init()
597 if (!child->ltr_path) in aspm_l1ss_init()
601 link->aspm_support |= ASPM_STATE_L1_1; in aspm_l1ss_init()
603 link->aspm_support |= ASPM_STATE_L1_2; in aspm_l1ss_init()
605 link->aspm_support |= ASPM_STATE_L1_1_PCIPM; in aspm_l1ss_init()
607 link->aspm_support |= ASPM_STATE_L1_2_PCIPM; in aspm_l1ss_init()
610 pci_read_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1, in aspm_l1ss_init()
613 pci_read_config_dword(child, child->l1ss + PCI_L1SS_CTL1, in aspm_l1ss_init()
617 link->aspm_enabled |= ASPM_STATE_L1_1; in aspm_l1ss_init()
619 link->aspm_enabled |= ASPM_STATE_L1_2; in aspm_l1ss_init()
621 link->aspm_enabled |= ASPM_STATE_L1_1_PCIPM; in aspm_l1ss_init()
623 link->aspm_enabled |= ASPM_STATE_L1_2_PCIPM; in aspm_l1ss_init()
625 if (link->aspm_support & ASPM_STATE_L1SS) in aspm_l1ss_init()
631 struct pci_dev *child = link->downstream, *parent = link->pdev; in pcie_aspm_cap_init() local
634 struct pci_bus *linkbus = parent->subordinate; in pcie_aspm_cap_init()
638 link->aspm_enabled = ASPM_STATE_ALL; in pcie_aspm_cap_init()
639 link->aspm_disable = ASPM_STATE_ALL; in pcie_aspm_cap_init()
647 pcie_capability_read_dword(parent, PCI_EXP_LNKCAP, &parent_lnkcap); in pcie_aspm_cap_init()
648 pcie_capability_read_dword(child, PCI_EXP_LNKCAP, &child_lnkcap); in pcie_aspm_cap_init()
656 * Re-read upstream/downstream components' register state after in pcie_aspm_cap_init()
658 * read-only Link Capabilities may change depending on common clock in pcie_aspm_cap_init()
661 pcie_capability_read_dword(parent, PCI_EXP_LNKCAP, &parent_lnkcap); in pcie_aspm_cap_init()
662 pcie_capability_read_dword(child, PCI_EXP_LNKCAP, &child_lnkcap); in pcie_aspm_cap_init()
663 pcie_capability_read_word(parent, PCI_EXP_LNKCTL, &parent_lnkctl); in pcie_aspm_cap_init()
664 pcie_capability_read_word(child, PCI_EXP_LNKCTL, &child_lnkctl); in pcie_aspm_cap_init()
674 link->aspm_support |= ASPM_STATE_L0S; in pcie_aspm_cap_init()
677 link->aspm_enabled |= ASPM_STATE_L0S_UP; in pcie_aspm_cap_init()
679 link->aspm_enabled |= ASPM_STATE_L0S_DW; in pcie_aspm_cap_init()
683 link->aspm_support |= ASPM_STATE_L1; in pcie_aspm_cap_init()
686 link->aspm_enabled |= ASPM_STATE_L1; in pcie_aspm_cap_init()
691 link->aspm_default = link->aspm_enabled; in pcie_aspm_cap_init()
694 link->aspm_capable = link->aspm_support; in pcie_aspm_cap_init()
697 list_for_each_entry(child, &linkbus->devices, bus_list) { in pcie_aspm_cap_init()
698 if (pci_pcie_type(child) != PCI_EXP_TYPE_ENDPOINT && in pcie_aspm_cap_init()
699 pci_pcie_type(child) != PCI_EXP_TYPE_LEG_END) in pcie_aspm_cap_init()
702 pcie_aspm_check_latency(child); in pcie_aspm_cap_init()
710 struct pci_dev *child = link->downstream, *parent = link->pdev; in pcie_config_aspm_l1ss() local
712 enable_req = (link->aspm_enabled ^ state) & state; in pcie_config_aspm_l1ss()
716 * - When enabling L1.x, enable bit at parent first, then at child in pcie_config_aspm_l1ss()
717 * - When disabling L1.x, disable bit at child first, then at parent in pcie_config_aspm_l1ss()
718 * - When enabling ASPM L1.x, need to disable L1 in pcie_config_aspm_l1ss()
719 * (at child followed by parent). in pcie_config_aspm_l1ss()
720 * - The ASPM/PCIPM L1.2 must be disabled while programming timing in pcie_config_aspm_l1ss()
728 pci_clear_and_set_dword(child, child->l1ss + PCI_L1SS_CTL1, in pcie_config_aspm_l1ss()
730 pci_clear_and_set_dword(parent, parent->l1ss + PCI_L1SS_CTL1, in pcie_config_aspm_l1ss()
737 pcie_capability_clear_and_set_word(child, PCI_EXP_LNKCTL, in pcie_config_aspm_l1ss()
739 pcie_capability_clear_and_set_word(parent, PCI_EXP_LNKCTL, in pcie_config_aspm_l1ss()
754 pci_clear_and_set_dword(parent, parent->l1ss + PCI_L1SS_CTL1, in pcie_config_aspm_l1ss()
756 pci_clear_and_set_dword(child, child->l1ss + PCI_L1SS_CTL1, in pcie_config_aspm_l1ss()
763 u16 l1ss = dev->l1ss; in pci_save_aspm_l1ss_state()
773 cap = (u32 *)&save_state->cap.data[0]; in pci_save_aspm_l1ss_state()
782 u16 l1ss = dev->l1ss; in pci_restore_aspm_l1ss_state()
791 cap = (u32 *)&save_state->cap.data[0]; in pci_restore_aspm_l1ss_state()
806 struct pci_dev *child = link->downstream, *parent = link->pdev; in pcie_config_aspm_link() local
807 struct pci_bus *linkbus = parent->subordinate; in pcie_config_aspm_link()
810 state &= (link->aspm_capable & ~link->aspm_disable); in pcie_config_aspm_link()
817 if (parent->current_state != PCI_D0 || child->current_state != PCI_D0) { in pcie_config_aspm_link()
819 state |= (link->aspm_enabled & ASPM_STATE_L1_SS_PCIPM); in pcie_config_aspm_link()
823 if (link->aspm_enabled == state) in pcie_config_aspm_link()
835 if (link->aspm_capable & ASPM_STATE_L1SS) in pcie_config_aspm_link()
845 pcie_config_aspm_dev(parent, upstream); in pcie_config_aspm_link()
846 list_for_each_entry(child, &linkbus->devices, bus_list) in pcie_config_aspm_link()
847 pcie_config_aspm_dev(child, dwstream); in pcie_config_aspm_link()
849 pcie_config_aspm_dev(parent, upstream); in pcie_config_aspm_link()
851 link->aspm_enabled = state; in pcie_config_aspm_link()
858 link = link->parent; in pcie_config_aspm_path()
864 link->pdev->link_state = NULL; in free_link_state()
870 struct pci_dev *child; in pcie_aspm_sanity_check() local
877 list_for_each_entry(child, &pdev->subordinate->devices, bus_list) { in pcie_aspm_sanity_check()
878 if (!pci_is_pcie(child)) in pcie_aspm_sanity_check()
879 return -EINVAL; in pcie_aspm_sanity_check()
884 * pre-1.1 device in pcie_aspm_sanity_check()
891 * Disable ASPM for pre-1.1 PCIe device, we follow MS to use in pcie_aspm_sanity_check()
894 pcie_capability_read_dword(child, PCI_EXP_DEVCAP, ®32); in pcie_aspm_sanity_check()
896 …pci_info(child, "disabling ASPM on pre-1.1 PCIe device. You can enable it with 'pcie_aspm=force'\… in pcie_aspm_sanity_check()
897 return -EINVAL; in pcie_aspm_sanity_check()
911 INIT_LIST_HEAD(&link->sibling); in alloc_pcie_link_state()
912 link->pdev = pdev; in alloc_pcie_link_state()
913 link->downstream = pci_function_0(pdev->subordinate); in alloc_pcie_link_state()
916 * Root Ports and PCI/PCI-X to PCIe Bridges are roots of PCIe in alloc_pcie_link_state()
924 !pdev->bus->parent->self) { in alloc_pcie_link_state()
925 link->root = link; in alloc_pcie_link_state()
927 struct pcie_link_state *parent; in alloc_pcie_link_state() local
929 parent = pdev->bus->parent->self->link_state; in alloc_pcie_link_state()
930 if (!parent) { in alloc_pcie_link_state()
935 link->parent = parent; in alloc_pcie_link_state()
936 link->root = link->parent->root; in alloc_pcie_link_state()
939 list_add(&link->sibling, &link_list); in alloc_pcie_link_state()
940 pdev->link_state = link; in alloc_pcie_link_state()
946 struct pci_dev *child; in pcie_aspm_update_sysfs_visibility() local
948 list_for_each_entry(child, &pdev->subordinate->devices, bus_list) in pcie_aspm_update_sysfs_visibility()
949 sysfs_update_group(&child->dev.kobj, &aspm_ctrl_attr_group); in pcie_aspm_update_sysfs_visibility()
965 if (pdev->link_state) in pcie_aspm_init_link_state()
978 pdev->bus->self) in pcie_aspm_init_link_state()
982 if (list_empty(&pdev->subordinate->devices)) in pcie_aspm_init_link_state()
1025 BUG_ON(root->parent); in pcie_update_aspm_capable()
1027 if (link->root != root) in pcie_update_aspm_capable()
1029 link->aspm_capable = link->aspm_support; in pcie_update_aspm_capable()
1032 struct pci_dev *child; in pcie_update_aspm_capable() local
1033 struct pci_bus *linkbus = link->pdev->subordinate; in pcie_update_aspm_capable()
1034 if (link->root != root) in pcie_update_aspm_capable()
1036 list_for_each_entry(child, &linkbus->devices, bus_list) { in pcie_update_aspm_capable()
1037 if ((pci_pcie_type(child) != PCI_EXP_TYPE_ENDPOINT) && in pcie_update_aspm_capable()
1038 (pci_pcie_type(child) != PCI_EXP_TYPE_LEG_END)) in pcie_update_aspm_capable()
1040 pcie_aspm_check_latency(child); in pcie_update_aspm_capable()
1048 struct pci_dev *parent = pdev->bus->self; in pcie_aspm_exit_link_state() local
1051 if (!parent || !parent->link_state) in pcie_aspm_exit_link_state()
1060 if (!list_empty(&parent->subordinate->devices)) in pcie_aspm_exit_link_state()
1063 link = parent->link_state; in pcie_aspm_exit_link_state()
1064 root = link->root; in pcie_aspm_exit_link_state()
1065 parent_link = link->parent; in pcie_aspm_exit_link_state()
1069 list_del(&link->sibling); in pcie_aspm_exit_link_state()
1085 struct pcie_link_state *link = pdev->link_state; in pcie_aspm_powersave_config_link()
1113 return bridge->link_state; in pcie_aspm_get_link()
1121 return -EINVAL; in __pci_disable_link_state()
1132 return -EPERM; in __pci_disable_link_state()
1139 link->aspm_disable |= ASPM_STATE_L0S; in __pci_disable_link_state()
1142 link->aspm_disable |= ASPM_STATE_L1 | ASPM_STATE_L1SS; in __pci_disable_link_state()
1144 link->aspm_disable |= ASPM_STATE_L1_1; in __pci_disable_link_state()
1146 link->aspm_disable |= ASPM_STATE_L1_2; in __pci_disable_link_state()
1148 link->aspm_disable |= ASPM_STATE_L1_1_PCIPM; in __pci_disable_link_state()
1150 link->aspm_disable |= ASPM_STATE_L1_2_PCIPM; in __pci_disable_link_state()
1154 link->clkpm_disable = 1; in __pci_disable_link_state()
1170 * pci_disable_link_state - Disable device's link state, so the link will
1191 return -EPERM; in pcie_aspm_set_policy()
1226 * pcie_aspm_enabled - Check if PCIe ASPM has been enabled for a device.
1230 * is deallocated only when the last child of the bridge (i.e., @pdev or a
1241 return link->aspm_enabled; in pcie_aspm_enabled()
1252 return sysfs_emit(buf, "%d\n", (link->aspm_enabled & state) ? 1 : 0); in aspm_attr_show_common()
1264 return -EINVAL; in aspm_attr_store_common()
1270 link->aspm_disable &= ~state; in aspm_attr_store_common()
1273 link->aspm_disable &= ~ASPM_STATE_L1; in aspm_attr_store_common()
1275 link->aspm_disable |= state; in aspm_attr_store_common()
1309 return sysfs_emit(buf, "%d\n", link->clkpm_enabled); in ASPM_ATTR()
1321 return -EINVAL; in clkpm_store()
1326 link->clkpm_disable = !state_enable; in clkpm_store()
1373 return link->clkpm_capable ? a->mode : 0; in aspm_ctrl_attrs_are_visible()
1375 return link->aspm_capable & aspm_state_map[n - 1] ? a->mode : 0; in aspm_ctrl_attrs_are_visible()