150 	pci_read_config_dword(dev, aer + PCI_ERR_CAP, &reg32);  in enable_ecrc_checking()
174 	pci_read_config_dword(dev, aer + PCI_ERR_CAP, &reg32);  in disable_ecrc_checking()
263 	pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, &status);  in pci_aer_clear_nonfatal_status()
264 	pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_SEVER, &sev);  in pci_aer_clear_nonfatal_status()
282 	pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, &status);  in pci_aer_clear_fatal_status()
283 	pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_SEVER, &sev);  in pci_aer_clear_fatal_status()
310 		pci_read_config_dword(dev, aer + PCI_ERR_ROOT_STATUS, &status);  in pci_aer_raw_clear_status()
314 	pci_read_config_dword(dev, aer + PCI_ERR_COR_STATUS, &status);  in pci_aer_raw_clear_status()
317 	pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, &status);  in pci_aer_raw_clear_status()
345 	pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, cap++);  in pci_save_aer_state()
346 	pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_SEVER, cap++);  in pci_save_aer_state()
347 	pci_read_config_dword(dev, aer + PCI_ERR_COR_MASK, cap++);  in pci_save_aer_state()
348 	pci_read_config_dword(dev, aer + PCI_ERR_CAP, cap++);  in pci_save_aer_state()
350 		pci_read_config_dword(dev, aer + PCI_ERR_ROOT_COMMAND, cap++);  in pci_save_aer_state()
876 		pci_read_config_dword(dev, aer + PCI_ERR_COR_STATUS, &status);  in is_error_source()
877 		pci_read_config_dword(dev, aer + PCI_ERR_COR_MASK, &mask);  in is_error_source()
879 		pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, &status);  in is_error_source()
880 		pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, &mask);  in is_error_source()
1067 		pci_read_config_dword(dev, aer + PCI_ERR_COR_STATUS,  in aer_get_device_error_info()
1069 		pci_read_config_dword(dev, aer + PCI_ERR_COR_MASK,  in aer_get_device_error_info()
1079 		pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS,  in aer_get_device_error_info()
1081 		pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK,  in aer_get_device_error_info()
1087 		pci_read_config_dword(dev, aer + PCI_ERR_CAP, &temp);  in aer_get_device_error_info()
1092 			pci_read_config_dword(dev,  in aer_get_device_error_info()
1094 			pci_read_config_dword(dev,  in aer_get_device_error_info()
1096 			pci_read_config_dword(dev,  in aer_get_device_error_info()
1098 			pci_read_config_dword(dev,  in aer_get_device_error_info()
1208 	pci_read_config_dword(rp, aer + PCI_ERR_ROOT_STATUS, &e_src.status);  in aer_irq()
1212 	pci_read_config_dword(rp, aer + PCI_ERR_ROOT_ERR_SRC, &e_src.id);  in aer_irq()
1279 	pci_read_config_dword(pdev, aer + PCI_ERR_ROOT_STATUS, &reg32);  in aer_enable_rootport()
1281 	pci_read_config_dword(pdev, aer + PCI_ERR_COR_STATUS, &reg32);  in aer_enable_rootport()
1283 	pci_read_config_dword(pdev, aer + PCI_ERR_UNCOR_STATUS, &reg32);  in aer_enable_rootport()
1293 	pci_read_config_dword(pdev, aer + PCI_ERR_ROOT_COMMAND, &reg32);  in aer_enable_rootport()
1317 	pci_read_config_dword(pdev, aer + PCI_ERR_ROOT_COMMAND, &reg32);  in aer_disable_rootport()
1322 	pci_read_config_dword(pdev, aer + PCI_ERR_ROOT_STATUS, &reg32);  in aer_disable_rootport()
1416 		pci_read_config_dword(root, aer + PCI_ERR_ROOT_COMMAND, &reg32);  in aer_root_reset()
1435 		pci_read_config_dword(root, aer + PCI_ERR_ROOT_STATUS, &reg32);  in aer_root_reset()
1439 		pci_read_config_dword(root, aer + PCI_ERR_ROOT_COMMAND, &reg32);  in aer_root_reset()