1 // SPDX-License-Identifier: GPL-2.0
3  * PCI Bus Services, see include/linux/pci.h for further explanation.
5  * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
6  * David Mosberger-Tang
8  * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
18 #include <linux/pci.h>
35 #include "pci.h"
62 	struct pci_dev *dev;  member
67 static void pci_dev_d3_sleep(struct pci_dev *dev)  in pci_dev_d3_sleep()  argument
69 	unsigned int delay_ms = max(dev->d3hot_delay, pci_pm_d3hot_delay);  in pci_dev_d3_sleep()
80 bool pci_reset_supported(struct pci_dev *dev)  in pci_reset_supported()  argument
82 	return dev->reset_methods[0] != 0;  in pci_reset_supported()
91 /* pci=cbmemsize=nnM,cbiosize=nn can override this */
101  * pci=hpmmiosize=nnM overrides non-prefetchable MMIO size,
102  * pci=hpmmioprefsize=nnM overrides prefetchable MMIO size;
103  * pci=hpmemsize=nnM overrides both
112 /* PCIe MPS/MRRS strategy; can be overridden by kernel command-line param */
127  * all pci devices agree on the same value.  Arch can override either
129  * measured in 32-bit words, not bytes.
146 /* If set, the PCI config space of each device is printed during boot. */
174  * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
175  * @bus: pointer to PCI bus structure to search
177  * Given a PCI bus, returns the highest PCI bus number present in the set
178  * including the given PCI bus and its list of child PCI buses.
185 	max = bus->busn_res.end;  in pci_bus_max_busnr()
186 	list_for_each_entry(tmp, &bus->children, node) {  in pci_bus_max_busnr()
196  * pci_status_get_and_clear_errors - return and clear error bits in PCI_STATUS
197  * @pdev: the PCI device
208 		return -EIO;  in pci_status_get_and_clear_errors()
222 	struct resource *res = &pdev->resource[bar];  in __pci_ioremap_resource()
223 	resource_size_t start = res->start;  in __pci_ioremap_resource()
229 	if (res->flags & IORESOURCE_UNSET || !(res->flags & IORESOURCE_MEM)) {  in __pci_ioremap_resource()
254  * pci_dev_str_match_path - test if a path string matches a device
255  * @dev: the PCI device to test
260  * path of device/function addresses matches a PCI device. The string must
265  * A path for a device can be obtained using 'lspci -t'.  Using a path
272 static int pci_dev_str_match_path(struct pci_dev *dev, const char *path,  in pci_dev_str_match_path()  argument
282 	wpath = kmemdup_nul(path, *endptr - path, GFP_ATOMIC);  in pci_dev_str_match_path()
284 		return -ENOMEM;  in pci_dev_str_match_path()
292 			ret = -EINVAL;  in pci_dev_str_match_path()
296 		if (dev->devfn != PCI_DEVFN(slot, func)) {  in pci_dev_str_match_path()
307 		dev = pci_upstream_bridge(dev);  in pci_dev_str_match_path()
308 		if (!dev) {  in pci_dev_str_match_path()
322 			ret = -EINVAL;  in pci_dev_str_match_path()
327 	ret = (seg == pci_domain_nr(dev->bus) &&  in pci_dev_str_match_path()
328 	       bus == dev->bus->number &&  in pci_dev_str_match_path()
329 	       dev->devfn == PCI_DEVFN(slot, func));  in pci_dev_str_match_path()
337  * pci_dev_str_match - test if a string matches a device
338  * @dev: the PCI device to test
343  * PCI device. The string may be of one of the following formats:
346  *   pci:<vendor>:<device>[:<subvendor>:<subdevice>]
348  * The first format specifies a PCI bus/device/function address which
352  * bus renumbering issues, a path of PCI device/function numbers may be used
354  * through the use of 'lspci -t'.
359  * in-kernel code that uses PCI_ANY_ID which is ~0; this is for
366 static int pci_dev_str_match(struct pci_dev *dev, const char *p,  in pci_dev_str_match()  argument
373 	if (strncmp(p, "pci:", 4) == 0) {  in pci_dev_str_match()
374 		/* PCI vendor/device (subvendor/subdevice) IDs are specified */  in pci_dev_str_match()
381 				return -EINVAL;  in pci_dev_str_match()
389 		if ((!vendor || vendor == dev->vendor) &&  in pci_dev_str_match()
390 		    (!device || device == dev->device) &&  in pci_dev_str_match()
392 			    subsystem_vendor == dev->subsystem_vendor) &&  in pci_dev_str_match()
394 			    subsystem_device == dev->subsystem_device))  in pci_dev_str_match()
398 		 * PCI Bus, Device, Function IDs are specified  in pci_dev_str_match()
401 		ret = pci_dev_str_match_path(dev, p, &p);  in pci_dev_str_match()
424 	while ((*ttl)--) {  in __pci_find_next_cap_ttl()
448 u8 pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)  in pci_find_next_capability()  argument
450 	return __pci_find_next_cap(dev->bus, dev->devfn,  in pci_find_next_capability()
476  * pci_find_capability - query for devices' capabilities
477  * @dev: PCI device to query
480  * Tell if a device supports a given PCI capability.
482  * device's PCI configuration space or 0 in case the device does not
491  *  %PCI_CAP_ID_PCIX         PCI-X
492  *  %PCI_CAP_ID_EXP          PCI Express
494 u8 pci_find_capability(struct pci_dev *dev, int cap)  in pci_find_capability()  argument
498 	pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);  in pci_find_capability()
500 		pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);  in pci_find_capability()
507  * pci_bus_find_capability - query for devices' capabilities
508  * @bus: the PCI bus to query
509  * @devfn: PCI device to query
512  * Like pci_find_capability() but works for PCI devices that do not have a
516  * device's PCI configuration space or 0 in case the device does not
534  * pci_find_next_ext_capability - Find an extended capability
535  * @dev: PCI device to query
540  * within the device's PCI configuration space or 0 if the device does
542  * vendor-specific capability, and this provides a way to find them all.
544 u16 pci_find_next_ext_capability(struct pci_dev *dev, u16 start, int cap)  in pci_find_next_ext_capability()  argument
551 	ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;  in pci_find_next_ext_capability()
553 	if (dev->cfg_size <= PCI_CFG_SPACE_SIZE)  in pci_find_next_ext_capability()
559 	if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)  in pci_find_next_ext_capability()
569 	while (ttl-- > 0) {  in pci_find_next_ext_capability()
577 		if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)  in pci_find_next_ext_capability()
586  * pci_find_ext_capability - Find an extended capability
587  * @dev: PCI device to query
591  * within the device's PCI configuration space or 0 if the device does
599 u16 pci_find_ext_capability(struct pci_dev *dev, int cap)  in pci_find_ext_capability()  argument
601 	return pci_find_next_ext_capability(dev, 0, cap);  in pci_find_ext_capability()
606  * pci_get_dsn - Read and return the 8-byte Device Serial Number
607  * @dev: PCI device to query
614 u64 pci_get_dsn(struct pci_dev *dev)  in pci_get_dsn()  argument
620 	pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_DSN);  in pci_get_dsn()
630 	pci_read_config_dword(dev, pos, &dword);  in pci_get_dsn()
632 	pci_read_config_dword(dev, pos + 4, &dword);  in pci_get_dsn()
639 static u8 __pci_find_next_ht_cap(struct pci_dev *dev, u8 pos, int ht_cap)  in __pci_find_next_ht_cap()  argument
649 	pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,  in __pci_find_next_ht_cap()
652 		rc = pci_read_config_byte(dev, pos + 3, &cap);  in __pci_find_next_ht_cap()
659 		pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,  in __pci_find_next_ht_cap()
668  * pci_find_next_ht_capability - query a device's HyperTransport capabilities
669  * @dev: PCI device to query
677  * NB. To be 100% safe against broken PCI devices, the caller should take
680 u8 pci_find_next_ht_capability(struct pci_dev *dev, u8 pos, int ht_cap)  in pci_find_next_ht_capability()  argument
682 	return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);  in pci_find_next_ht_capability()
687  * pci_find_ht_capability - query a device's HyperTransport capabilities
688  * @dev: PCI device to query
692  * Returns an address within the device's PCI configuration space
694  * The address points to the PCI capability, of type PCI_CAP_ID_HT,
697 u8 pci_find_ht_capability(struct pci_dev *dev, int ht_cap)  in pci_find_ht_capability()  argument
701 	pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);  in pci_find_ht_capability()
703 		pos = __pci_find_next_ht_cap(dev, pos, ht_cap);  in pci_find_ht_capability()
710  * pci_find_vsec_capability - Find a vendor-specific extended capability
711  * @dev: PCI device to query
713  * @cap: Vendor-specific capability ID
715  * If @dev has Vendor ID @vendor, search for a VSEC capability with
719 u16 pci_find_vsec_capability(struct pci_dev *dev, u16 vendor, int cap)  in pci_find_vsec_capability()  argument
724 	if (vendor != dev->vendor)  in pci_find_vsec_capability()
727 	while ((vsec = pci_find_next_ext_capability(dev, vsec,  in pci_find_vsec_capability()
729 		if (pci_read_config_dword(dev, vsec + PCI_VNDR_HEADER,  in pci_find_vsec_capability()
740  * pci_find_dvsec_capability - Find DVSEC for vendor
741  * @dev: PCI device to query
743  * @dvsec: Designated Vendor-specific capability ID
748 u16 pci_find_dvsec_capability(struct pci_dev *dev, u16 vendor, u16 dvsec)  in pci_find_dvsec_capability()  argument
752 	pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_DVSEC);  in pci_find_dvsec_capability()
759 		pci_read_config_word(dev, pos + PCI_DVSEC_HEADER1, &v);  in pci_find_dvsec_capability()
760 		pci_read_config_word(dev, pos + PCI_DVSEC_HEADER2, &id);  in pci_find_dvsec_capability()
764 		pos = pci_find_next_ext_capability(dev, pos, PCI_EXT_CAP_ID_DVSEC);  in pci_find_dvsec_capability()
772  * pci_find_parent_resource - return resource region of parent bus of given
774  * @dev: PCI device structure contains resources to be searched
780 struct resource *pci_find_parent_resource(const struct pci_dev *dev,  in pci_find_parent_resource()  argument
783 	const struct pci_bus *bus = dev->bus;  in pci_find_parent_resource()
796 			if (r->flags & IORESOURCE_PREFETCH &&  in pci_find_parent_resource()
797 			    !(res->flags & IORESOURCE_PREFETCH))  in pci_find_parent_resource()
802 			 * be both a positively-decoded aperture and a  in pci_find_parent_resource()
803 			 * subtractively-decoded region that contain the BAR.  in pci_find_parent_resource()
804 			 * We want the positively-decoded one, so this depends  in pci_find_parent_resource()
816  * pci_find_resource - Return matching PCI device resource
817  * @dev: PCI device to query
820  * Goes over standard PCI resources (BARs) and checks if the given resource
824 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res)  in pci_find_resource()  argument
829 		struct resource *r = &dev->resource[i];  in pci_find_resource()
831 		if (r->start && resource_contains(r, res))  in pci_find_resource()
840  * pci_wait_for_pending - wait for @mask bit(s) to clear in status word @pos
841  * @dev: the PCI device to operate on
847 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask)  in pci_wait_for_pending()  argument
855 			msleep((1 << (i - 1)) * 100);  in pci_wait_for_pending()
857 		pci_read_config_word(dev, pos, &status);  in pci_wait_for_pending()
868  * pci_request_acs - ask for ACS to be enabled if supported
878  * pci_disable_acs_redir - disable ACS redirect capabilities
879  * @dev: the PCI device
883 static void pci_disable_acs_redir(struct pci_dev *dev)  in pci_disable_acs_redir()  argument
895 		ret = pci_dev_str_match(dev, p, &p);  in pci_disable_acs_redir()
897 			pr_info_once("PCI: Can't parse disable_acs_redir parameter: %s\n",  in pci_disable_acs_redir()
916 	if (!pci_dev_specific_disable_acs_redir(dev))  in pci_disable_acs_redir()
919 	pos = dev->acs_cap;  in pci_disable_acs_redir()
921 …pci_warn(dev, "cannot disable ACS redirect for this hardware as it does not have ACS capabilities\…  in pci_disable_acs_redir()
925 	pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);  in pci_disable_acs_redir()
930 	pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);  in pci_disable_acs_redir()
932 	pci_info(dev, "disabled ACS redirect\n");  in pci_disable_acs_redir()
936  * pci_std_enable_acs - enable ACS on devices using standard ACS capabilities
937  * @dev: the PCI device
939 static void pci_std_enable_acs(struct pci_dev *dev)  in pci_std_enable_acs()  argument
945 	pos = dev->acs_cap;  in pci_std_enable_acs()
949 	pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap);  in pci_std_enable_acs()
950 	pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);  in pci_std_enable_acs()
965 	if (pci_ats_disabled() || dev->external_facing || dev->untrusted)  in pci_std_enable_acs()
968 	pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);  in pci_std_enable_acs()
972  * pci_enable_acs - enable ACS if hardware support it
973  * @dev: the PCI device
975 static void pci_enable_acs(struct pci_dev *dev)  in pci_enable_acs()  argument
980 	if (!pci_dev_specific_enable_acs(dev))  in pci_enable_acs()
983 	pci_std_enable_acs(dev);  in pci_enable_acs()
993 	pci_disable_acs_redir(dev);  in pci_enable_acs()
997  * pci_restore_bars - restore a device's BAR values (e.g. after wake-up)
998  * @dev: PCI device to have its BARs restored
1003 static void pci_restore_bars(struct pci_dev *dev)  in pci_restore_bars()  argument
1008 		pci_update_resource(dev, i);  in pci_restore_bars()
1011 static inline bool platform_pci_power_manageable(struct pci_dev *dev)  in platform_pci_power_manageable()  argument
1016 	return acpi_pci_power_manageable(dev);  in platform_pci_power_manageable()
1019 static inline int platform_pci_set_power_state(struct pci_dev *dev,  in platform_pci_set_power_state()  argument
1023 		return mid_pci_set_power_state(dev, t);  in platform_pci_set_power_state()
1025 	return acpi_pci_set_power_state(dev, t);  in platform_pci_set_power_state()
1028 static inline pci_power_t platform_pci_get_power_state(struct pci_dev *dev)  in platform_pci_get_power_state()  argument
1031 		return mid_pci_get_power_state(dev);  in platform_pci_get_power_state()
1033 	return acpi_pci_get_power_state(dev);  in platform_pci_get_power_state()
1036 static inline void platform_pci_refresh_power_state(struct pci_dev *dev)  in platform_pci_refresh_power_state()  argument
1039 		acpi_pci_refresh_power_state(dev);  in platform_pci_refresh_power_state()
1042 static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev)  in platform_pci_choose_state()  argument
1047 	return acpi_pci_choose_state(dev);  in platform_pci_choose_state()
1050 static inline int platform_pci_set_wakeup(struct pci_dev *dev, bool enable)  in platform_pci_set_wakeup()  argument
1055 	return acpi_pci_wakeup(dev, enable);  in platform_pci_set_wakeup()
1058 static inline bool platform_pci_need_resume(struct pci_dev *dev)  in platform_pci_need_resume()  argument
1063 	return acpi_pci_need_resume(dev);  in platform_pci_need_resume()
1066 static inline bool platform_pci_bridge_d3(struct pci_dev *dev)  in platform_pci_bridge_d3()  argument
1071 	return acpi_pci_bridge_d3(dev);  in platform_pci_bridge_d3()
1075  * pci_update_current_state - Read power state of given device and cache it
1076  * @dev: PCI device to handle.
1086 void pci_update_current_state(struct pci_dev *dev, pci_power_t state)  in pci_update_current_state()  argument
1088 	if (platform_pci_get_power_state(dev) == PCI_D3cold) {  in pci_update_current_state()
1089 		dev->current_state = PCI_D3cold;  in pci_update_current_state()
1090 	} else if (dev->pm_cap) {  in pci_update_current_state()
1093 		pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);  in pci_update_current_state()
1095 			dev->current_state = PCI_D3cold;  in pci_update_current_state()
1098 		dev->current_state = pmcsr & PCI_PM_CTRL_STATE_MASK;  in pci_update_current_state()
1100 		dev->current_state = state;  in pci_update_current_state()
1105  * pci_refresh_power_state - Refresh the given device's power state data
1106  * @dev: Target PCI device.
1109  * pci_update_current_state() to update its current PCI power state.
1111 void pci_refresh_power_state(struct pci_dev *dev)  in pci_refresh_power_state()  argument
1113 	platform_pci_refresh_power_state(dev);  in pci_refresh_power_state()
1114 	pci_update_current_state(dev, dev->current_state);  in pci_refresh_power_state()
1118  * pci_platform_power_transition - Use platform to change device power state
1119  * @dev: PCI device to handle.
1122 int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state)  in pci_platform_power_transition()  argument
1126 	error = platform_pci_set_power_state(dev, state);  in pci_platform_power_transition()
1128 		pci_update_current_state(dev, state);  in pci_platform_power_transition()
1129 	else if (!dev->pm_cap) /* Fall back to PCI_D0 */  in pci_platform_power_transition()
1130 		dev->current_state = PCI_D0;  in pci_platform_power_transition()
1138 	pm_request_resume(&pci_dev->dev);  in pci_resume_one()
1143  * pci_resume_bus - Walk given bus and runtime resume devices on it
1152 static int pci_dev_wait(struct pci_dev *dev, char *reset_type, int timeout)  in pci_dev_wait()  argument
1165 	 * Wait for the device to return a non-CRS completion.  Read the  in pci_dev_wait()
1169 	pci_read_config_dword(dev, PCI_COMMAND, &id);  in pci_dev_wait()
1172 			pci_warn(dev, "not ready %dms after %s; giving up\n",  in pci_dev_wait()
1173 				 delay - 1, reset_type);  in pci_dev_wait()
1174 			return -ENOTTY;  in pci_dev_wait()
1178 			pci_info(dev, "not ready %dms after %s; waiting\n",  in pci_dev_wait()
1179 				 delay - 1, reset_type);  in pci_dev_wait()
1183 		pci_read_config_dword(dev, PCI_COMMAND, &id);  in pci_dev_wait()
1187 		pci_info(dev, "ready %dms after %s\n", delay - 1,  in pci_dev_wait()
1194  * pci_power_up - Put the given device into D0
1195  * @dev: PCI device to power up
1200 int pci_power_up(struct pci_dev *dev)  in pci_power_up()  argument
1206 	platform_pci_set_power_state(dev, PCI_D0);  in pci_power_up()
1208 	if (!dev->pm_cap) {  in pci_power_up()
1209 		state = platform_pci_get_power_state(dev);  in pci_power_up()
1211 			dev->current_state = PCI_D0;  in pci_power_up()
1213 			dev->current_state = state;  in pci_power_up()
1218 		return -EIO;  in pci_power_up()
1221 	pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);  in pci_power_up()
1223 		pci_err(dev, "Unable to change power state from %s to D0, device inaccessible\n",  in pci_power_up()
1224 			pci_power_name(dev->current_state));  in pci_power_up()
1225 		dev->current_state = PCI_D3cold;  in pci_power_up()
1226 		return -EIO;  in pci_power_up()
1231 	need_restore = (state == PCI_D3hot || dev->current_state >= PCI_D3hot) &&  in pci_power_up()
1241 	pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, 0);  in pci_power_up()
1243 	/* Mandatory transition delays; see PCI PM 1.2. */  in pci_power_up()
1245 		pci_dev_d3_sleep(dev);  in pci_power_up()
1250 	dev->current_state = PCI_D0;  in pci_power_up()
1258  * pci_set_full_power_state - Put a PCI device into D0 and update its state
1259  * @dev: PCI device to power up
1261  * Call pci_power_up() to put @dev into D0, read from its PCI_PM_CTRL register
1269 static int pci_set_full_power_state(struct pci_dev *dev)  in pci_set_full_power_state()  argument
1274 	ret = pci_power_up(dev);  in pci_set_full_power_state()
1278 	pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);  in pci_set_full_power_state()
1279 	dev->current_state = pmcsr & PCI_PM_CTRL_STATE_MASK;  in pci_set_full_power_state()
1280 	if (dev->current_state != PCI_D0) {  in pci_set_full_power_state()
1281 		pci_info_ratelimited(dev, "Refused to change power state from %s to D0\n",  in pci_set_full_power_state()
1282 				     pci_power_name(dev->current_state));  in pci_set_full_power_state()
1285 		 * According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT  in pci_set_full_power_state()
1297 		pci_restore_bars(dev);  in pci_set_full_power_state()
1304  * __pci_dev_set_current_state - Set current state of a PCI device
1305  * @dev: Device to handle
1308 static int __pci_dev_set_current_state(struct pci_dev *dev, void *data)  in __pci_dev_set_current_state()  argument
1312 	dev->current_state = state;  in __pci_dev_set_current_state()
1317  * pci_bus_set_current_state - Walk given bus and set current state of devices
1328  * pci_set_low_power_state - Put a PCI device into a low-power state.
1329  * @dev: PCI device to handle.
1330  * @state: PCI power state (D1, D2, D3hot) to put the device into.
1332  * Use the device's PCI_PM_CTRL register to put it into a low-power state.
1335  * -EINVAL if the requested state is invalid.
1336  * -EIO if device does not support PCI PM or its PM capabilities register has a
1341 static int pci_set_low_power_state(struct pci_dev *dev, pci_power_t state)  in pci_set_low_power_state()  argument
1345 	if (!dev->pm_cap)  in pci_set_low_power_state()
1346 		return -EIO;  in pci_set_low_power_state()
1350 	 * we're already in a low-power state, we can only go deeper.  E.g.,  in pci_set_low_power_state()
1354 	if (dev->current_state <= PCI_D3cold && dev->current_state > state) {  in pci_set_low_power_state()
1355 		pci_dbg(dev, "Invalid power transition (from %s to %s)\n",  in pci_set_low_power_state()
1356 			pci_power_name(dev->current_state),  in pci_set_low_power_state()
1358 		return -EINVAL;  in pci_set_low_power_state()
1362 	if ((state == PCI_D1 && !dev->d1_support)  in pci_set_low_power_state()
1363 	   || (state == PCI_D2 && !dev->d2_support))  in pci_set_low_power_state()
1364 		return -EIO;  in pci_set_low_power_state()
1366 	pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);  in pci_set_low_power_state()
1368 		pci_err(dev, "Unable to change power state from %s to %s, device inaccessible\n",  in pci_set_low_power_state()
1369 			pci_power_name(dev->current_state),  in pci_set_low_power_state()
1371 		dev->current_state = PCI_D3cold;  in pci_set_low_power_state()
1372 		return -EIO;  in pci_set_low_power_state()
1379 	pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);  in pci_set_low_power_state()
1381 	/* Mandatory power management transition delays; see PCI PM 1.2. */  in pci_set_low_power_state()
1383 		pci_dev_d3_sleep(dev);  in pci_set_low_power_state()
1387 	pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);  in pci_set_low_power_state()
1388 	dev->current_state = pmcsr & PCI_PM_CTRL_STATE_MASK;  in pci_set_low_power_state()
1389 	if (dev->current_state != state)  in pci_set_low_power_state()
1390 		pci_info_ratelimited(dev, "Refused to change power state from %s to %s\n",  in pci_set_low_power_state()
1391 				     pci_power_name(dev->current_state),  in pci_set_low_power_state()
1398  * pci_set_power_state - Set the power state of a PCI device
1399  * @dev: PCI device to handle.
1400  * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
1403  * the device's PCI PM registers.
1406  * -EINVAL if the requested state is invalid.
1407  * -EIO if device does not support PCI PM or its PM capabilities register has a
1414 int pci_set_power_state(struct pci_dev *dev, pci_power_t state)  in pci_set_power_state()  argument
1423 	else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))  in pci_set_power_state()
1426 		 * If the device or the parent bridge do not support PCI  in pci_set_power_state()
1434 	if (dev->current_state == state)  in pci_set_power_state()
1438 		return pci_set_full_power_state(dev);  in pci_set_power_state()
1444 	if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))  in pci_set_power_state()
1452 		error = pci_set_low_power_state(dev, PCI_D3hot);  in pci_set_power_state()
1454 		if (pci_platform_power_transition(dev, PCI_D3cold))  in pci_set_power_state()
1458 		if (dev->current_state == PCI_D3cold)  in pci_set_power_state()
1459 			pci_bus_set_current_state(dev->subordinate, PCI_D3cold);  in pci_set_power_state()
1461 		error = pci_set_low_power_state(dev, state);  in pci_set_power_state()
1463 		if (pci_platform_power_transition(dev, state))  in pci_set_power_state()
1478 	hlist_for_each_entry(tmp, &pci_dev->saved_cap_space, next) {  in _pci_find_saved_cap()
1479 		if (tmp->cap.cap_extended == extended && tmp->cap.cap_nr == cap)  in _pci_find_saved_cap()
1485 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap)  in pci_find_saved_cap()  argument
1487 	return _pci_find_saved_cap(dev, cap, false);  in pci_find_saved_cap()
1490 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, u16 cap)  in pci_find_saved_ext_cap()  argument
1492 	return _pci_find_saved_cap(dev, cap, true);  in pci_find_saved_ext_cap()
1495 static int pci_save_pcie_state(struct pci_dev *dev)  in pci_save_pcie_state()  argument
1501 	if (!pci_is_pcie(dev))  in pci_save_pcie_state()
1504 	save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);  in pci_save_pcie_state()
1506 		pci_err(dev, "buffer not found in %s\n", __func__);  in pci_save_pcie_state()
1507 		return -ENOMEM;  in pci_save_pcie_state()
1510 	cap = (u16 *)&save_state->cap.data[0];  in pci_save_pcie_state()
1511 	pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &cap[i++]);  in pci_save_pcie_state()
1512 	pcie_capability_read_word(dev, PCI_EXP_LNKCTL, &cap[i++]);  in pci_save_pcie_state()
1513 	pcie_capability_read_word(dev, PCI_EXP_SLTCTL, &cap[i++]);  in pci_save_pcie_state()
1514 	pcie_capability_read_word(dev, PCI_EXP_RTCTL,  &cap[i++]);  in pci_save_pcie_state()
1515 	pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &cap[i++]);  in pci_save_pcie_state()
1516 	pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &cap[i++]);  in pci_save_pcie_state()
1517 	pcie_capability_read_word(dev, PCI_EXP_SLTCTL2, &cap[i++]);  in pci_save_pcie_state()
1522 void pci_bridge_reconfigure_ltr(struct pci_dev *dev)  in pci_bridge_reconfigure_ltr()  argument
1528 	bridge = pci_upstream_bridge(dev);  in pci_bridge_reconfigure_ltr()
1529 	if (bridge && bridge->ltr_path) {  in pci_bridge_reconfigure_ltr()
1532 			pci_dbg(bridge, "re-enabling LTR\n");  in pci_bridge_reconfigure_ltr()
1540 static void pci_restore_pcie_state(struct pci_dev *dev)  in pci_restore_pcie_state()  argument
1546 	save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);  in pci_restore_pcie_state()
1552 	 * Check and re-configure the bit here before restoring device.  in pci_restore_pcie_state()
1555 	pci_bridge_reconfigure_ltr(dev);  in pci_restore_pcie_state()
1557 	cap = (u16 *)&save_state->cap.data[0];  in pci_restore_pcie_state()
1558 	pcie_capability_write_word(dev, PCI_EXP_DEVCTL, cap[i++]);  in pci_restore_pcie_state()
1559 	pcie_capability_write_word(dev, PCI_EXP_LNKCTL, cap[i++]);  in pci_restore_pcie_state()
1560 	pcie_capability_write_word(dev, PCI_EXP_SLTCTL, cap[i++]);  in pci_restore_pcie_state()
1561 	pcie_capability_write_word(dev, PCI_EXP_RTCTL, cap[i++]);  in pci_restore_pcie_state()
1562 	pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, cap[i++]);  in pci_restore_pcie_state()
1563 	pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, cap[i++]);  in pci_restore_pcie_state()
1564 	pcie_capability_write_word(dev, PCI_EXP_SLTCTL2, cap[i++]);  in pci_restore_pcie_state()
1567 static int pci_save_pcix_state(struct pci_dev *dev)  in pci_save_pcix_state()  argument
1572 	pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);  in pci_save_pcix_state()
1576 	save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);  in pci_save_pcix_state()
1578 		pci_err(dev, "buffer not found in %s\n", __func__);  in pci_save_pcix_state()
1579 		return -ENOMEM;  in pci_save_pcix_state()
1582 	pci_read_config_word(dev, pos + PCI_X_CMD,  in pci_save_pcix_state()
1583 			     (u16 *)save_state->cap.data);  in pci_save_pcix_state()
1588 static void pci_restore_pcix_state(struct pci_dev *dev)  in pci_restore_pcix_state()  argument
1594 	save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);  in pci_restore_pcix_state()
1595 	pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);  in pci_restore_pcix_state()
1598 	cap = (u16 *)&save_state->cap.data[0];  in pci_restore_pcix_state()
1600 	pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);  in pci_restore_pcix_state()
1603 static void pci_save_ltr_state(struct pci_dev *dev)  in pci_save_ltr_state()  argument
1609 	if (!pci_is_pcie(dev))  in pci_save_ltr_state()
1612 	ltr = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR);  in pci_save_ltr_state()
1616 	save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_LTR);  in pci_save_ltr_state()
1618 		pci_err(dev, "no suspend buffer for LTR; ASPM issues possible after resume\n");  in pci_save_ltr_state()
1623 	cap = &save_state->cap.data[0];  in pci_save_ltr_state()
1624 	pci_read_config_dword(dev, ltr + PCI_LTR_MAX_SNOOP_LAT, cap);  in pci_save_ltr_state()
1627 static void pci_restore_ltr_state(struct pci_dev *dev)  in pci_restore_ltr_state()  argument
1633 	save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_LTR);  in pci_restore_ltr_state()
1634 	ltr = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR);  in pci_restore_ltr_state()
1639 	cap = &save_state->cap.data[0];  in pci_restore_ltr_state()
1640 	pci_write_config_dword(dev, ltr + PCI_LTR_MAX_SNOOP_LAT, *cap);  in pci_restore_ltr_state()
1644  * pci_save_state - save the PCI configuration space of a device before
1646  * @dev: PCI device that we're dealing with
1648 int pci_save_state(struct pci_dev *dev)  in pci_save_state()  argument
1653 		pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]);  in pci_save_state()
1654 		pci_dbg(dev, "saving config space at offset %#x (reading %#x)\n",  in pci_save_state()
1655 			i * 4, dev->saved_config_space[i]);  in pci_save_state()
1657 	dev->state_saved = true;  in pci_save_state()
1659 	i = pci_save_pcie_state(dev);  in pci_save_state()
1663 	i = pci_save_pcix_state(dev);  in pci_save_state()
1667 	pci_save_ltr_state(dev);  in pci_save_state()
1668 	pci_save_aspm_l1ss_state(dev);  in pci_save_state()
1669 	pci_save_dpc_state(dev);  in pci_save_state()
1670 	pci_save_aer_state(dev);  in pci_save_state()
1671 	pci_save_ptm_state(dev);  in pci_save_state()
1672 	return pci_save_vc_state(dev);  in pci_save_state()
1689 		if (retry-- <= 0)  in pci_restore_config_dword()
1706 	for (index = end; index >= start; index--)  in pci_restore_config_space_range()
1708 					 pdev->saved_config_space[index],  in pci_restore_config_space_range()
1714 	if (pdev->hdr_type == PCI_HEADER_TYPE_NORMAL) {  in pci_restore_config_space()
1719 	} else if (pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {  in pci_restore_config_space()
1724 		 * issues on Intel PCI bridges that occur when these  in pci_restore_config_space()
1753 		res = pdev->resource + bar_idx;  in pci_restore_rebar_state()
1762  * pci_restore_state - Restore the saved state of a PCI device
1763  * @dev: PCI device that we're dealing with
1765 void pci_restore_state(struct pci_dev *dev)  in pci_restore_state()  argument
1767 	if (!dev->state_saved)  in pci_restore_state()
1774 	pci_restore_ltr_state(dev);  in pci_restore_state()
1775 	pci_restore_aspm_l1ss_state(dev);  in pci_restore_state()
1777 	pci_restore_pcie_state(dev);  in pci_restore_state()
1778 	pci_restore_pasid_state(dev);  in pci_restore_state()
1779 	pci_restore_pri_state(dev);  in pci_restore_state()
1780 	pci_restore_ats_state(dev);  in pci_restore_state()
1781 	pci_restore_vc_state(dev);  in pci_restore_state()
1782 	pci_restore_rebar_state(dev);  in pci_restore_state()
1783 	pci_restore_dpc_state(dev);  in pci_restore_state()
1784 	pci_restore_ptm_state(dev);  in pci_restore_state()
1786 	pci_aer_clear_status(dev);  in pci_restore_state()
1787 	pci_restore_aer_state(dev);  in pci_restore_state()
1789 	pci_restore_config_space(dev);  in pci_restore_state()
1791 	pci_restore_pcix_state(dev);  in pci_restore_state()
1792 	pci_restore_msi_state(dev);  in pci_restore_state()
1795 	pci_enable_acs(dev);  in pci_restore_state()
1796 	pci_restore_iov_state(dev);  in pci_restore_state()
1798 	dev->state_saved = false;  in pci_restore_state()
1808  * pci_store_saved_state - Allocate and return an opaque struct containing
1810  * @dev: PCI device that we're dealing with
1814 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev)  in pci_store_saved_state()  argument
1821 	if (!dev->state_saved)  in pci_store_saved_state()
1826 	hlist_for_each_entry(tmp, &dev->saved_cap_space, next)  in pci_store_saved_state()
1827 		size += sizeof(struct pci_cap_saved_data) + tmp->cap.size;  in pci_store_saved_state()
1833 	memcpy(state->config_space, dev->saved_config_space,  in pci_store_saved_state()
1834 	       sizeof(state->config_space));  in pci_store_saved_state()
1836 	cap = state->cap;  in pci_store_saved_state()
1837 	hlist_for_each_entry(tmp, &dev->saved_cap_space, next) {  in pci_store_saved_state()
1838 		size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size;  in pci_store_saved_state()
1839 		memcpy(cap, &tmp->cap, len);  in pci_store_saved_state()
1849  * pci_load_saved_state - Reload the provided save state into struct pci_dev.
1850  * @dev: PCI device that we're dealing with
1853 int pci_load_saved_state(struct pci_dev *dev,  in pci_load_saved_state()  argument
1858 	dev->state_saved = false;  in pci_load_saved_state()
1863 	memcpy(dev->saved_config_space, state->config_space,  in pci_load_saved_state()
1864 	       sizeof(state->config_space));  in pci_load_saved_state()
1866 	cap = state->cap;  in pci_load_saved_state()
1867 	while (cap->size) {  in pci_load_saved_state()
1870 		tmp = _pci_find_saved_cap(dev, cap->cap_nr, cap->cap_extended);  in pci_load_saved_state()
1871 		if (!tmp || tmp->cap.size != cap->size)  in pci_load_saved_state()
1872 			return -EINVAL;  in pci_load_saved_state()
1874 		memcpy(tmp->cap.data, cap->data, tmp->cap.size);  in pci_load_saved_state()
1876 		       sizeof(struct pci_cap_saved_data) + cap->size);  in pci_load_saved_state()
1879 	dev->state_saved = true;  in pci_load_saved_state()
1885  * pci_load_and_free_saved_state - Reload the save state pointed to by state,
1887  * @dev: PCI device that we're dealing with
1890 int pci_load_and_free_saved_state(struct pci_dev *dev,  in pci_load_and_free_saved_state()  argument
1893 	int ret = pci_load_saved_state(dev, *state);  in pci_load_and_free_saved_state()
1900 int __weak pcibios_enable_device(struct pci_dev *dev, int bars)  in pcibios_enable_device()  argument
1902 	return pci_enable_resources(dev, bars);  in pcibios_enable_device()
1905 static int do_pci_enable_device(struct pci_dev *dev, int bars)  in do_pci_enable_device()  argument
1912 	err = pci_set_power_state(dev, PCI_D0);  in do_pci_enable_device()
1913 	if (err < 0 && err != -EIO)  in do_pci_enable_device()
1916 	bridge = pci_upstream_bridge(dev);  in do_pci_enable_device()
1920 	err = pcibios_enable_device(dev, bars);  in do_pci_enable_device()
1923 	pci_fixup_device(pci_fixup_enable, dev);  in do_pci_enable_device()
1925 	if (dev->msi_enabled || dev->msix_enabled)  in do_pci_enable_device()
1928 	pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);  in do_pci_enable_device()
1930 		pci_read_config_word(dev, PCI_COMMAND, &cmd);  in do_pci_enable_device()
1932 			pci_write_config_word(dev, PCI_COMMAND,  in do_pci_enable_device()
1940  * pci_reenable_device - Resume abandoned device
1941  * @dev: PCI device to be resumed
1946 int pci_reenable_device(struct pci_dev *dev)  in pci_reenable_device()  argument
1948 	if (pci_is_enabled(dev))  in pci_reenable_device()
1949 		return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);  in pci_reenable_device()
1954 static void pci_enable_bridge(struct pci_dev *dev)  in pci_enable_bridge()  argument
1959 	bridge = pci_upstream_bridge(dev);  in pci_enable_bridge()
1963 	if (pci_is_enabled(dev)) {  in pci_enable_bridge()
1964 		if (!dev->is_busmaster)  in pci_enable_bridge()
1965 			pci_set_master(dev);  in pci_enable_bridge()
1969 	retval = pci_enable_device(dev);  in pci_enable_bridge()
1971 		pci_err(dev, "Error enabling bridge (%d), continuing\n",  in pci_enable_bridge()
1973 	pci_set_master(dev);  in pci_enable_bridge()
1976 static int pci_enable_device_flags(struct pci_dev *dev, unsigned long flags)  in pci_enable_device_flags()  argument
1988 	pci_update_current_state(dev, dev->current_state);  in pci_enable_device_flags()
1990 	if (atomic_inc_return(&dev->enable_cnt) > 1)  in pci_enable_device_flags()
1993 	bridge = pci_upstream_bridge(dev);  in pci_enable_device_flags()
1999 		if (dev->resource[i].flags & flags)  in pci_enable_device_flags()
2002 		if (dev->resource[i].flags & flags)  in pci_enable_device_flags()
2005 	err = do_pci_enable_device(dev, bars);  in pci_enable_device_flags()
2007 		atomic_dec(&dev->enable_cnt);  in pci_enable_device_flags()
2012  * pci_enable_device_io - Initialize a device for use with IO space
2013  * @dev: PCI device to be initialized
2015  * Initialize device before it's used by a driver. Ask low-level code
2019 int pci_enable_device_io(struct pci_dev *dev)  in pci_enable_device_io()  argument
2021 	return pci_enable_device_flags(dev, IORESOURCE_IO);  in pci_enable_device_io()
2026  * pci_enable_device_mem - Initialize a device for use with Memory space
2027  * @dev: PCI device to be initialized
2029  * Initialize device before it's used by a driver. Ask low-level code
2033 int pci_enable_device_mem(struct pci_dev *dev)  in pci_enable_device_mem()  argument
2035 	return pci_enable_device_flags(dev, IORESOURCE_MEM);  in pci_enable_device_mem()
2040  * pci_enable_device - Initialize device before it's used by a driver.
2041  * @dev: PCI device to be initialized
2043  * Initialize device before it's used by a driver. Ask low-level code
2050 int pci_enable_device(struct pci_dev *dev)  in pci_enable_device()  argument
2052 	return pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);  in pci_enable_device()
2057  * Managed PCI resources.  This manages device on/off, INTx/MSI/MSI-X
2058  * on/off and BAR regions.  pci_dev itself records MSI/MSI-X status, so
2060  * when a device is enabled using managed PCI device enable interface.
2073 	struct pci_dev *dev = to_pci_dev(gendev);  in pcim_release()  local
2078 		if (this->region_mask & (1 << i))  in pcim_release()
2079 			pci_release_region(dev, i);  in pcim_release()
2081 	if (this->mwi)  in pcim_release()
2082 		pci_clear_mwi(dev);  in pcim_release()
2084 	if (this->restore_intx)  in pcim_release()
2085 		pci_intx(dev, this->orig_intx);  in pcim_release()
2087 	if (this->enabled && !this->pinned)  in pcim_release()
2088 		pci_disable_device(dev);  in pcim_release()
2095 	dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);  in get_pci_dr()
2102 	return devres_get(&pdev->dev, new_dr, NULL, NULL);  in get_pci_dr()
2108 		return devres_find(&pdev->dev, pcim_release, NULL, NULL);  in find_pci_dr()
2113  * pcim_enable_device - Managed pci_enable_device()
2114  * @pdev: PCI device to be initialized
2125 		return -ENOMEM;  in pcim_enable_device()
2126 	if (dr->enabled)  in pcim_enable_device()
2131 		pdev->is_managed = 1;  in pcim_enable_device()
2132 		dr->enabled = 1;  in pcim_enable_device()
2139  * pcim_pin_device - Pin managed PCI device
2140  * @pdev: PCI device to pin
2142  * Pin managed PCI device @pdev.  Pinned device won't be disabled on
2151 	WARN_ON(!dr || !dr->enabled);  in pcim_pin_device()
2153 		dr->pinned = 1;  in pcim_pin_device()
2158  * pcibios_device_add - provide arch specific hooks when adding device dev
2159  * @dev: the PCI device being added
2165 int __weak pcibios_device_add(struct pci_dev *dev)  in pcibios_device_add()  argument
2171  * pcibios_release_device - provide arch specific hooks when releasing
2172  *			    device dev
2173  * @dev: the PCI device being released
2179 void __weak pcibios_release_device(struct pci_dev *dev) {}  in pcibios_release_device()  argument
2182  * pcibios_disable_device - disable arch specific PCI resources for device dev
2183  * @dev: the PCI device to disable
2185  * Disables architecture specific PCI resources for the device. This
2189 void __weak pcibios_disable_device(struct pci_dev *dev) {}  in pcibios_disable_device()  argument
2192  * pcibios_penalize_isa_irq - penalize an ISA IRQ
2196  * Permits the platform to provide architecture-specific functionality when
2202 static void do_pci_disable_device(struct pci_dev *dev)  in do_pci_disable_device()  argument
2206 	pci_read_config_word(dev, PCI_COMMAND, &pci_command);  in do_pci_disable_device()
2209 		pci_write_config_word(dev, PCI_COMMAND, pci_command);  in do_pci_disable_device()
2212 	pcibios_disable_device(dev);  in do_pci_disable_device()
2216  * pci_disable_enabled_device - Disable device without updating enable_cnt
2217  * @dev: PCI device to disable
2219  * NOTE: This function is a backend of PCI power management routines and is
2222 void pci_disable_enabled_device(struct pci_dev *dev)  in pci_disable_enabled_device()  argument
2224 	if (pci_is_enabled(dev))  in pci_disable_enabled_device()
2225 		do_pci_disable_device(dev);  in pci_disable_enabled_device()
2229  * pci_disable_device - Disable PCI device after use
2230  * @dev: PCI device to be disabled
2232  * Signal to the system that the PCI device is not in use by the system
2233  * anymore.  This only involves disabling PCI bus-mastering, if active.
2238 void pci_disable_device(struct pci_dev *dev)  in pci_disable_device()  argument
2242 	dr = find_pci_dr(dev);  in pci_disable_device()
2244 		dr->enabled = 0;  in pci_disable_device()
2246 	dev_WARN_ONCE(&dev->dev, atomic_read(&dev->enable_cnt) <= 0,  in pci_disable_device()
2247 		      "disabling already-disabled device");  in pci_disable_device()
2249 	if (atomic_dec_return(&dev->enable_cnt) != 0)  in pci_disable_device()
2252 	do_pci_disable_device(dev);  in pci_disable_device()
2254 	dev->is_busmaster = 0;  in pci_disable_device()
2259  * pcibios_set_pcie_reset_state - set reset state for device dev
2260  * @dev: the PCIe device reset
2266 int __weak pcibios_set_pcie_reset_state(struct pci_dev *dev,  in pcibios_set_pcie_reset_state()  argument
2269 	return -EINVAL;  in pcibios_set_pcie_reset_state()
2273  * pci_set_pcie_reset_state - set reset state for device dev
2274  * @dev: the PCIe device reset
2277  * Sets the PCI reset state for the device.
2279 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)  in pci_set_pcie_reset_state()  argument
2281 	return pcibios_set_pcie_reset_state(dev, state);  in pci_set_pcie_reset_state()
2286 void pcie_clear_device_status(struct pci_dev *dev)  in pcie_clear_device_status()  argument
2290 	pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &sta);  in pcie_clear_device_status()
2291 	pcie_capability_write_word(dev, PCI_EXP_DEVSTA, sta);  in pcie_clear_device_status()
2296  * pcie_clear_root_pme_status - Clear root port PME interrupt status.
2297  * @dev: PCIe root port or event collector.
2299 void pcie_clear_root_pme_status(struct pci_dev *dev)  in pcie_clear_root_pme_status()  argument
2301 	pcie_capability_set_dword(dev, PCI_EXP_RTSTA, PCI_EXP_RTSTA_PME);  in pcie_clear_root_pme_status()
2305  * pci_check_pme_status - Check if given device has generated PME.
2306  * @dev: Device to check.
2312 bool pci_check_pme_status(struct pci_dev *dev)  in pci_check_pme_status()  argument
2318 	if (!dev->pm_cap)  in pci_check_pme_status()
2321 	pmcsr_pos = dev->pm_cap + PCI_PM_CTRL;  in pci_check_pme_status()
2322 	pci_read_config_word(dev, pmcsr_pos, &pmcsr);  in pci_check_pme_status()
2334 	pci_write_config_word(dev, pmcsr_pos, pmcsr);  in pci_check_pme_status()
2340  * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
2341  * @dev: Device to handle.
2344  * Check if @dev has generated PME and queue a resume request for it in that
2347 static int pci_pme_wakeup(struct pci_dev *dev, void *pme_poll_reset)  in pci_pme_wakeup()  argument
2349 	if (pme_poll_reset && dev->pme_poll)  in pci_pme_wakeup()
2350 		dev->pme_poll = false;  in pci_pme_wakeup()
2352 	if (pci_check_pme_status(dev)) {  in pci_pme_wakeup()
2353 		pci_wakeup_event(dev);  in pci_pme_wakeup()
2354 		pm_request_resume(&dev->dev);  in pci_pme_wakeup()
2360  * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
2371  * pci_pme_capable - check the capability of PCI device to generate PME#
2372  * @dev: PCI device to handle.
2373  * @state: PCI state from which device will issue PME#.
2375 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state)  in pci_pme_capable()  argument
2377 	if (!dev->pm_cap)  in pci_pme_capable()
2380 	return !!(dev->pme_support & (1 << state));  in pci_pme_capable()
2390 		if (pme_dev->dev->pme_poll) {  in pci_pme_list_scan()
2393 			bridge = pme_dev->dev->bus->self;  in pci_pme_list_scan()
2399 			if (bridge && bridge->current_state != PCI_D0)  in pci_pme_list_scan()
2405 			if (pme_dev->dev->current_state == PCI_D3cold)  in pci_pme_list_scan()
2408 			pci_pme_wakeup(pme_dev->dev, NULL);  in pci_pme_list_scan()
2410 			list_del(&pme_dev->list);  in pci_pme_list_scan()
2420 static void __pci_pme_active(struct pci_dev *dev, bool enable)  in __pci_pme_active()  argument
2424 	if (!dev->pme_support)  in __pci_pme_active()
2427 	pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);  in __pci_pme_active()
2433 	pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);  in __pci_pme_active()
2437  * pci_pme_restore - Restore PME configuration after config space restore.
2438  * @dev: PCI device to update.
2440 void pci_pme_restore(struct pci_dev *dev)  in pci_pme_restore()  argument
2444 	if (!dev->pme_support)  in pci_pme_restore()
2447 	pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);  in pci_pme_restore()
2448 	if (dev->wakeup_prepared) {  in pci_pme_restore()
2455 	pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);  in pci_pme_restore()
2459  * pci_pme_active - enable or disable PCI device's PME# function
2460  * @dev: PCI device to handle.
2466 void pci_pme_active(struct pci_dev *dev, bool enable)  in pci_pme_active()  argument
2468 	__pci_pme_active(dev, enable);  in pci_pme_active()
2471 	 * PCI (as opposed to PCIe) PME requires that the device have  in pci_pme_active()
2481 	 * Although PCIe uses in-band PME message instead of PME# line  in pci_pme_active()
2485 	 * there are PCI Express Root Ports that don't bother to  in pci_pme_active()
2490 	if (dev->pme_poll) {  in pci_pme_active()
2496 				pci_warn(dev, "can't enable PME#\n");  in pci_pme_active()
2499 			pme_dev->dev = dev;  in pci_pme_active()
2501 			list_add(&pme_dev->list, &pci_pme_list);  in pci_pme_active()
2510 				if (pme_dev->dev == dev) {  in pci_pme_active()
2511 					list_del(&pme_dev->list);  in pci_pme_active()
2520 	pci_dbg(dev, "PME# %s\n", enable ? "enabled" : "disabled");  in pci_pme_active()
2525  * __pci_enable_wake - enable PCI device as wakeup event source
2526  * @dev: PCI device affected
2527  * @state: PCI state from which device will issue wakeup events
2531  * When such events involves platform-specific hooks, those hooks are
2534  * Devices with legacy power management (no standard PCI PM capabilities)
2539  * -EINVAL is returned if device is not supposed to wake up the system
2541  * the native mechanism fail to enable the generation of wake-up events
2543 static int __pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable)  in __pci_enable_wake()  argument
2548 	 * Bridges that are not power-manageable directly only signal  in __pci_enable_wake()
2551 	 * power-manageable may signal wakeup for themselves (for example,  in __pci_enable_wake()
2554 	if (!pci_power_manageable(dev))  in __pci_enable_wake()
2558 	if (!!enable == !!dev->wakeup_prepared)  in __pci_enable_wake()
2562 	 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don  in __pci_enable_wake()
2564 	 * enable.  To disable wake-up we call the platform first, for symmetry.  in __pci_enable_wake()
2577 		if (pci_pme_capable(dev, state) || pci_pme_capable(dev, PCI_D3cold))  in __pci_enable_wake()
2578 			pci_pme_active(dev, true);  in __pci_enable_wake()
2581 		error = platform_pci_set_wakeup(dev, true);  in __pci_enable_wake()
2585 			dev->wakeup_prepared = true;  in __pci_enable_wake()
2587 		platform_pci_set_wakeup(dev, false);  in __pci_enable_wake()
2588 		pci_pme_active(dev, false);  in __pci_enable_wake()
2589 		dev->wakeup_prepared = false;  in __pci_enable_wake()
2596  * pci_enable_wake - change wakeup settings for a PCI device
2598  * @state: PCI state from which device will issue wakeup events
2606 	if (enable && !device_may_wakeup(&pci_dev->dev))  in pci_enable_wake()
2607 		return -EINVAL;  in pci_enable_wake()
2614  * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
2615  * @dev: PCI device to prepare
2616  * @enable: True to enable wake-up event generation; false to disable
2619  * and this function allows them to set that up cleanly - pci_enable_wake()
2620  * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
2625  * D3_hot and D3_cold and the platform is unable to enable wake-up power for it.
2627 int pci_wake_from_d3(struct pci_dev *dev, bool enable)  in pci_wake_from_d3()  argument
2629 	return pci_pme_capable(dev, PCI_D3cold) ?  in pci_wake_from_d3()
2630 			pci_enable_wake(dev, PCI_D3cold, enable) :  in pci_wake_from_d3()
2631 			pci_enable_wake(dev, PCI_D3hot, enable);  in pci_wake_from_d3()
2636  * pci_target_state - find an appropriate low power state for a given PCI dev
2637  * @dev: PCI device
2640  * Use underlying platform code to find a supported low power state for @dev.
2641  * If the platform can't manage @dev, return the deepest state from which it
2644 static pci_power_t pci_target_state(struct pci_dev *dev, bool wakeup)  in pci_target_state()  argument
2646 	if (platform_pci_power_manageable(dev)) {  in pci_target_state()
2650 		pci_power_t state = platform_pci_choose_state(dev);  in pci_target_state()
2659 			if (pci_no_d1d2(dev))  in pci_target_state()
2667 	 * If the device is in D3cold even though it's not power-manageable by  in pci_target_state()
2668 	 * the platform, it may have been powered down by non-standard means.  in pci_target_state()
2671 	if (dev->current_state == PCI_D3cold)  in pci_target_state()
2673 	else if (!dev->pm_cap)  in pci_target_state()
2676 	if (wakeup && dev->pme_support) {  in pci_target_state()
2683 		while (state && !(dev->pme_support & (1 << state)))  in pci_target_state()
2684 			state--;  in pci_target_state()
2688 		else if (dev->pme_support & 1)  in pci_target_state()
2696  * pci_prepare_to_sleep - prepare PCI device for system-wide transition
2698  * @dev: Device to handle.
2704 int pci_prepare_to_sleep(struct pci_dev *dev)  in pci_prepare_to_sleep()  argument
2706 	bool wakeup = device_may_wakeup(&dev->dev);  in pci_prepare_to_sleep()
2707 	pci_power_t target_state = pci_target_state(dev, wakeup);  in pci_prepare_to_sleep()
2711 		return -EIO;  in pci_prepare_to_sleep()
2713 	pci_enable_wake(dev, target_state, wakeup);  in pci_prepare_to_sleep()
2715 	error = pci_set_power_state(dev, target_state);  in pci_prepare_to_sleep()
2718 		pci_enable_wake(dev, target_state, false);  in pci_prepare_to_sleep()
2725  * pci_back_from_sleep - turn PCI device on during system-wide transition
2727  * @dev: Device to handle.
2729  * Disable device's system wake-up capability and put it into D0.
2731 int pci_back_from_sleep(struct pci_dev *dev)  in pci_back_from_sleep()  argument
2733 	int ret = pci_set_power_state(dev, PCI_D0);  in pci_back_from_sleep()
2738 	pci_enable_wake(dev, PCI_D0, false);  in pci_back_from_sleep()
2744  * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
2745  * @dev: PCI device being suspended.
2747  * Prepare @dev to generate wake-up events at run time and put it into a low
2750 int pci_finish_runtime_suspend(struct pci_dev *dev)  in pci_finish_runtime_suspend()  argument
2755 	target_state = pci_target_state(dev, device_can_wakeup(&dev->dev));  in pci_finish_runtime_suspend()
2757 		return -EIO;  in pci_finish_runtime_suspend()
2759 	__pci_enable_wake(dev, target_state, pci_dev_run_wake(dev));  in pci_finish_runtime_suspend()
2761 	error = pci_set_power_state(dev, target_state);  in pci_finish_runtime_suspend()
2764 		pci_enable_wake(dev, target_state, false);  in pci_finish_runtime_suspend()
2770  * pci_dev_run_wake - Check if device can generate run-time wake-up events.
2771  * @dev: Device to check.
2773  * Return true if the device itself is capable of generating wake-up events
2775  * PME and one of its upstream bridges can generate wake-up events.
2777 bool pci_dev_run_wake(struct pci_dev *dev)  in pci_dev_run_wake()  argument
2779 	struct pci_bus *bus = dev->bus;  in pci_dev_run_wake()
2781 	if (!dev->pme_support)  in pci_dev_run_wake()
2784 	/* PME-capable in principle, but not from the target power state */  in pci_dev_run_wake()
2785 	if (!pci_pme_capable(dev, pci_target_state(dev, true)))  in pci_dev_run_wake()
2788 	if (device_can_wakeup(&dev->dev))  in pci_dev_run_wake()
2791 	while (bus->parent) {  in pci_dev_run_wake()
2792 		struct pci_dev *bridge = bus->self;  in pci_dev_run_wake()
2794 		if (device_can_wakeup(&bridge->dev))  in pci_dev_run_wake()
2797 		bus = bus->parent;  in pci_dev_run_wake()
2801 	if (bus->bridge)  in pci_dev_run_wake()
2802 		return device_can_wakeup(bus->bridge);  in pci_dev_run_wake()
2809  * pci_dev_need_resume - Check if it is necessary to resume the device.
2812  * Return 'true' if the device is not runtime-suspended or it has to be
2815  * (system-wide) transition.
2819 	struct device *dev = &pci_dev->dev;  in pci_dev_need_resume()  local
2822 	if (!pm_runtime_suspended(dev) || platform_pci_need_resume(pci_dev))  in pci_dev_need_resume()
2825 	target_state = pci_target_state(pci_dev, device_may_wakeup(dev));  in pci_dev_need_resume()
2832 	return target_state != pci_dev->current_state &&  in pci_dev_need_resume()
2834 		pci_dev->current_state != PCI_D3hot;  in pci_dev_need_resume()
2838  * pci_dev_adjust_pme - Adjust PME setting for a suspended device.
2850 	struct device *dev = &pci_dev->dev;  in pci_dev_adjust_pme()  local
2852 	spin_lock_irq(&dev->power.lock);  in pci_dev_adjust_pme()
2854 	if (pm_runtime_suspended(dev) && !device_may_wakeup(dev) &&  in pci_dev_adjust_pme()
2855 	    pci_dev->current_state < PCI_D3cold)  in pci_dev_adjust_pme()
2858 	spin_unlock_irq(&dev->power.lock);  in pci_dev_adjust_pme()
2862  * pci_dev_complete_resume - Finalize resume from system sleep for a device.
2865  * If the device is runtime suspended and wakeup-capable, enable PME for it as
2871 	struct device *dev = &pci_dev->dev;  in pci_dev_complete_resume()  local
2876 	spin_lock_irq(&dev->power.lock);  in pci_dev_complete_resume()
2878 	if (pm_runtime_suspended(dev) && pci_dev->current_state < PCI_D3cold)  in pci_dev_complete_resume()
2881 	spin_unlock_irq(&dev->power.lock);  in pci_dev_complete_resume()
2885  * pci_choose_state - Choose the power state of a PCI device.
2886  * @dev: Target PCI device.
2889  * Returns PCI power state suitable for @dev and @state.
2891 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)  in pci_choose_state()  argument
2896 	return pci_target_state(dev, false);  in pci_choose_state()
2902 	struct device *dev = &pdev->dev;  in pci_config_pm_runtime_get()  local
2903 	struct device *parent = dev->parent;  in pci_config_pm_runtime_get()
2907 	pm_runtime_get_noresume(dev);  in pci_config_pm_runtime_get()
2909 	 * pdev->current_state is set to PCI_D3cold during suspending,  in pci_config_pm_runtime_get()
2912 	pm_runtime_barrier(dev);  in pci_config_pm_runtime_get()
2918 	if (pdev->current_state == PCI_D3cold)  in pci_config_pm_runtime_get()
2919 		pm_runtime_resume(dev);  in pci_config_pm_runtime_get()
2924 	struct device *dev = &pdev->dev;  in pci_config_pm_runtime_put()  local
2925 	struct device *parent = dev->parent;  in pci_config_pm_runtime_put()
2927 	pm_runtime_put(dev);  in pci_config_pm_runtime_put()
2941 		.ident = "X299 DESIGNARE EX-CF",
2944 			DMI_MATCH(DMI_BOARD_NAME, "X299 DESIGNARE EX-CF"),
2964  * pci_bridge_d3_possible - Is it possible to put the bridge into D3
2984 		 * may not be put into D3 by the OS (Thunderbolt on non-Macs).  in pci_bridge_d3_possible()
2986 		if (bridge->is_hotplug_bridge && !pciehp_is_native(bridge))  in pci_bridge_d3_possible()
2993 		if (bridge->is_thunderbolt)  in pci_bridge_d3_possible()
3005 		if (bridge->is_hotplug_bridge)  in pci_bridge_d3_possible()
3023 static int pci_dev_check_d3cold(struct pci_dev *dev, void *data)  in pci_dev_check_d3cold()  argument
3028 	    dev->no_d3cold || !dev->d3cold_allowed ||  in pci_dev_check_d3cold()
3031 	    (device_may_wakeup(&dev->dev) &&  in pci_dev_check_d3cold()
3032 	     !pci_pme_capable(dev, PCI_D3cold)) ||  in pci_dev_check_d3cold()
3035 	    !pci_power_manageable(dev))  in pci_dev_check_d3cold()
3043  * pci_bridge_d3_update - Update bridge D3 capabilities
3044  * @dev: PCI device which is changed
3050 void pci_bridge_d3_update(struct pci_dev *dev)  in pci_bridge_d3_update()  argument
3052 	bool remove = !device_is_registered(&dev->dev);  in pci_bridge_d3_update()
3056 	bridge = pci_upstream_bridge(dev);  in pci_bridge_d3_update()
3064 	if (remove && bridge->bridge_d3)  in pci_bridge_d3_update()
3076 		pci_dev_check_d3cold(dev, &d3cold_ok);  in pci_bridge_d3_update()
3084 	if (d3cold_ok && !bridge->bridge_d3)  in pci_bridge_d3_update()
3085 		pci_walk_bus(bridge->subordinate, pci_dev_check_d3cold,  in pci_bridge_d3_update()
3088 	if (bridge->bridge_d3 != d3cold_ok) {  in pci_bridge_d3_update()
3089 		bridge->bridge_d3 = d3cold_ok;  in pci_bridge_d3_update()
3096  * pci_d3cold_enable - Enable D3cold for device
3097  * @dev: PCI device to handle
3100  * they handle.  It also updates upstream PCI bridge PM capabilities
3103 void pci_d3cold_enable(struct pci_dev *dev)  in pci_d3cold_enable()  argument
3105 	if (dev->no_d3cold) {  in pci_d3cold_enable()
3106 		dev->no_d3cold = false;  in pci_d3cold_enable()
3107 		pci_bridge_d3_update(dev);  in pci_d3cold_enable()
3113  * pci_d3cold_disable - Disable D3cold for device
3114  * @dev: PCI device to handle
3117  * they handle.  It also updates upstream PCI bridge PM capabilities
3120 void pci_d3cold_disable(struct pci_dev *dev)  in pci_d3cold_disable()  argument
3122 	if (!dev->no_d3cold) {  in pci_d3cold_disable()
3123 		dev->no_d3cold = true;  in pci_d3cold_disable()
3124 		pci_bridge_d3_update(dev);  in pci_d3cold_disable()
3130  * pci_pm_init - Initialize PM functions of given PCI device
3131  * @dev: PCI device to handle.
3133 void pci_pm_init(struct pci_dev *dev)  in pci_pm_init()  argument
3139 	pm_runtime_forbid(&dev->dev);  in pci_pm_init()
3140 	pm_runtime_set_active(&dev->dev);  in pci_pm_init()
3141 	pm_runtime_enable(&dev->dev);  in pci_pm_init()
3142 	device_enable_async_suspend(&dev->dev);  in pci_pm_init()
3143 	dev->wakeup_prepared = false;  in pci_pm_init()
3145 	dev->pm_cap = 0;  in pci_pm_init()
3146 	dev->pme_support = 0;  in pci_pm_init()
3148 	/* find PCI PM capability in list */  in pci_pm_init()
3149 	pm = pci_find_capability(dev, PCI_CAP_ID_PM);  in pci_pm_init()
3153 	pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);  in pci_pm_init()
3156 		pci_err(dev, "unsupported PM cap regs version (%u)\n",  in pci_pm_init()
3161 	dev->pm_cap = pm;  in pci_pm_init()
3162 	dev->d3hot_delay = PCI_PM_D3HOT_WAIT;  in pci_pm_init()
3163 	dev->d3cold_delay = PCI_PM_D3COLD_WAIT;  in pci_pm_init()
3164 	dev->bridge_d3 = pci_bridge_d3_possible(dev);  in pci_pm_init()
3165 	dev->d3cold_allowed = true;  in pci_pm_init()
3167 	dev->d1_support = false;  in pci_pm_init()
3168 	dev->d2_support = false;  in pci_pm_init()
3169 	if (!pci_no_d1d2(dev)) {  in pci_pm_init()
3171 			dev->d1_support = true;  in pci_pm_init()
3173 			dev->d2_support = true;  in pci_pm_init()
3175 		if (dev->d1_support || dev->d2_support)  in pci_pm_init()
3176 			pci_info(dev, "supports%s%s\n",  in pci_pm_init()
3177 				   dev->d1_support ? " D1" : "",  in pci_pm_init()
3178 				   dev->d2_support ? " D2" : "");  in pci_pm_init()
3183 		pci_info(dev, "PME# supported from%s%s%s%s%s\n",  in pci_pm_init()
3189 		dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT;  in pci_pm_init()
3190 		dev->pme_poll = true;  in pci_pm_init()
3192 		 * Make device's PM flags reflect the wake-up capability, but  in pci_pm_init()
3195 		device_set_wakeup_capable(&dev->dev, true);  in pci_pm_init()
3197 		pci_pme_active(dev, false);  in pci_pm_init()
3200 	pci_read_config_word(dev, PCI_STATUS, &status);  in pci_pm_init()
3202 		dev->imm_ready = 1;  in pci_pm_init()
3205 static unsigned long pci_ea_flags(struct pci_dev *dev, u8 prop)  in pci_ea_flags()  argument
3228 static struct resource *pci_ea_get_resource(struct pci_dev *dev, u8 bei,  in pci_ea_get_resource()  argument
3232 		return &dev->resource[bei];  in pci_ea_get_resource()
3236 		return &dev->resource[PCI_IOV_RESOURCES +  in pci_ea_get_resource()
3237 				      bei - PCI_EA_BEI_VF_BAR0];  in pci_ea_get_resource()
3240 		return &dev->resource[PCI_ROM_RESOURCE];  in pci_ea_get_resource()
3246 static int pci_ea_read(struct pci_dev *dev, int offset)  in pci_ea_read()  argument
3256 	pci_read_config_dword(dev, ent_offset, &dw0);  in pci_ea_read()
3277 	res = pci_ea_get_resource(dev, bei, prop);  in pci_ea_read()
3279 		pci_err(dev, "Unsupported EA entry BEI: %u\n", bei);  in pci_ea_read()
3283 	flags = pci_ea_flags(dev, prop);  in pci_ea_read()
3285 		pci_err(dev, "Unsupported EA properties: %#x\n", prop);  in pci_ea_read()
3290 	pci_read_config_dword(dev, ent_offset, &base);  in pci_ea_read()
3295 	pci_read_config_dword(dev, ent_offset, &max_offset);  in pci_ea_read()
3298 	/* Read Base MSBs (if 64-bit entry) */  in pci_ea_read()
3302 		pci_read_config_dword(dev, ent_offset, &base_upper);  in pci_ea_read()
3307 		/* entry starts above 32-bit boundary, can't use */  in pci_ea_read()
3317 	/* Read MaxOffset MSBs (if 64-bit entry) */  in pci_ea_read()
3321 		pci_read_config_dword(dev, ent_offset, &max_offset_upper);  in pci_ea_read()
3335 		pci_err(dev, "EA Entry crosses address boundary\n");  in pci_ea_read()
3339 	if (ent_size != ent_offset - offset) {  in pci_ea_read()
3340 		pci_err(dev, "EA Entry Size (%d) does not match length read (%d)\n",  in pci_ea_read()
3341 			ent_size, ent_offset - offset);  in pci_ea_read()
3345 	res->name = pci_name(dev);  in pci_ea_read()
3346 	res->start = start;  in pci_ea_read()
3347 	res->end = end;  in pci_ea_read()
3348 	res->flags = flags;  in pci_ea_read()
3351 		pci_info(dev, "BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",  in pci_ea_read()
3354 		pci_info(dev, "ROM: %pR (from Enhanced Allocation, properties %#02x)\n",  in pci_ea_read()
3357 		pci_info(dev, "VF BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",  in pci_ea_read()
3358 			   bei - PCI_EA_BEI_VF_BAR0, res, prop);  in pci_ea_read()
3360 		pci_info(dev, "BEI %d res: %pR (from Enhanced Allocation, properties %#02x)\n",  in pci_ea_read()
3368 void pci_ea_init(struct pci_dev *dev)  in pci_ea_init()  argument
3375 	/* find PCI EA capability in list */  in pci_ea_init()
3376 	ea = pci_find_capability(dev, PCI_CAP_ID_EA);  in pci_ea_init()
3381 	pci_bus_read_config_byte(dev->bus, dev->devfn, ea + PCI_EA_NUM_ENT,  in pci_ea_init()
3388 	if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE)  in pci_ea_init()
3393 		offset = pci_ea_read(dev, offset);  in pci_ea_init()
3399 	hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space);  in pci_add_saved_cap()
3403  * _pci_add_cap_save_buffer - allocate buffer for saving given
3405  * @dev: the PCI device
3410 static int _pci_add_cap_save_buffer(struct pci_dev *dev, u16 cap,  in _pci_add_cap_save_buffer()  argument
3417 		pos = pci_find_ext_capability(dev, cap);  in _pci_add_cap_save_buffer()
3419 		pos = pci_find_capability(dev, cap);  in _pci_add_cap_save_buffer()
3426 		return -ENOMEM;  in _pci_add_cap_save_buffer()
3428 	save_state->cap.cap_nr = cap;  in _pci_add_cap_save_buffer()
3429 	save_state->cap.cap_extended = extended;  in _pci_add_cap_save_buffer()
3430 	save_state->cap.size = size;  in _pci_add_cap_save_buffer()
3431 	pci_add_saved_cap(dev, save_state);  in _pci_add_cap_save_buffer()
3436 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size)  in pci_add_cap_save_buffer()  argument
3438 	return _pci_add_cap_save_buffer(dev, cap, false, size);  in pci_add_cap_save_buffer()
3441 int pci_add_ext_cap_save_buffer(struct pci_dev *dev, u16 cap, unsigned int size)  in pci_add_ext_cap_save_buffer()  argument
3443 	return _pci_add_cap_save_buffer(dev, cap, true, size);  in pci_add_ext_cap_save_buffer()
3447  * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
3448  * @dev: the PCI device
3450 void pci_allocate_cap_save_buffers(struct pci_dev *dev)  in pci_allocate_cap_save_buffers()  argument
3454 	error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP,  in pci_allocate_cap_save_buffers()
3457 		pci_err(dev, "unable to preallocate PCI Express save buffer\n");  in pci_allocate_cap_save_buffers()
3459 	error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16));  in pci_allocate_cap_save_buffers()
3461 		pci_err(dev, "unable to preallocate PCI-X save buffer\n");  in pci_allocate_cap_save_buffers()
3463 	error = pci_add_ext_cap_save_buffer(dev, PCI_EXT_CAP_ID_LTR,  in pci_allocate_cap_save_buffers()
3466 		pci_err(dev, "unable to allocate suspend buffer for LTR\n");  in pci_allocate_cap_save_buffers()
3468 	error = pci_add_ext_cap_save_buffer(dev, PCI_EXT_CAP_ID_L1SS,  in pci_allocate_cap_save_buffers()
3471 		pci_err(dev, "unable to allocate suspend buffer for ASPM-L1SS\n");  in pci_allocate_cap_save_buffers()
3473 	pci_allocate_vc_save_buffers(dev);  in pci_allocate_cap_save_buffers()
3476 void pci_free_cap_save_buffers(struct pci_dev *dev)  in pci_free_cap_save_buffers()  argument
3481 	hlist_for_each_entry_safe(tmp, n, &dev->saved_cap_space, next)  in pci_free_cap_save_buffers()
3486  * pci_configure_ari - enable or disable ARI forwarding
3487  * @dev: the PCI device
3489  * If @dev and its upstream bridge both support ARI, enable ARI in the
3492 void pci_configure_ari(struct pci_dev *dev)  in pci_configure_ari()  argument
3497 	if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn)  in pci_configure_ari()
3500 	bridge = dev->bus->self;  in pci_configure_ari()
3508 	if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI)) {  in pci_configure_ari()
3511 		bridge->ari_enabled = 1;  in pci_configure_ari()
3515 		bridge->ari_enabled = 0;  in pci_configure_ari()
3524 	pos = pdev->acs_cap;  in pci_acs_flags_enabled()
3531 	 * capability field can therefore be assumed as hard-wired enabled.  in pci_acs_flags_enabled()
3541  * pci_acs_enabled - test ACS against required flags for a given device
3543  * @acs_flags: required PCI ACS flags
3551  * opportunity for peer-to-peer access.  We therefore return 'true'
3565 	 * Conventional PCI and PCI-X devices never support ACS, either  in pci_acs_enabled()
3574 	 * PCI/X-to-PCIe bridges are not specifically mentioned by the spec,  in pci_acs_enabled()
3575 	 * but since their primary interface is PCI/X, we conservatively  in pci_acs_enabled()
3576 	 * handle them as we would a non-PCIe device.  in pci_acs_enabled()
3590 	 * implement ACS in order to indicate their peer-to-peer capabilities,  in pci_acs_enabled()
3591 	 * regardless of whether they are single- or multi-function devices.  in pci_acs_enabled()
3598 	 * implemented by the remaining PCIe types to indicate peer-to-peer  in pci_acs_enabled()
3607 		if (!pdev->multifunction)  in pci_acs_enabled()
3621  * pci_acs_path_enabled - test ACS flags from start to end in a hierarchy
3626  * Walk up a device tree from start to end testing PCI ACS support.  If
3640 		if (pci_is_root_bus(pdev->bus))  in pci_acs_path_enabled()
3643 		parent = pdev->bus->self;  in pci_acs_path_enabled()
3650  * pci_acs_init - Initialize ACS if hardware supports it
3651  * @dev: the PCI device
3653 void pci_acs_init(struct pci_dev *dev)  in pci_acs_init()  argument
3655 	dev->acs_cap = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);  in pci_acs_init()
3663 	pci_enable_acs(dev);  in pci_acs_init()
3667  * pci_rebar_find_pos - find position of resize ctrl reg for BAR
3668  * @pdev: PCI device
3672  * Returns -ENOTSUPP if resizable BARs are not supported at all.
3673  * Returns -ENOENT if no ctrl register for the BAR could be found.
3682 		return -ENOTSUPP;  in pci_rebar_find_pos()
3697 	return -ENOENT;  in pci_rebar_find_pos()
3701  * pci_rebar_get_possible_sizes - get possible sizes for BAR
3702  * @pdev: PCI device
3721 	if (pdev->vendor == PCI_VENDOR_ID_ATI && pdev->device == 0x731f &&  in pci_rebar_get_possible_sizes()
3730  * pci_rebar_get_current_size - get the current size of a BAR
3731  * @pdev: PCI device
3751  * pci_rebar_set_size - set a new size for a BAR
3752  * @pdev: PCI device
3776  * pci_enable_atomic_ops_to_root - enable AtomicOp requests to root port
3777  * @dev: the PCI device
3785  * the requested completion capabilities (32-bit, 64-bit and/or 128-bit
3788 int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask)  in pci_enable_atomic_ops_to_root()  argument
3790 	struct pci_bus *bus = dev->bus;  in pci_enable_atomic_ops_to_root()
3799 	if (dev->is_virtfn)  in pci_enable_atomic_ops_to_root()
3800 		return -EINVAL;  in pci_enable_atomic_ops_to_root()
3802 	if (!pci_is_pcie(dev))  in pci_enable_atomic_ops_to_root()
3803 		return -EINVAL;  in pci_enable_atomic_ops_to_root()
3809 	 * completers, and no peer-to-peer.  in pci_enable_atomic_ops_to_root()
3812 	switch (pci_pcie_type(dev)) {  in pci_enable_atomic_ops_to_root()
3818 		return -EINVAL;  in pci_enable_atomic_ops_to_root()
3821 	while (bus->parent) {  in pci_enable_atomic_ops_to_root()
3822 		bridge = bus->self;  in pci_enable_atomic_ops_to_root()
3831 				return -EINVAL;  in pci_enable_atomic_ops_to_root()
3837 				return -EINVAL;  in pci_enable_atomic_ops_to_root()
3846 				return -EINVAL;  in pci_enable_atomic_ops_to_root()
3849 		bus = bus->parent;  in pci_enable_atomic_ops_to_root()
3852 	pcie_capability_set_word(dev, PCI_EXP_DEVCTL2,  in pci_enable_atomic_ops_to_root()
3859  * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
3860  * @dev: the PCI device
3864  * required by section 9.1 of the PCI-to-PCI bridge specification for devices
3865  * behind bridges on add-in cards.  For devices with ARI enabled, the slot
3867  * the PCI Express Base Specification, Revision 2.1)
3869 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin)  in pci_swizzle_interrupt_pin()  argument
3873 	if (pci_ari_enabled(dev->bus))  in pci_swizzle_interrupt_pin()
3876 		slot = PCI_SLOT(dev->devfn);  in pci_swizzle_interrupt_pin()
3878 	return (((pin - 1) + slot) % 4) + 1;  in pci_swizzle_interrupt_pin()
3881 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)  in pci_get_interrupt_pin()  argument
3885 	pin = dev->pin;  in pci_get_interrupt_pin()
3887 		return -1;  in pci_get_interrupt_pin()
3889 	while (!pci_is_root_bus(dev->bus)) {  in pci_get_interrupt_pin()
3890 		pin = pci_swizzle_interrupt_pin(dev, pin);  in pci_get_interrupt_pin()
3891 		dev = dev->bus->self;  in pci_get_interrupt_pin()
3893 	*bridge = dev;  in pci_get_interrupt_pin()
3898  * pci_common_swizzle - swizzle INTx all the way to root bridge
3899  * @dev: the PCI device
3902  * Perform INTx swizzling for a device.  This traverses through all PCI-to-PCI
3903  * bridges all the way up to a PCI root bus.
3905 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp)  in pci_common_swizzle()  argument
3909 	while (!pci_is_root_bus(dev->bus)) {  in pci_common_swizzle()
3910 		pin = pci_swizzle_interrupt_pin(dev, pin);  in pci_common_swizzle()
3911 		dev = dev->bus->self;  in pci_common_swizzle()
3914 	return PCI_SLOT(dev->devfn);  in pci_common_swizzle()
3919  * pci_release_region - Release a PCI bar
3920  * @pdev: PCI device whose resources were previously reserved by
3924  * Releases the PCI I/O and memory resources previously reserved by a
3926  * after all use of the PCI regions has ceased.
3943 		dr->region_mask &= ~(1 << bar);  in pci_release_region()
3948  * __pci_request_region - Reserved PCI I/O and memory resource
3949  * @pdev: PCI device whose resources are to be reserved
3954  * Mark the PCI region associated with PCI device @pdev BAR @bar as
3956  * address inside the PCI regions unless this call returns
3960  * is explicitly not allowed to map the resource via /dev/mem or
3987 		dr->region_mask |= 1 << bar;  in __pci_request_region()
3993 		 &pdev->resource[bar]);  in __pci_request_region()
3994 	return -EBUSY;  in __pci_request_region()
3998  * pci_request_region - Reserve PCI I/O and memory resource
3999  * @pdev: PCI device whose resources are to be reserved
4003  * Mark the PCI region associated with PCI device @pdev BAR @bar as
4005  * address inside the PCI regions unless this call returns
4018  * pci_release_selected_regions - Release selected PCI I/O and memory resources
4019  * @pdev: PCI device whose resources were previously reserved
4022  * Release selected PCI I/O and memory resources previously reserved.
4023  * Call this function only after all use of the PCI regions has ceased.
4047 	while (--i >= 0)  in __pci_request_selected_regions()
4051 	return -EBUSY;  in __pci_request_selected_regions()
4056  * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
4057  * @pdev: PCI device whose resources are to be reserved
4077  * pci_release_regions - Release reserved PCI I/O and memory resources
4078  * @pdev: PCI device whose resources were previously reserved by
4081  * Releases all PCI I/O and memory resources previously reserved by a
4083  * after all use of the PCI regions has ceased.
4088 	pci_release_selected_regions(pdev, (1 << PCI_STD_NUM_BARS) - 1);  in pci_release_regions()
4093  * pci_request_regions - Reserve PCI I/O and memory resources
4094  * @pdev: PCI device whose resources are to be reserved
4097  * Mark all PCI regions associated with PCI device @pdev as
4099  * address inside the PCI regions unless this call returns
4108 			((1 << PCI_STD_NUM_BARS) - 1), res_name);  in pci_request_regions()
4113  * pci_request_regions_exclusive - Reserve PCI I/O and memory resources
4114  * @pdev: PCI device whose resources are to be reserved
4117  * Mark all PCI regions associated with PCI device @pdev as being reserved
4118  * by owner @res_name.  Do not access any address inside the PCI regions
4121  * pci_request_regions_exclusive() will mark the region so that /dev/mem
4130 				((1 << PCI_STD_NUM_BARS) - 1), res_name);  in pci_request_regions_exclusive()
4135  * Record the PCI IO range (expressed as CPU physical address + size).
4146 		return -EINVAL;  in pci_register_io_range()
4150 		return -ENOMEM;  in pci_register_io_range()
4152 	range->fwnode = fwnode;  in pci_register_io_range()
4153 	range->size = size;  in pci_register_io_range()
4154 	range->hw_start = addr;  in pci_register_io_range()
4155 	range->flags = LOGIC_PIO_CPU_MMIO;  in pci_register_io_range()
4162 	if (ret == -EEXIST)  in pci_register_io_range()
4190 		return (unsigned long)-1;  in pci_address_to_pio()
4197  * pci_remap_iospace - Remap the memory mapped I/O space
4210 	unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start;  in pci_remap_iospace()
4212 	if (!(res->flags & IORESOURCE_IO))  in pci_remap_iospace()
4213 		return -EINVAL;  in pci_remap_iospace()
4215 	if (res->end > IO_SPACE_LIMIT)  in pci_remap_iospace()
4216 		return -EINVAL;  in pci_remap_iospace()
4226 	return -ENODEV;  in pci_remap_iospace()
4233  * pci_unmap_iospace - Unmap the memory mapped I/O space
4243 	unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start;  in pci_unmap_iospace()
4250 static void devm_pci_unmap_iospace(struct device *dev, void *ptr)  in devm_pci_unmap_iospace()  argument
4258  * devm_pci_remap_iospace - Managed pci_remap_iospace()
4259  * @dev: Generic device to remap IO address for
4266 int devm_pci_remap_iospace(struct device *dev, const struct resource *res,  in devm_pci_remap_iospace()  argument
4274 		return -ENOMEM;  in devm_pci_remap_iospace()
4281 		devres_add(dev, ptr);  in devm_pci_remap_iospace()
4289  * devm_pci_remap_cfgspace - Managed pci_remap_cfgspace()
4290  * @dev: Generic device to remap IO address for
4297 void __iomem *devm_pci_remap_cfgspace(struct device *dev,  in devm_pci_remap_cfgspace()  argument
4310 		devres_add(dev, ptr);  in devm_pci_remap_cfgspace()
4319  * devm_pci_remap_cfg_resource - check, request region and ioremap cfg resource
4320  * @dev: generic device to handle the resource for
4325  * proper PCI configuration space memory attributes are guaranteed.
4333  *	base = devm_pci_remap_cfg_resource(&pdev->dev, res);
4337 void __iomem *devm_pci_remap_cfg_resource(struct device *dev,  in devm_pci_remap_cfg_resource()  argument
4344 	BUG_ON(!dev);  in devm_pci_remap_cfg_resource()
4347 		dev_err(dev, "invalid resource\n");  in devm_pci_remap_cfg_resource()
4348 		return IOMEM_ERR_PTR(-EINVAL);  in devm_pci_remap_cfg_resource()
4353 	if (res->name)  in devm_pci_remap_cfg_resource()
4354 		name = devm_kasprintf(dev, GFP_KERNEL, "%s %s", dev_name(dev),  in devm_pci_remap_cfg_resource()
4355 				      res->name);  in devm_pci_remap_cfg_resource()
4357 		name = devm_kstrdup(dev, dev_name(dev), GFP_KERNEL);  in devm_pci_remap_cfg_resource()
4359 		return IOMEM_ERR_PTR(-ENOMEM);  in devm_pci_remap_cfg_resource()
4361 	if (!devm_request_mem_region(dev, res->start, size, name)) {  in devm_pci_remap_cfg_resource()
4362 		dev_err(dev, "can't request region for resource %pR\n", res);  in devm_pci_remap_cfg_resource()
4363 		return IOMEM_ERR_PTR(-EBUSY);  in devm_pci_remap_cfg_resource()
4366 	dest_ptr = devm_pci_remap_cfgspace(dev, res->start, size);  in devm_pci_remap_cfg_resource()
4368 		dev_err(dev, "ioremap failed for resource %pR\n", res);  in devm_pci_remap_cfg_resource()
4369 		devm_release_mem_region(dev, res->start, size);  in devm_pci_remap_cfg_resource()
4370 		dest_ptr = IOMEM_ERR_PTR(-ENOMEM);  in devm_pci_remap_cfg_resource()
4377 static void __pci_set_master(struct pci_dev *dev, bool enable)  in __pci_set_master()  argument
4381 	pci_read_config_word(dev, PCI_COMMAND, &old_cmd);  in __pci_set_master()
4387 		pci_dbg(dev, "%s bus mastering\n",  in __pci_set_master()
4389 		pci_write_config_word(dev, PCI_COMMAND, cmd);  in __pci_set_master()
4391 	dev->is_busmaster = enable;  in __pci_set_master()
4395  * pcibios_setup - process "pci=" kernel boot arguments
4396  * @str: string used to pass in "pci=" kernel boot arguments
4407  * pcibios_set_master - enable PCI bus-mastering for device dev
4408  * @dev: the PCI device to enable
4410  * Enables PCI bus-mastering for the device.  This is the default
4414 void __weak pcibios_set_master(struct pci_dev *dev)  in pcibios_set_master()  argument
4419 	if (pci_is_pcie(dev))  in pcibios_set_master()
4422 	pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);  in pcibios_set_master()
4430 	pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);  in pcibios_set_master()
4434  * pci_set_master - enables bus-mastering for device dev
4435  * @dev: the PCI device to enable
4437  * Enables bus-mastering on the device and calls pcibios_set_master()
4440 void pci_set_master(struct pci_dev *dev)  in pci_set_master()  argument
4442 	__pci_set_master(dev, true);  in pci_set_master()
4443 	pcibios_set_master(dev);  in pci_set_master()
4448  * pci_clear_master - disables bus-mastering for device dev
4449  * @dev: the PCI device to disable
4451 void pci_clear_master(struct pci_dev *dev)  in pci_clear_master()  argument
4453 	__pci_set_master(dev, false);  in pci_clear_master()
4458  * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
4459  * @dev: the PCI device for which MWI is to be enabled
4463  * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
4465  * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4467 int pci_set_cacheline_size(struct pci_dev *dev)  in pci_set_cacheline_size()  argument
4472 		return -EINVAL;  in pci_set_cacheline_size()
4476 	pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);  in pci_set_cacheline_size()
4482 	pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);  in pci_set_cacheline_size()
4484 	pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);  in pci_set_cacheline_size()
4488 	pci_dbg(dev, "cache line size of %d is not supported\n",  in pci_set_cacheline_size()
4491 	return -EINVAL;  in pci_set_cacheline_size()
4496  * pci_set_mwi - enables memory-write-invalidate PCI transaction
4497  * @dev: the PCI device for which MWI is enabled
4499  * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
4501  * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4503 int pci_set_mwi(struct pci_dev *dev)  in pci_set_mwi()  argument
4511 	rc = pci_set_cacheline_size(dev);  in pci_set_mwi()
4515 	pci_read_config_word(dev, PCI_COMMAND, &cmd);  in pci_set_mwi()
4517 		pci_dbg(dev, "enabling Mem-Wr-Inval\n");  in pci_set_mwi()
4519 		pci_write_config_word(dev, PCI_COMMAND, cmd);  in pci_set_mwi()
4527  * pcim_set_mwi - a device-managed pci_set_mwi()
4528  * @dev: the PCI device for which MWI is enabled
4532  * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4534 int pcim_set_mwi(struct pci_dev *dev)  in pcim_set_mwi()  argument
4538 	dr = find_pci_dr(dev);  in pcim_set_mwi()
4540 		return -ENOMEM;  in pcim_set_mwi()
4542 	dr->mwi = 1;  in pcim_set_mwi()
4543 	return pci_set_mwi(dev);  in pcim_set_mwi()
4548  * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
4549  * @dev: the PCI device for which MWI is enabled
4551  * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
4554  * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4556 int pci_try_set_mwi(struct pci_dev *dev)  in pci_try_set_mwi()  argument
4561 	return pci_set_mwi(dev);  in pci_try_set_mwi()
4567  * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
4568  * @dev: the PCI device to disable
4570  * Disables PCI Memory-Write-Invalidate transaction on the device
4572 void pci_clear_mwi(struct pci_dev *dev)  in pci_clear_mwi()  argument
4577 	pci_read_config_word(dev, PCI_COMMAND, &cmd);  in pci_clear_mwi()
4580 		pci_write_config_word(dev, PCI_COMMAND, cmd);  in pci_clear_mwi()
4587  * pci_disable_parity - disable parity checking for device
4588  * @dev: the PCI device to operate on
4590  * Disable parity checking for device @dev
4592 void pci_disable_parity(struct pci_dev *dev)  in pci_disable_parity()  argument
4596 	pci_read_config_word(dev, PCI_COMMAND, &cmd);  in pci_disable_parity()
4599 		pci_write_config_word(dev, PCI_COMMAND, cmd);  in pci_disable_parity()
4604  * pci_intx - enables/disables PCI INTx for device dev
4605  * @pdev: the PCI device to operate on
4606  * @enable: boolean: whether to enable or disable PCI INTx
4608  * Enables/disables PCI INTx for device @pdev
4627 		if (dr && !dr->restore_intx) {  in pci_intx()
4628 			dr->restore_intx = 1;  in pci_intx()
4629 			dr->orig_intx = !enable;  in pci_intx()
4635 static bool pci_check_and_set_intx_mask(struct pci_dev *dev, bool mask)  in pci_check_and_set_intx_mask()  argument
4637 	struct pci_bus *bus = dev->bus;  in pci_check_and_set_intx_mask()
4653 	bus->ops->read(bus, dev->devfn, PCI_COMMAND, 4, &cmd_status_dword);  in pci_check_and_set_intx_mask()
4672 		bus->ops->write(bus, dev->devfn, PCI_COMMAND, 2, newcmd);  in pci_check_and_set_intx_mask()
4681  * pci_check_and_mask_intx - mask INTx on pending interrupt
4682  * @dev: the PCI device to operate on
4684  * Check if the device dev has its INTx line asserted, mask it and return
4687 bool pci_check_and_mask_intx(struct pci_dev *dev)  in pci_check_and_mask_intx()  argument
4689 	return pci_check_and_set_intx_mask(dev, true);  in pci_check_and_mask_intx()
4694  * pci_check_and_unmask_intx - unmask INTx if no interrupt is pending
4695  * @dev: the PCI device to operate on
4697  * Check if the device dev has its INTx line asserted, unmask it if not and
4701 bool pci_check_and_unmask_intx(struct pci_dev *dev)  in pci_check_and_unmask_intx()  argument
4703 	return pci_check_and_set_intx_mask(dev, false);  in pci_check_and_unmask_intx()
4708  * pci_wait_for_pending_transaction - wait for pending transaction
4709  * @dev: the PCI device to operate on
4713 int pci_wait_for_pending_transaction(struct pci_dev *dev)  in pci_wait_for_pending_transaction()  argument
4715 	if (!pci_is_pcie(dev))  in pci_wait_for_pending_transaction()
4718 	return pci_wait_for_pending(dev, pci_pcie_cap(dev) + PCI_EXP_DEVSTA,  in pci_wait_for_pending_transaction()
4724  * pcie_flr - initiate a PCIe function level reset
4725  * @dev: device to reset
4727  * Initiate a function level reset unconditionally on @dev without
4730 int pcie_flr(struct pci_dev *dev)  in pcie_flr()  argument
4732 	if (!pci_wait_for_pending_transaction(dev))  in pcie_flr()
4733 …pci_err(dev, "timed out waiting for pending transaction; performing function level reset anyway\n"…  in pcie_flr()
4735 	pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);  in pcie_flr()
4737 	if (dev->imm_ready)  in pcie_flr()
4747 	return pci_dev_wait(dev, "FLR", PCIE_RESET_READY_POLL_MS);  in pcie_flr()
4752  * pcie_reset_flr - initiate a PCIe function level reset
4753  * @dev: device to reset
4756  * Initiate a function level reset on @dev.
4758 int pcie_reset_flr(struct pci_dev *dev, bool probe)  in pcie_reset_flr()  argument
4760 	if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET)  in pcie_reset_flr()
4761 		return -ENOTTY;  in pcie_reset_flr()
4763 	if (!(dev->devcap & PCI_EXP_DEVCAP_FLR))  in pcie_reset_flr()
4764 		return -ENOTTY;  in pcie_reset_flr()
4769 	return pcie_flr(dev);  in pcie_reset_flr()
4773 static int pci_af_flr(struct pci_dev *dev, bool probe)  in pci_af_flr()  argument
4778 	pos = pci_find_capability(dev, PCI_CAP_ID_AF);  in pci_af_flr()
4780 		return -ENOTTY;  in pci_af_flr()
4782 	if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET)  in pci_af_flr()
4783 		return -ENOTTY;  in pci_af_flr()
4785 	pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap);  in pci_af_flr()
4787 		return -ENOTTY;  in pci_af_flr()
4793 	 * Wait for Transaction Pending bit to clear.  A word-aligned test  in pci_af_flr()
4797 	if (!pci_wait_for_pending(dev, pos + PCI_AF_CTRL,  in pci_af_flr()
4799 …pci_err(dev, "timed out waiting for pending transaction; performing AF function level reset anyway…  in pci_af_flr()
4801 	pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);  in pci_af_flr()
4803 	if (dev->imm_ready)  in pci_af_flr()
4807 	 * Per Advanced Capabilities for Conventional PCI ECN, 13 April 2006,  in pci_af_flr()
4814 	return pci_dev_wait(dev, "AF_FLR", PCIE_RESET_READY_POLL_MS);  in pci_af_flr()
4818  * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0.
4819  * @dev: Device to reset.
4822  * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is
4824  * PCI_D0.  If that's the case and the device is not in a low-power state
4828  * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms
4829  * by default (i.e. unless the @dev's d3hot_delay field has a different value).
4832 static int pci_pm_reset(struct pci_dev *dev, bool probe)  in pci_pm_reset()  argument
4836 	if (!dev->pm_cap || dev->dev_flags & PCI_DEV_FLAGS_NO_PM_RESET)  in pci_pm_reset()
4837 		return -ENOTTY;  in pci_pm_reset()
4839 	pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr);  in pci_pm_reset()
4841 		return -ENOTTY;  in pci_pm_reset()
4846 	if (dev->current_state != PCI_D0)  in pci_pm_reset()
4847 		return -EINVAL;  in pci_pm_reset()
4851 	pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);  in pci_pm_reset()
4852 	pci_dev_d3_sleep(dev);  in pci_pm_reset()
4856 	pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);  in pci_pm_reset()
4857 	pci_dev_d3_sleep(dev);  in pci_pm_reset()
4859 	return pci_dev_wait(dev, "PM D3hot->D0", PCIE_RESET_READY_POLL_MS);  in pci_pm_reset()
4863  * pcie_wait_for_link_delay - Wait until link is active or inactive
4881 	if (!pdev->link_active_reporting) {  in pcie_wait_for_link_delay()
4905 		timeout -= 10;  in pcie_wait_for_link_delay()
4914  * pcie_wait_for_link - Wait until link is active or inactive
4938 	list_for_each_entry(pdev, &bus->devices, bus_list) {  in pci_bus_max_d3cold_delay()
4939 		if (pdev->d3cold_delay < min_delay)  in pci_bus_max_d3cold_delay()
4940 			min_delay = pdev->d3cold_delay;  in pci_bus_max_d3cold_delay()
4941 		if (pdev->d3cold_delay > max_delay)  in pci_bus_max_d3cold_delay()
4942 			max_delay = pdev->d3cold_delay;  in pci_bus_max_d3cold_delay()
4949  * pci_bridge_wait_for_secondary_bus - Wait for secondary bus to be accessible
4950  * @dev: PCI bridge
4956  * conventional PCI it means Tpvrh + Trhfa specified in PCI 3.0 section
4959 void pci_bridge_wait_for_secondary_bus(struct pci_dev *dev)  in pci_bridge_wait_for_secondary_bus()  argument
4964 	if (pci_dev_is_disconnected(dev))  in pci_bridge_wait_for_secondary_bus()
4967 	if (!pci_is_bridge(dev) || !dev->bridge_d3)  in pci_bridge_wait_for_secondary_bus()
4974 	 * For any hot-added devices the access delay is handled in pciehp  in pci_bridge_wait_for_secondary_bus()
4978 	if (!dev->subordinate || list_empty(&dev->subordinate->devices)) {  in pci_bridge_wait_for_secondary_bus()
4984 	delay = pci_bus_max_d3cold_delay(dev->subordinate);  in pci_bridge_wait_for_secondary_bus()
4990 	child = list_first_entry(&dev->subordinate->devices, struct pci_dev,  in pci_bridge_wait_for_secondary_bus()
4995 	 * Conventional PCI and PCI-X we need to wait Tpvrh + Trhfa before  in pci_bridge_wait_for_secondary_bus()
5000 	if (!pci_is_pcie(dev)) {  in pci_bridge_wait_for_secondary_bus()
5001 		pci_dbg(dev, "waiting %d ms for secondary bus\n", 1000 + delay);  in pci_bridge_wait_for_secondary_bus()
5023 	if (!pcie_downstream_port(dev))  in pci_bridge_wait_for_secondary_bus()
5026 	if (pcie_get_speed_cap(dev) <= PCIE_SPEED_5_0GT) {  in pci_bridge_wait_for_secondary_bus()
5027 		pci_dbg(dev, "waiting %d ms for downstream link\n", delay);  in pci_bridge_wait_for_secondary_bus()
5030 		pci_dbg(dev, "waiting %d ms for downstream link, after activation\n",  in pci_bridge_wait_for_secondary_bus()
5032 		if (!pcie_wait_for_link_delay(dev, true, delay)) {  in pci_bridge_wait_for_secondary_bus()
5034 			pci_info(dev, "Data Link Layer Link Active not set in 1000 msec\n");  in pci_bridge_wait_for_secondary_bus()
5045 void pci_reset_secondary_bus(struct pci_dev *dev)  in pci_reset_secondary_bus()  argument
5049 	pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl);  in pci_reset_secondary_bus()
5051 	pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);  in pci_reset_secondary_bus()
5054 	 * PCI spec v3.0 7.6.4.2 requires minimum Trst of 1ms.  Double  in pci_reset_secondary_bus()
5060 	pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);  in pci_reset_secondary_bus()
5063 	 * Trhfa for conventional PCI is 2^25 clock cycles.  in pci_reset_secondary_bus()
5066 	 * be re-initialized.  PCIe has some ways to shorten this,  in pci_reset_secondary_bus()
5072 void __weak pcibios_reset_secondary_bus(struct pci_dev *dev)  in pcibios_reset_secondary_bus()  argument
5074 	pci_reset_secondary_bus(dev);  in pcibios_reset_secondary_bus()
5078  * pci_bridge_secondary_bus_reset - Reset the secondary bus on a PCI bridge.
5079  * @dev: Bridge device
5082  * Devices on the secondary bus are left in power-on state.
5084 int pci_bridge_secondary_bus_reset(struct pci_dev *dev)  in pci_bridge_secondary_bus_reset()  argument
5086 	pcibios_reset_secondary_bus(dev);  in pci_bridge_secondary_bus_reset()
5088 	return pci_dev_wait(dev, "bus reset", PCIE_RESET_READY_POLL_MS);  in pci_bridge_secondary_bus_reset()
5092 static int pci_parent_bus_reset(struct pci_dev *dev, bool probe)  in pci_parent_bus_reset()  argument
5096 	if (pci_is_root_bus(dev->bus) || dev->subordinate ||  in pci_parent_bus_reset()
5097 	    !dev->bus->self || dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)  in pci_parent_bus_reset()
5098 		return -ENOTTY;  in pci_parent_bus_reset()
5100 	list_for_each_entry(pdev, &dev->bus->devices, bus_list)  in pci_parent_bus_reset()
5101 		if (pdev != dev)  in pci_parent_bus_reset()
5102 			return -ENOTTY;  in pci_parent_bus_reset()
5107 	return pci_bridge_secondary_bus_reset(dev->bus->self);  in pci_parent_bus_reset()
5112 	int rc = -ENOTTY;  in pci_reset_hotplug_slot()
5114 	if (!hotplug || !try_module_get(hotplug->owner))  in pci_reset_hotplug_slot()
5117 	if (hotplug->ops->reset_slot)  in pci_reset_hotplug_slot()
5118 		rc = hotplug->ops->reset_slot(hotplug, probe);  in pci_reset_hotplug_slot()
5120 	module_put(hotplug->owner);  in pci_reset_hotplug_slot()
5125 static int pci_dev_reset_slot_function(struct pci_dev *dev, bool probe)  in pci_dev_reset_slot_function()  argument
5127 	if (dev->multifunction || dev->subordinate || !dev->slot ||  in pci_dev_reset_slot_function()
5128 	    dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)  in pci_dev_reset_slot_function()
5129 		return -ENOTTY;  in pci_dev_reset_slot_function()
5131 	return pci_reset_hotplug_slot(dev->slot->hotplug, probe);  in pci_dev_reset_slot_function()
5134 static int pci_reset_bus_function(struct pci_dev *dev, bool probe)  in pci_reset_bus_function()  argument
5138 	rc = pci_dev_reset_slot_function(dev, probe);  in pci_reset_bus_function()
5139 	if (rc != -ENOTTY)  in pci_reset_bus_function()
5141 	return pci_parent_bus_reset(dev, probe);  in pci_reset_bus_function()
5144 void pci_dev_lock(struct pci_dev *dev)  in pci_dev_lock()  argument
5147 	device_lock(&dev->dev);  in pci_dev_lock()
5148 	pci_cfg_access_lock(dev);  in pci_dev_lock()
5153 int pci_dev_trylock(struct pci_dev *dev)  in pci_dev_trylock()  argument
5155 	if (device_trylock(&dev->dev)) {  in pci_dev_trylock()
5156 		if (pci_cfg_access_trylock(dev))  in pci_dev_trylock()
5158 		device_unlock(&dev->dev);  in pci_dev_trylock()
5165 void pci_dev_unlock(struct pci_dev *dev)  in pci_dev_unlock()  argument
5167 	pci_cfg_access_unlock(dev);  in pci_dev_unlock()
5168 	device_unlock(&dev->dev);  in pci_dev_unlock()
5172 static void pci_dev_save_and_disable(struct pci_dev *dev)  in pci_dev_save_and_disable()  argument
5175 			dev->driver ? dev->driver->err_handler : NULL;  in pci_dev_save_and_disable()
5178 	 * dev->driver->err_handler->reset_prepare() is protected against  in pci_dev_save_and_disable()
5179 	 * races with ->remove() by the device lock, which must be held by  in pci_dev_save_and_disable()
5182 	if (err_handler && err_handler->reset_prepare)  in pci_dev_save_and_disable()
5183 		err_handler->reset_prepare(dev);  in pci_dev_save_and_disable()
5186 	 * Wake-up device prior to save.  PM registers default to D0 after  in pci_dev_save_and_disable()
5188 	 * to a non-D0 state anyway.  in pci_dev_save_and_disable()
5190 	pci_set_power_state(dev, PCI_D0);  in pci_dev_save_and_disable()
5192 	pci_save_state(dev);  in pci_dev_save_and_disable()
5195 	 * INTx-disable which is set.  This not only disables MMIO and I/O port  in pci_dev_save_and_disable()
5197 	 * DMA from the device including MSI/MSI-X interrupts.  For PCI 2.3  in pci_dev_save_and_disable()
5198 	 * compliant devices, INTx-disable prevents legacy interrupts.  in pci_dev_save_and_disable()
5200 	pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);  in pci_dev_save_and_disable()
5203 static void pci_dev_restore(struct pci_dev *dev)  in pci_dev_restore()  argument
5206 			dev->driver ? dev->driver->err_handler : NULL;  in pci_dev_restore()
5208 	pci_restore_state(dev);  in pci_dev_restore()
5211 	 * dev->driver->err_handler->reset_done() is protected against  in pci_dev_restore()
5212 	 * races with ->remove() by the device lock, which must be held by  in pci_dev_restore()
5215 	if (err_handler && err_handler->reset_done)  in pci_dev_restore()
5216 		err_handler->reset_done(dev);  in pci_dev_restore()
5219 /* dev->reset_methods[] is a 0-terminated list of indices into this array */
5230 static ssize_t reset_method_show(struct device *dev,  in reset_method_show()  argument
5233 	struct pci_dev *pdev = to_pci_dev(dev);  in reset_method_show()
5238 		m = pdev->reset_methods[i];  in reset_method_show()
5264 static ssize_t reset_method_store(struct device *dev,  in reset_method_store()  argument
5268 	struct pci_dev *pdev = to_pci_dev(dev);  in reset_method_store()
5274 		pdev->reset_methods[0] = 0;  in reset_method_store()
5286 		return -ENOMEM;  in reset_method_store()
5306 		if (n == PCI_NUM_RESET_METHODS - 1) {  in reset_method_store()
5316 	/* Warn if dev-specific supported but not highest priority */  in reset_method_store()
5319 		pci_warn(pdev, "Device-specific reset disabled/de-prioritized by user");  in reset_method_store()
5320 	memcpy(pdev->reset_methods, reset_methods, sizeof(pdev->reset_methods));  in reset_method_store()
5327 	return -EINVAL;  in reset_method_store()
5344 	return a->mode;  in pci_dev_reset_method_attr_is_visible()
5353  * __pci_reset_function_locked - reset a PCI device function while holding
5354  * the @dev mutex lock.
5355  * @dev: PCI device to reset
5358  * other functions in the same device.  The PCI device must be responsive
5359  * to PCI config space in order to use this function.
5364  * Resetting the device will make the contents of PCI configuration space
5372 int __pci_reset_function_locked(struct pci_dev *dev)  in __pci_reset_function_locked()  argument
5379 	 * A reset method returns -ENOTTY if it doesn't support this device and  in __pci_reset_function_locked()
5387 		m = dev->reset_methods[i];  in __pci_reset_function_locked()
5389 			return -ENOTTY;  in __pci_reset_function_locked()
5391 		rc = pci_reset_fn_methods[m].reset_fn(dev, PCI_RESET_DO_RESET);  in __pci_reset_function_locked()
5394 		if (rc != -ENOTTY)  in __pci_reset_function_locked()
5398 	return -ENOTTY;  in __pci_reset_function_locked()
5403  * pci_init_reset_methods - check whether device can be safely reset
5405  * @dev: PCI device to check for reset mechanisms
5408  * other functions in the same device.  The PCI device must be in D0-D3hot
5414 void pci_init_reset_methods(struct pci_dev *dev)  in pci_init_reset_methods()  argument
5424 		rc = pci_reset_fn_methods[m].reset_fn(dev, PCI_RESET_PROBE);  in pci_init_reset_methods()
5426 			dev->reset_methods[i++] = m;  in pci_init_reset_methods()
5427 		else if (rc != -ENOTTY)  in pci_init_reset_methods()
5431 	dev->reset_methods[i] = 0;  in pci_init_reset_methods()
5435  * pci_reset_function - quiesce and reset a PCI device function
5436  * @dev: PCI device to reset
5439  * other functions in the same device.  The PCI device must be responsive
5440  * to PCI config space in order to use this function.
5442  * This function does not just reset the PCI portion of a device, but
5445  * over the reset and takes the PCI device lock.
5450 int pci_reset_function(struct pci_dev *dev)  in pci_reset_function()  argument
5454 	if (!pci_reset_supported(dev))  in pci_reset_function()
5455 		return -ENOTTY;  in pci_reset_function()
5457 	pci_dev_lock(dev);  in pci_reset_function()
5458 	pci_dev_save_and_disable(dev);  in pci_reset_function()
5460 	rc = __pci_reset_function_locked(dev);  in pci_reset_function()
5462 	pci_dev_restore(dev);  in pci_reset_function()
5463 	pci_dev_unlock(dev);  in pci_reset_function()
5470  * pci_reset_function_locked - quiesce and reset a PCI device function
5471  * @dev: PCI device to reset
5474  * other functions in the same device.  The PCI device must be responsive
5475  * to PCI config space in order to use this function.
5477  * This function does not just reset the PCI portion of a device, but
5481  * requires the PCI device lock to be held.
5486 int pci_reset_function_locked(struct pci_dev *dev)  in pci_reset_function_locked()  argument
5490 	if (!pci_reset_supported(dev))  in pci_reset_function_locked()
5491 		return -ENOTTY;  in pci_reset_function_locked()
5493 	pci_dev_save_and_disable(dev);  in pci_reset_function_locked()
5495 	rc = __pci_reset_function_locked(dev);  in pci_reset_function_locked()
5497 	pci_dev_restore(dev);  in pci_reset_function_locked()
5504  * pci_try_reset_function - quiesce and reset a PCI device function
5505  * @dev: PCI device to reset
5507  * Same as above, except return -EAGAIN if unable to lock device.
5509 int pci_try_reset_function(struct pci_dev *dev)  in pci_try_reset_function()  argument
5513 	if (!pci_reset_supported(dev))  in pci_try_reset_function()
5514 		return -ENOTTY;  in pci_try_reset_function()
5516 	if (!pci_dev_trylock(dev))  in pci_try_reset_function()
5517 		return -EAGAIN;  in pci_try_reset_function()
5519 	pci_dev_save_and_disable(dev);  in pci_try_reset_function()
5520 	rc = __pci_reset_function_locked(dev);  in pci_try_reset_function()
5521 	pci_dev_restore(dev);  in pci_try_reset_function()
5522 	pci_dev_unlock(dev);  in pci_try_reset_function()
5531 	struct pci_dev *dev;  in pci_bus_resetable()  local
5534 	if (bus->self && (bus->self->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET))  in pci_bus_resetable()
5537 	list_for_each_entry(dev, &bus->devices, bus_list) {  in pci_bus_resetable()
5538 		if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET ||  in pci_bus_resetable()
5539 		    (dev->subordinate && !pci_bus_resetable(dev->subordinate)))  in pci_bus_resetable()
5549 	struct pci_dev *dev;  in pci_bus_lock()  local
5551 	list_for_each_entry(dev, &bus->devices, bus_list) {  in pci_bus_lock()
5552 		pci_dev_lock(dev);  in pci_bus_lock()
5553 		if (dev->subordinate)  in pci_bus_lock()
5554 			pci_bus_lock(dev->subordinate);  in pci_bus_lock()
5561 	struct pci_dev *dev;  in pci_bus_unlock()  local
5563 	list_for_each_entry(dev, &bus->devices, bus_list) {  in pci_bus_unlock()
5564 		if (dev->subordinate)  in pci_bus_unlock()
5565 			pci_bus_unlock(dev->subordinate);  in pci_bus_unlock()
5566 		pci_dev_unlock(dev);  in pci_bus_unlock()
5573 	struct pci_dev *dev;  in pci_bus_trylock()  local
5575 	list_for_each_entry(dev, &bus->devices, bus_list) {  in pci_bus_trylock()
5576 		if (!pci_dev_trylock(dev))  in pci_bus_trylock()
5578 		if (dev->subordinate) {  in pci_bus_trylock()
5579 			if (!pci_bus_trylock(dev->subordinate)) {  in pci_bus_trylock()
5580 				pci_dev_unlock(dev);  in pci_bus_trylock()
5588 	list_for_each_entry_continue_reverse(dev, &bus->devices, bus_list) {  in pci_bus_trylock()
5589 		if (dev->subordinate)  in pci_bus_trylock()
5590 			pci_bus_unlock(dev->subordinate);  in pci_bus_trylock()
5591 		pci_dev_unlock(dev);  in pci_bus_trylock()
5599 	struct pci_dev *dev;  in pci_slot_resetable()  local
5601 	if (slot->bus->self &&  in pci_slot_resetable()
5602 	    (slot->bus->self->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET))  in pci_slot_resetable()
5605 	list_for_each_entry(dev, &slot->bus->devices, bus_list) {  in pci_slot_resetable()
5606 		if (!dev->slot || dev->slot != slot)  in pci_slot_resetable()
5608 		if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET ||  in pci_slot_resetable()
5609 		    (dev->subordinate && !pci_bus_resetable(dev->subordinate)))  in pci_slot_resetable()
5619 	struct pci_dev *dev;  in pci_slot_lock()  local
5621 	list_for_each_entry(dev, &slot->bus->devices, bus_list) {  in pci_slot_lock()
5622 		if (!dev->slot || dev->slot != slot)  in pci_slot_lock()
5624 		pci_dev_lock(dev);  in pci_slot_lock()
5625 		if (dev->subordinate)  in pci_slot_lock()
5626 			pci_bus_lock(dev->subordinate);  in pci_slot_lock()
5633 	struct pci_dev *dev;  in pci_slot_unlock()  local
5635 	list_for_each_entry(dev, &slot->bus->devices, bus_list) {  in pci_slot_unlock()
5636 		if (!dev->slot || dev->slot != slot)  in pci_slot_unlock()
5638 		if (dev->subordinate)  in pci_slot_unlock()
5639 			pci_bus_unlock(dev->subordinate);  in pci_slot_unlock()
5640 		pci_dev_unlock(dev);  in pci_slot_unlock()
5647 	struct pci_dev *dev;  in pci_slot_trylock()  local
5649 	list_for_each_entry(dev, &slot->bus->devices, bus_list) {  in pci_slot_trylock()
5650 		if (!dev->slot || dev->slot != slot)  in pci_slot_trylock()
5652 		if (!pci_dev_trylock(dev))  in pci_slot_trylock()
5654 		if (dev->subordinate) {  in pci_slot_trylock()
5655 			if (!pci_bus_trylock(dev->subordinate)) {  in pci_slot_trylock()
5656 				pci_dev_unlock(dev);  in pci_slot_trylock()
5664 	list_for_each_entry_continue_reverse(dev,  in pci_slot_trylock()
5665 					     &slot->bus->devices, bus_list) {  in pci_slot_trylock()
5666 		if (!dev->slot || dev->slot != slot)  in pci_slot_trylock()
5668 		if (dev->subordinate)  in pci_slot_trylock()
5669 			pci_bus_unlock(dev->subordinate);  in pci_slot_trylock()
5670 		pci_dev_unlock(dev);  in pci_slot_trylock()
5677  * the @dev mutex lock for the entire tree.
5681 	struct pci_dev *dev;  in pci_bus_save_and_disable_locked()  local
5683 	list_for_each_entry(dev, &bus->devices, bus_list) {  in pci_bus_save_and_disable_locked()
5684 		pci_dev_save_and_disable(dev);  in pci_bus_save_and_disable_locked()
5685 		if (dev->subordinate)  in pci_bus_save_and_disable_locked()
5686 			pci_bus_save_and_disable_locked(dev->subordinate);  in pci_bus_save_and_disable_locked()
5691  * Restore devices from top of the tree down while holding @dev mutex lock
5697 	struct pci_dev *dev;  in pci_bus_restore_locked()  local
5699 	list_for_each_entry(dev, &bus->devices, bus_list) {  in pci_bus_restore_locked()
5700 		pci_dev_restore(dev);  in pci_bus_restore_locked()
5701 		if (dev->subordinate)  in pci_bus_restore_locked()
5702 			pci_bus_restore_locked(dev->subordinate);  in pci_bus_restore_locked()
5708  * the @dev mutex lock for the entire tree.
5712 	struct pci_dev *dev;  in pci_slot_save_and_disable_locked()  local
5714 	list_for_each_entry(dev, &slot->bus->devices, bus_list) {  in pci_slot_save_and_disable_locked()
5715 		if (!dev->slot || dev->slot != slot)  in pci_slot_save_and_disable_locked()
5717 		pci_dev_save_and_disable(dev);  in pci_slot_save_and_disable_locked()
5718 		if (dev->subordinate)  in pci_slot_save_and_disable_locked()
5719 			pci_bus_save_and_disable_locked(dev->subordinate);  in pci_slot_save_and_disable_locked()
5724  * Restore devices from top of the tree down while holding @dev mutex lock
5730 	struct pci_dev *dev;  in pci_slot_restore_locked()  local
5732 	list_for_each_entry(dev, &slot->bus->devices, bus_list) {  in pci_slot_restore_locked()
5733 		if (!dev->slot || dev->slot != slot)  in pci_slot_restore_locked()
5735 		pci_dev_restore(dev);  in pci_slot_restore_locked()
5736 		if (dev->subordinate)  in pci_slot_restore_locked()
5737 			pci_bus_restore_locked(dev->subordinate);  in pci_slot_restore_locked()
5746 		return -ENOTTY;  in pci_slot_reset()
5753 	rc = pci_reset_hotplug_slot(slot->hotplug, probe);  in pci_slot_reset()
5762  * pci_probe_reset_slot - probe whether a PCI slot can be reset
5763  * @slot: PCI slot to probe
5774  * __pci_reset_slot - Try to reset a PCI slot
5775  * @slot: PCI slot to reset
5777  * A PCI bus may host multiple slots, each slot may support a reset mechanism
5783  * through this function.  PCI config space of all devices in the slot and
5786  * Same as above except return -EAGAIN if the slot cannot be locked
5799 		rc = pci_reset_hotplug_slot(slot->hotplug, PCI_RESET_DO_RESET);  in __pci_reset_slot()
5803 		rc = -EAGAIN;  in __pci_reset_slot()
5812 	if (!bus->self || !pci_bus_resetable(bus))  in pci_bus_reset()
5813 		return -ENOTTY;  in pci_bus_reset()
5822 	ret = pci_bridge_secondary_bus_reset(bus->self);  in pci_bus_reset()
5830  * pci_bus_error_reset - reset the bridge's subordinate bus
5839 	struct pci_bus *bus = bridge->subordinate;  in pci_bus_error_reset()
5843 		return -ENOTTY;  in pci_bus_error_reset()
5846 	if (list_empty(&bus->slots))  in pci_bus_error_reset()
5849 	list_for_each_entry(slot, &bus->slots, list)  in pci_bus_error_reset()
5853 	list_for_each_entry(slot, &bus->slots, list)  in pci_bus_error_reset()
5861 	return pci_bus_reset(bridge->subordinate, PCI_RESET_DO_RESET);  in pci_bus_error_reset()
5865  * pci_probe_reset_bus - probe whether a PCI bus can be reset
5866  * @bus: PCI bus to probe
5877  * __pci_reset_bus - Try to reset a PCI bus
5878  * @bus: top level PCI bus to reset
5880  * Same as above except return -EAGAIN if the bus cannot be locked
5893 		rc = pci_bridge_secondary_bus_reset(bus->self);  in __pci_reset_bus()
5897 		rc = -EAGAIN;  in __pci_reset_bus()
5903  * pci_reset_bus - Try to reset a PCI bus
5904  * @pdev: top level PCI device to reset via slot/bus
5906  * Same as above except return -EAGAIN if the bus cannot be locked
5910 	return (!pci_probe_reset_slot(pdev->slot)) ?  in pci_reset_bus()
5911 	    __pci_reset_slot(pdev->slot) : __pci_reset_bus(pdev->bus);  in pci_reset_bus()
5916  * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
5917  * @dev: PCI device to query
5922 int pcix_get_max_mmrbc(struct pci_dev *dev)  in pcix_get_max_mmrbc()  argument
5927 	cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);  in pcix_get_max_mmrbc()
5929 		return -EINVAL;  in pcix_get_max_mmrbc()
5931 	if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))  in pcix_get_max_mmrbc()
5932 		return -EINVAL;  in pcix_get_max_mmrbc()
5939  * pcix_get_mmrbc - get PCI-X maximum memory read byte count
5940  * @dev: PCI device to query
5945 int pcix_get_mmrbc(struct pci_dev *dev)  in pcix_get_mmrbc()  argument
5950 	cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);  in pcix_get_mmrbc()
5952 		return -EINVAL;  in pcix_get_mmrbc()
5954 	if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))  in pcix_get_mmrbc()
5955 		return -EINVAL;  in pcix_get_mmrbc()
5962  * pcix_set_mmrbc - set PCI-X maximum memory read byte count
5963  * @dev: PCI device to query
5970 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)  in pcix_set_mmrbc()  argument
5977 		return -EINVAL;  in pcix_set_mmrbc()
5979 	v = ffs(mmrbc) - 10;  in pcix_set_mmrbc()
5981 	cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);  in pcix_set_mmrbc()
5983 		return -EINVAL;  in pcix_set_mmrbc()
5985 	if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))  in pcix_set_mmrbc()
5986 		return -EINVAL;  in pcix_set_mmrbc()
5989 		return -E2BIG;  in pcix_set_mmrbc()
5991 	if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))  in pcix_set_mmrbc()
5992 		return -EINVAL;  in pcix_set_mmrbc()
5996 		if (v > o && (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))  in pcix_set_mmrbc()
5997 			return -EIO;  in pcix_set_mmrbc()
6001 		if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd))  in pcix_set_mmrbc()
6002 			return -EIO;  in pcix_set_mmrbc()
6009  * pcie_get_readrq - get PCI Express read request size
6010  * @dev: PCI device to query
6014 int pcie_get_readrq(struct pci_dev *dev)  in pcie_get_readrq()  argument
6018 	pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);  in pcie_get_readrq()
6025  * pcie_set_readrq - set PCI Express maximum memory read request
6026  * @dev: PCI device to query
6032 int pcie_set_readrq(struct pci_dev *dev, int rq)  in pcie_set_readrq()  argument
6038 		return -EINVAL;  in pcie_set_readrq()
6046 		int mps = pcie_get_mps(dev);  in pcie_set_readrq()
6052 	v = (ffs(rq) - 8) << 12;  in pcie_set_readrq()
6054 	ret = pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,  in pcie_set_readrq()
6062  * pcie_get_mps - get PCI Express maximum payload size
6063  * @dev: PCI device to query
6067 int pcie_get_mps(struct pci_dev *dev)  in pcie_get_mps()  argument
6071 	pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);  in pcie_get_mps()
6078  * pcie_set_mps - set PCI Express maximum payload size
6079  * @dev: PCI device to query
6085 int pcie_set_mps(struct pci_dev *dev, int mps)  in pcie_set_mps()  argument
6091 		return -EINVAL;  in pcie_set_mps()
6093 	v = ffs(mps) - 8;  in pcie_set_mps()
6094 	if (v > dev->pcie_mpss)  in pcie_set_mps()
6095 		return -EINVAL;  in pcie_set_mps()
6098 	ret = pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,  in pcie_set_mps()
6106  * pcie_bandwidth_available - determine minimum link settings of a PCIe
6108  * @dev: PCI device to query
6113  * Walk up the PCI device chain and find the point where the minimum
6119 u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,  in pcie_bandwidth_available()  argument
6135 	while (dev) {  in pcie_bandwidth_available()
6136 		pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta);  in pcie_bandwidth_available()
6149 				*limiting_dev = dev;  in pcie_bandwidth_available()
6156 		dev = pci_upstream_bridge(dev);  in pcie_bandwidth_available()
6164  * pcie_get_speed_cap - query for the PCI device's link speed capability
6165  * @dev: PCI device to query
6167  * Query the PCI device speed capability.  Return the maximum link speed
6170 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev)  in pcie_get_speed_cap()  argument
6183 	pcie_capability_read_dword(dev, PCI_EXP_LNKCAP2, &lnkcap2);  in pcie_get_speed_cap()
6185 	/* PCIe r3.0-compliant */  in pcie_get_speed_cap()
6189 	pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap);  in pcie_get_speed_cap()
6200  * pcie_get_width_cap - query for the PCI device's link width capability
6201  * @dev: PCI device to query
6203  * Query the PCI device width capability.  Return the maximum link width
6206 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev)  in pcie_get_width_cap()  argument
6210 	pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap);  in pcie_get_width_cap()
6219  * pcie_bandwidth_capable - calculate a PCI device's link bandwidth capability
6220  * @dev: PCI device
6224  * Calculate a PCI device's link bandwidth by querying for its link speed
6228 u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed,  in pcie_bandwidth_capable()  argument
6231 	*speed = pcie_get_speed_cap(dev);  in pcie_bandwidth_capable()
6232 	*width = pcie_get_width_cap(dev);  in pcie_bandwidth_capable()
6241  * __pcie_print_link_status - Report the PCI device's link speed and width
6242  * @dev: PCI device to query
6250 void __pcie_print_link_status(struct pci_dev *dev, bool verbose)  in __pcie_print_link_status()  argument
6257 	bw_cap = pcie_bandwidth_capable(dev, &speed_cap, &width_cap);  in __pcie_print_link_status()
6258 	bw_avail = pcie_bandwidth_available(dev, &limiting_dev, &speed, &width);  in __pcie_print_link_status()
6261 		pci_info(dev, "%u.%03u Gb/s available PCIe bandwidth (%s x%d link)\n",  in __pcie_print_link_status()
6265 …pci_info(dev, "%u.%03u Gb/s available PCIe bandwidth, limited by %s x%d link at %s (capable of %u.…  in __pcie_print_link_status()
6274  * pcie_print_link_status - Report the PCI device's link speed and width
6275  * @dev: PCI device to query
6279 void pcie_print_link_status(struct pci_dev *dev)  in pcie_print_link_status()  argument
6281 	__pcie_print_link_status(dev, true);  in pcie_print_link_status()
6286  * pci_select_bars - Make BAR mask from the type of resource
6287  * @dev: the PCI device for which BAR mask is made
6292 int pci_select_bars(struct pci_dev *dev, unsigned long flags)  in pci_select_bars()  argument
6296 		if (pci_resource_flags(dev, i) & flags)  in pci_select_bars()
6310 static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode,  in pci_set_vga_state_arch()  argument
6314 		return arch_set_vga_state(dev, decode, command_bits,  in pci_set_vga_state_arch()
6320  * pci_set_vga_state - set VGA decode state on device and parents if requested
6321  * @dev: the PCI device
6327 int pci_set_vga_state(struct pci_dev *dev, bool decode,  in pci_set_vga_state()  argument
6338 	rc = pci_set_vga_state_arch(dev, decode, command_bits, flags);  in pci_set_vga_state()
6343 		pci_read_config_word(dev, PCI_COMMAND, &cmd);  in pci_set_vga_state()
6348 		pci_write_config_word(dev, PCI_COMMAND, cmd);  in pci_set_vga_state()
6354 	bus = dev->bus;  in pci_set_vga_state()
6356 		bridge = bus->self;  in pci_set_vga_state()
6367 		bus = bus->parent;  in pci_set_vga_state()
6380 	adev = ACPI_COMPANION(&pdev->dev);  in pci_pr3_present()
6384 	return adev->power.flags.power_resources &&  in pci_pr3_present()
6385 		acpi_has_method(adev->handle, "_PR3");  in pci_pr3_present()
6391  * pci_add_dma_alias - Add a DMA devfn alias for a device
6392  * @dev: the PCI device for which alias is added
6396  * This helper encodes an 8-bit devfn as a bit number in dma_alias_mask
6397  * which is used to program permissible bus-devfn source addresses for DMA
6400  * from their logical bus-devfn.  Examples include device quirks where the
6401  * device simply uses the wrong devfn, as well as non-transparent bridges
6408  * be configured via quirks, such as the PCI fixup header quirk.
6410 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn_from,  in pci_add_dma_alias()  argument
6415 	nr_devfns = min(nr_devfns, (unsigned int)MAX_NR_DEVFNS - devfn_from);  in pci_add_dma_alias()
6416 	devfn_to = devfn_from + nr_devfns - 1;  in pci_add_dma_alias()
6418 	if (!dev->dma_alias_mask)  in pci_add_dma_alias()
6419 		dev->dma_alias_mask = bitmap_zalloc(MAX_NR_DEVFNS, GFP_KERNEL);  in pci_add_dma_alias()
6420 	if (!dev->dma_alias_mask) {  in pci_add_dma_alias()
6421 		pci_warn(dev, "Unable to allocate DMA alias mask\n");  in pci_add_dma_alias()
6425 	bitmap_set(dev->dma_alias_mask, devfn_from, nr_devfns);  in pci_add_dma_alias()
6428 		pci_info(dev, "Enabling fixed DMA alias to %02x.%d\n",  in pci_add_dma_alias()
6431 		pci_info(dev, "Enabling fixed DMA alias for devfn range from %02x.%d to %02x.%d\n",  in pci_add_dma_alias()
6438 	return (dev1->dma_alias_mask &&  in pci_devs_are_dma_aliases()
6439 		test_bit(dev2->devfn, dev1->dma_alias_mask)) ||  in pci_devs_are_dma_aliases()
6440 	       (dev2->dma_alias_mask &&  in pci_devs_are_dma_aliases()
6441 		test_bit(dev1->devfn, dev2->dma_alias_mask)) ||  in pci_devs_are_dma_aliases()
6452 	return pci_bus_read_dev_vendor_id(pdev->bus, pdev->devfn, &v, 0);  in pci_device_is_present()
6456 void pci_ignore_hotplug(struct pci_dev *dev)  in pci_ignore_hotplug()  argument
6458 	struct pci_dev *bridge = dev->bus->self;  in pci_ignore_hotplug()
6460 	dev->ignore_hotplug = 1;  in pci_ignore_hotplug()
6463 		bridge->ignore_hotplug = 1;  in pci_ignore_hotplug()
6468  * pci_real_dma_dev - Get PCI DMA device for PCI device
6469  * @dev: the PCI device that may have a PCI DMA alias
6471  * Permits the platform to provide architecture-specific functionality to
6472  * devices needing to alias DMA to another PCI device on another PCI bus. If
6473  * the PCI device is on the same bus, it is recommended to use
6477 struct pci_dev __weak *pci_real_dma_dev(struct pci_dev *dev)  in pci_real_dma_dev()  argument
6479 	return dev;  in pci_real_dma_dev()
6488  * Arches that don't want to expose struct resource to userland as-is in
6491 void __weak pci_resource_to_user(const struct pci_dev *dev, int bar,  in pci_resource_to_user()  argument
6495 	*start = rsrc->start;  in pci_resource_to_user()
6496 	*end = rsrc->end;  in pci_resource_to_user()
6503  * pci_specified_resource_alignment - get resource alignment specified by user.
6504  * @dev: the PCI device to get
6510 static resource_size_t pci_specified_resource_alignment(struct pci_dev *dev,  in pci_specified_resource_alignment()  argument
6524 		pr_info_once("PCI: Ignoring requested alignments (PCI_PROBE_ONLY)\n");  in pci_specified_resource_alignment()
6534 				pr_err("PCI: Invalid requested alignment (order %d)\n",  in pci_specified_resource_alignment()
6542 		ret = pci_dev_str_match(dev, p, &p);  in pci_specified_resource_alignment()
6548 			pr_err("PCI: Can't parse resource_alignment parameter: %s\n",  in pci_specified_resource_alignment()
6564 static void pci_request_resource_alignment(struct pci_dev *dev, int bar,  in pci_request_resource_alignment()  argument
6567 	struct resource *r = &dev->resource[bar];  in pci_request_resource_alignment()
6570 	if (!(r->flags & IORESOURCE_MEM))  in pci_request_resource_alignment()
6573 	if (r->flags & IORESOURCE_PCI_FIXED) {  in pci_request_resource_alignment()
6574 		pci_info(dev, "BAR%d %pR: ignoring requested alignment %#llx\n",  in pci_request_resource_alignment()
6600 	 *    set r->start to the desired alignment.  By itself this  in pci_request_resource_alignment()
6606 	 * the "pci=resource_alignment" argument, "resize" is true and we  in pci_request_resource_alignment()
6611 	pci_info(dev, "BAR%d %pR: requesting alignment to %#llx\n",  in pci_request_resource_alignment()
6615 		r->start = 0;  in pci_request_resource_alignment()
6616 		r->end = align - 1;  in pci_request_resource_alignment()
6618 		r->flags &= ~IORESOURCE_SIZEALIGN;  in pci_request_resource_alignment()
6619 		r->flags |= IORESOURCE_STARTALIGN;  in pci_request_resource_alignment()
6620 		r->start = align;  in pci_request_resource_alignment()
6621 		r->end = r->start + size - 1;  in pci_request_resource_alignment()
6623 	r->flags |= IORESOURCE_UNSET;  in pci_request_resource_alignment()
6628  * of the device specified by kernel's boot parameter 'pci=resource_alignment='.
6630  * Later on, the kernel will assign page-aligned memory resource back
6633 void pci_reassigndev_resource_alignment(struct pci_dev *dev)  in pci_reassigndev_resource_alignment()  argument
6642 	 * VF BARs are read-only zero according to SR-IOV spec r1.1, sec  in pci_reassigndev_resource_alignment()
6644 	 * described by the VF BARx register in the PF's SR-IOV capability.  in pci_reassigndev_resource_alignment()
6647 	if (dev->is_virtfn)  in pci_reassigndev_resource_alignment()
6650 	/* check if specified PCI is target device to reassign */  in pci_reassigndev_resource_alignment()
6651 	align = pci_specified_resource_alignment(dev, &resize);  in pci_reassigndev_resource_alignment()
6655 	if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL &&  in pci_reassigndev_resource_alignment()
6656 	    (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) {  in pci_reassigndev_resource_alignment()
6657 		pci_warn(dev, "Can't reassign resources to host bridge\n");  in pci_reassigndev_resource_alignment()
6661 	pci_read_config_word(dev, PCI_COMMAND, &command);  in pci_reassigndev_resource_alignment()
6663 	pci_write_config_word(dev, PCI_COMMAND, command);  in pci_reassigndev_resource_alignment()
6666 		pci_request_resource_alignment(dev, i, align, resize);  in pci_reassigndev_resource_alignment()
6673 	if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {  in pci_reassigndev_resource_alignment()
6675 			r = &dev->resource[i];  in pci_reassigndev_resource_alignment()
6676 			if (!(r->flags & IORESOURCE_MEM))  in pci_reassigndev_resource_alignment()
6678 			r->flags |= IORESOURCE_UNSET;  in pci_reassigndev_resource_alignment()
6679 			r->end = resource_size(r) - 1;  in pci_reassigndev_resource_alignment()
6680 			r->start = 0;  in pci_reassigndev_resource_alignment()
6682 		pci_disable_bridge_window(dev);  in pci_reassigndev_resource_alignment()
6703 	if (count >= (PAGE_SIZE - 1))  in resource_alignment_store()
6704 		return -EINVAL;  in resource_alignment_store()
6708 		return -ENOMEM;  in resource_alignment_store()
6746 static atomic_t __domain_nr = ATOMIC_INIT(-1);
6755 	static int use_dt_domains = -1;  in of_pci_bus_find_domain_nr()
6756 	int domain = -1;  in of_pci_bus_find_domain_nr()
6759 		domain = of_get_pci_domain_nr(parent->of_node);  in of_pci_bus_find_domain_nr()
6784 	 * invalidating the domain value (domain = -1) and printing a  in of_pci_bus_find_domain_nr()
6794 			pr_err("Node %pOF has ", parent->of_node);  in of_pci_bus_find_domain_nr()
6795 		pr_err("Inconsistent \"linux,pci-domain\" property in DT\n");  in of_pci_bus_find_domain_nr()
6796 		domain = -1;  in of_pci_bus_find_domain_nr()
6810  * pci_ext_cfg_avail - can we access extended PCI config space?
6812  * Returns 1 if we can access PCI extended config space (offsets
6885 				pr_err("PCI: Unknown option `%s'\n", str);  in pci_setup()
6892 early_param("pci", pci_setup);