Lines Matching +full:inactive +full:- +full:delay +full:- +full:ms
1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
6 * David Mosberger-Tang
8 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
13 #include <linux/delay.h>
69 unsigned int delay_ms = max(dev->d3hot_delay, pci_pm_d3hot_delay); in pci_dev_d3_sleep()
73 /* Use a 20% upper bound, 1ms minimum */ in pci_dev_d3_sleep()
82 return dev->reset_methods[0] != 0; in pci_reset_supported()
101 * pci=hpmmiosize=nnM overrides non-prefetchable MMIO size,
112 /* PCIe MPS/MRRS strategy; can be overridden by kernel command-line param */
129 * measured in 32-bit words, not bytes.
174 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
185 max = bus->busn_res.end; in pci_bus_max_busnr()
186 list_for_each_entry(tmp, &bus->children, node) { in pci_bus_max_busnr()
196 * pci_status_get_and_clear_errors - return and clear error bits in PCI_STATUS
208 return -EIO; in pci_status_get_and_clear_errors()
222 struct resource *res = &pdev->resource[bar]; in __pci_ioremap_resource()
223 resource_size_t start = res->start; in __pci_ioremap_resource()
229 if (res->flags & IORESOURCE_UNSET || !(res->flags & IORESOURCE_MEM)) { in __pci_ioremap_resource()
254 * pci_dev_str_match_path - test if a path string matches a device
265 * A path for a device can be obtained using 'lspci -t'. Using a path
282 wpath = kmemdup_nul(path, *endptr - path, GFP_ATOMIC); in pci_dev_str_match_path()
284 return -ENOMEM; in pci_dev_str_match_path()
292 ret = -EINVAL; in pci_dev_str_match_path()
296 if (dev->devfn != PCI_DEVFN(slot, func)) { in pci_dev_str_match_path()
322 ret = -EINVAL; in pci_dev_str_match_path()
327 ret = (seg == pci_domain_nr(dev->bus) && in pci_dev_str_match_path()
328 bus == dev->bus->number && in pci_dev_str_match_path()
329 dev->devfn == PCI_DEVFN(slot, func)); in pci_dev_str_match_path()
337 * pci_dev_str_match - test if a string matches a device
354 * through the use of 'lspci -t'.
359 * in-kernel code that uses PCI_ANY_ID which is ~0; this is for
381 return -EINVAL; in pci_dev_str_match()
389 if ((!vendor || vendor == dev->vendor) && in pci_dev_str_match()
390 (!device || device == dev->device) && in pci_dev_str_match()
392 subsystem_vendor == dev->subsystem_vendor) && in pci_dev_str_match()
394 subsystem_device == dev->subsystem_device)) in pci_dev_str_match()
424 while ((*ttl)--) { in __pci_find_next_cap_ttl()
450 return __pci_find_next_cap(dev->bus, dev->devfn, in pci_find_next_capability()
476 * pci_find_capability - query for devices' capabilities
491 * %PCI_CAP_ID_PCIX PCI-X
498 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); in pci_find_capability()
500 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap); in pci_find_capability()
507 * pci_bus_find_capability - query for devices' capabilities
534 * pci_find_next_ext_capability - Find an extended capability
542 * vendor-specific capability, and this provides a way to find them all.
551 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; in pci_find_next_ext_capability()
553 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE) in pci_find_next_ext_capability()
569 while (ttl-- > 0) { in pci_find_next_ext_capability()
586 * pci_find_ext_capability - Find an extended capability
606 * pci_get_dsn - Read and return the 8-byte Device Serial Number
649 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos, in __pci_find_next_ht_cap()
659 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, in __pci_find_next_ht_cap()
668 * pci_find_next_ht_capability - query a device's HyperTransport capabilities
687 * pci_find_ht_capability - query a device's HyperTransport capabilities
701 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); in pci_find_ht_capability()
710 * pci_find_vsec_capability - Find a vendor-specific extended capability
713 * @cap: Vendor-specific capability ID
724 if (vendor != dev->vendor) in pci_find_vsec_capability()
740 * pci_find_dvsec_capability - Find DVSEC for vendor
743 * @dvsec: Designated Vendor-specific capability ID
772 * pci_find_parent_resource - return resource region of parent bus of given
783 const struct pci_bus *bus = dev->bus; in pci_find_parent_resource()
796 if (r->flags & IORESOURCE_PREFETCH && in pci_find_parent_resource()
797 !(res->flags & IORESOURCE_PREFETCH)) in pci_find_parent_resource()
802 * be both a positively-decoded aperture and a in pci_find_parent_resource()
803 * subtractively-decoded region that contain the BAR. in pci_find_parent_resource()
804 * We want the positively-decoded one, so this depends in pci_find_parent_resource()
816 * pci_find_resource - Return matching PCI device resource
829 struct resource *r = &dev->resource[i]; in pci_find_resource()
831 if (r->start && resource_contains(r, res)) in pci_find_resource()
840 * pci_wait_for_pending - wait for @mask bit(s) to clear in status word @pos
855 msleep((1 << (i - 1)) * 100); in pci_wait_for_pending()
868 * pci_request_acs - ask for ACS to be enabled if supported
878 * pci_disable_acs_redir - disable ACS redirect capabilities
919 pos = dev->acs_cap; in pci_disable_acs_redir()
936 * pci_std_enable_acs - enable ACS on devices using standard ACS capabilities
945 pos = dev->acs_cap; in pci_std_enable_acs()
965 if (pci_ats_disabled() || dev->external_facing || dev->untrusted) in pci_std_enable_acs()
972 * pci_enable_acs - enable ACS if hardware support it
997 * pci_restore_bars - restore a device's BAR values (e.g. after wake-up)
1075 * pci_update_current_state - Read power state of given device and cache it
1089 dev->current_state = PCI_D3cold; in pci_update_current_state()
1090 } else if (dev->pm_cap) { in pci_update_current_state()
1093 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); in pci_update_current_state()
1095 dev->current_state = PCI_D3cold; in pci_update_current_state()
1098 dev->current_state = pmcsr & PCI_PM_CTRL_STATE_MASK; in pci_update_current_state()
1100 dev->current_state = state; in pci_update_current_state()
1105 * pci_refresh_power_state - Refresh the given device's power state data
1114 pci_update_current_state(dev, dev->current_state); in pci_refresh_power_state()
1118 * pci_platform_power_transition - Use platform to change device power state
1129 else if (!dev->pm_cap) /* Fall back to PCI_D0 */ in pci_platform_power_transition()
1130 dev->current_state = PCI_D0; in pci_platform_power_transition()
1138 pm_request_resume(&pci_dev->dev); in pci_resume_one()
1143 * pci_resume_bus - Walk given bus and runtime resume devices on it
1154 int delay = 1; in pci_dev_wait() local
1165 * Wait for the device to return a non-CRS completion. Read the in pci_dev_wait()
1171 if (delay > timeout) { in pci_dev_wait()
1173 delay - 1, reset_type); in pci_dev_wait()
1174 return -ENOTTY; in pci_dev_wait()
1177 if (delay > 1000) in pci_dev_wait()
1179 delay - 1, reset_type); in pci_dev_wait()
1181 msleep(delay); in pci_dev_wait()
1182 delay *= 2; in pci_dev_wait()
1186 if (delay > 1000) in pci_dev_wait()
1187 pci_info(dev, "ready %dms after %s\n", delay - 1, in pci_dev_wait()
1194 * pci_power_up - Put the given device into D0
1208 if (!dev->pm_cap) { in pci_power_up()
1211 dev->current_state = PCI_D0; in pci_power_up()
1213 dev->current_state = state; in pci_power_up()
1218 return -EIO; in pci_power_up()
1221 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); in pci_power_up()
1224 pci_power_name(dev->current_state)); in pci_power_up()
1225 dev->current_state = PCI_D3cold; in pci_power_up()
1226 return -EIO; in pci_power_up()
1231 need_restore = (state == PCI_D3hot || dev->current_state >= PCI_D3hot) && in pci_power_up()
1241 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, 0); in pci_power_up()
1250 dev->current_state = PCI_D0; in pci_power_up()
1258 * pci_set_full_power_state - Put a PCI device into D0 and update its state
1278 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); in pci_set_full_power_state()
1279 dev->current_state = pmcsr & PCI_PM_CTRL_STATE_MASK; in pci_set_full_power_state()
1280 if (dev->current_state != PCI_D0) { in pci_set_full_power_state()
1282 pci_power_name(dev->current_state)); in pci_set_full_power_state()
1304 * __pci_dev_set_current_state - Set current state of a PCI device
1312 dev->current_state = state; in __pci_dev_set_current_state()
1317 * pci_bus_set_current_state - Walk given bus and set current state of devices
1328 * pci_set_low_power_state - Put a PCI device into a low-power state.
1332 * Use the device's PCI_PM_CTRL register to put it into a low-power state.
1335 * -EINVAL if the requested state is invalid.
1336 * -EIO if device does not support PCI PM or its PM capabilities register has a
1345 if (!dev->pm_cap) in pci_set_low_power_state()
1346 return -EIO; in pci_set_low_power_state()
1350 * we're already in a low-power state, we can only go deeper. E.g., in pci_set_low_power_state()
1354 if (dev->current_state <= PCI_D3cold && dev->current_state > state) { in pci_set_low_power_state()
1356 pci_power_name(dev->current_state), in pci_set_low_power_state()
1358 return -EINVAL; in pci_set_low_power_state()
1362 if ((state == PCI_D1 && !dev->d1_support) in pci_set_low_power_state()
1363 || (state == PCI_D2 && !dev->d2_support)) in pci_set_low_power_state()
1364 return -EIO; in pci_set_low_power_state()
1366 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); in pci_set_low_power_state()
1369 pci_power_name(dev->current_state), in pci_set_low_power_state()
1371 dev->current_state = PCI_D3cold; in pci_set_low_power_state()
1372 return -EIO; in pci_set_low_power_state()
1379 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); in pci_set_low_power_state()
1387 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); in pci_set_low_power_state()
1388 dev->current_state = pmcsr & PCI_PM_CTRL_STATE_MASK; in pci_set_low_power_state()
1389 if (dev->current_state != state) in pci_set_low_power_state()
1391 pci_power_name(dev->current_state), in pci_set_low_power_state()
1398 * pci_set_power_state - Set the power state of a PCI device
1406 * -EINVAL if the requested state is invalid.
1407 * -EIO if device does not support PCI PM or its PM capabilities register has a
1434 if (dev->current_state == state) in pci_set_power_state()
1444 if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3)) in pci_set_power_state()
1458 if (dev->current_state == PCI_D3cold) in pci_set_power_state()
1459 pci_bus_set_current_state(dev->subordinate, PCI_D3cold); in pci_set_power_state()
1478 hlist_for_each_entry(tmp, &pci_dev->saved_cap_space, next) { in _pci_find_saved_cap()
1479 if (tmp->cap.cap_extended == extended && tmp->cap.cap_nr == cap) in _pci_find_saved_cap()
1507 return -ENOMEM; in pci_save_pcie_state()
1510 cap = (u16 *)&save_state->cap.data[0]; in pci_save_pcie_state()
1529 if (bridge && bridge->ltr_path) { in pci_bridge_reconfigure_ltr()
1532 pci_dbg(bridge, "re-enabling LTR\n"); in pci_bridge_reconfigure_ltr()
1552 * Check and re-configure the bit here before restoring device. in pci_restore_pcie_state()
1557 cap = (u16 *)&save_state->cap.data[0]; in pci_restore_pcie_state()
1579 return -ENOMEM; in pci_save_pcix_state()
1583 (u16 *)save_state->cap.data); in pci_save_pcix_state()
1598 cap = (u16 *)&save_state->cap.data[0]; in pci_restore_pcix_state()
1623 cap = &save_state->cap.data[0]; in pci_save_ltr_state()
1639 cap = &save_state->cap.data[0]; in pci_restore_ltr_state()
1644 * pci_save_state - save the PCI configuration space of a device before
1653 pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]); in pci_save_state()
1655 i * 4, dev->saved_config_space[i]); in pci_save_state()
1657 dev->state_saved = true; in pci_save_state()
1689 if (retry-- <= 0) in pci_restore_config_dword()
1706 for (index = end; index >= start; index--) in pci_restore_config_space_range()
1708 pdev->saved_config_space[index], in pci_restore_config_space_range()
1714 if (pdev->hdr_type == PCI_HEADER_TYPE_NORMAL) { in pci_restore_config_space()
1719 } else if (pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE) { in pci_restore_config_space()
1753 res = pdev->resource + bar_idx; in pci_restore_rebar_state()
1762 * pci_restore_state - Restore the saved state of a PCI device
1767 if (!dev->state_saved) in pci_restore_state()
1798 dev->state_saved = false; in pci_restore_state()
1808 * pci_store_saved_state - Allocate and return an opaque struct containing
1821 if (!dev->state_saved) in pci_store_saved_state()
1826 hlist_for_each_entry(tmp, &dev->saved_cap_space, next) in pci_store_saved_state()
1827 size += sizeof(struct pci_cap_saved_data) + tmp->cap.size; in pci_store_saved_state()
1833 memcpy(state->config_space, dev->saved_config_space, in pci_store_saved_state()
1834 sizeof(state->config_space)); in pci_store_saved_state()
1836 cap = state->cap; in pci_store_saved_state()
1837 hlist_for_each_entry(tmp, &dev->saved_cap_space, next) { in pci_store_saved_state()
1838 size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size; in pci_store_saved_state()
1839 memcpy(cap, &tmp->cap, len); in pci_store_saved_state()
1849 * pci_load_saved_state - Reload the provided save state into struct pci_dev.
1858 dev->state_saved = false; in pci_load_saved_state()
1863 memcpy(dev->saved_config_space, state->config_space, in pci_load_saved_state()
1864 sizeof(state->config_space)); in pci_load_saved_state()
1866 cap = state->cap; in pci_load_saved_state()
1867 while (cap->size) { in pci_load_saved_state()
1870 tmp = _pci_find_saved_cap(dev, cap->cap_nr, cap->cap_extended); in pci_load_saved_state()
1871 if (!tmp || tmp->cap.size != cap->size) in pci_load_saved_state()
1872 return -EINVAL; in pci_load_saved_state()
1874 memcpy(tmp->cap.data, cap->data, tmp->cap.size); in pci_load_saved_state()
1876 sizeof(struct pci_cap_saved_data) + cap->size); in pci_load_saved_state()
1879 dev->state_saved = true; in pci_load_saved_state()
1885 * pci_load_and_free_saved_state - Reload the save state pointed to by state,
1913 if (err < 0 && err != -EIO) in do_pci_enable_device()
1925 if (dev->msi_enabled || dev->msix_enabled) in do_pci_enable_device()
1940 * pci_reenable_device - Resume abandoned device
1949 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1); in pci_reenable_device()
1964 if (!dev->is_busmaster) in pci_enable_bridge()
1988 pci_update_current_state(dev, dev->current_state); in pci_enable_device_flags()
1990 if (atomic_inc_return(&dev->enable_cnt) > 1) in pci_enable_device_flags()
1999 if (dev->resource[i].flags & flags) in pci_enable_device_flags()
2002 if (dev->resource[i].flags & flags) in pci_enable_device_flags()
2007 atomic_dec(&dev->enable_cnt); in pci_enable_device_flags()
2012 * pci_enable_device_io - Initialize a device for use with IO space
2015 * Initialize device before it's used by a driver. Ask low-level code
2026 * pci_enable_device_mem - Initialize a device for use with Memory space
2029 * Initialize device before it's used by a driver. Ask low-level code
2040 * pci_enable_device - Initialize device before it's used by a driver.
2043 * Initialize device before it's used by a driver. Ask low-level code
2057 * Managed PCI resources. This manages device on/off, INTx/MSI/MSI-X
2058 * on/off and BAR regions. pci_dev itself records MSI/MSI-X status, so
2078 if (this->region_mask & (1 << i)) in pcim_release()
2081 if (this->mwi) in pcim_release()
2084 if (this->restore_intx) in pcim_release()
2085 pci_intx(dev, this->orig_intx); in pcim_release()
2087 if (this->enabled && !this->pinned) in pcim_release()
2095 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL); in get_pci_dr()
2102 return devres_get(&pdev->dev, new_dr, NULL, NULL); in get_pci_dr()
2108 return devres_find(&pdev->dev, pcim_release, NULL, NULL); in find_pci_dr()
2113 * pcim_enable_device - Managed pci_enable_device()
2125 return -ENOMEM; in pcim_enable_device()
2126 if (dr->enabled) in pcim_enable_device()
2131 pdev->is_managed = 1; in pcim_enable_device()
2132 dr->enabled = 1; in pcim_enable_device()
2139 * pcim_pin_device - Pin managed PCI device
2151 WARN_ON(!dr || !dr->enabled); in pcim_pin_device()
2153 dr->pinned = 1; in pcim_pin_device()
2158 * pcibios_device_add - provide arch specific hooks when adding device dev
2171 * pcibios_release_device - provide arch specific hooks when releasing
2182 * pcibios_disable_device - disable arch specific PCI resources for device dev
2192 * pcibios_penalize_isa_irq - penalize an ISA IRQ
2196 * Permits the platform to provide architecture-specific functionality when
2216 * pci_disable_enabled_device - Disable device without updating enable_cnt
2229 * pci_disable_device - Disable PCI device after use
2233 * anymore. This only involves disabling PCI bus-mastering, if active.
2244 dr->enabled = 0; in pci_disable_device()
2246 dev_WARN_ONCE(&dev->dev, atomic_read(&dev->enable_cnt) <= 0, in pci_disable_device()
2247 "disabling already-disabled device"); in pci_disable_device()
2249 if (atomic_dec_return(&dev->enable_cnt) != 0) in pci_disable_device()
2254 dev->is_busmaster = 0; in pci_disable_device()
2259 * pcibios_set_pcie_reset_state - set reset state for device dev
2269 return -EINVAL; in pcibios_set_pcie_reset_state()
2273 * pci_set_pcie_reset_state - set reset state for device dev
2296 * pcie_clear_root_pme_status - Clear root port PME interrupt status.
2305 * pci_check_pme_status - Check if given device has generated PME.
2318 if (!dev->pm_cap) in pci_check_pme_status()
2321 pmcsr_pos = dev->pm_cap + PCI_PM_CTRL; in pci_check_pme_status()
2340 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
2349 if (pme_poll_reset && dev->pme_poll) in pci_pme_wakeup()
2350 dev->pme_poll = false; in pci_pme_wakeup()
2354 pm_request_resume(&dev->dev); in pci_pme_wakeup()
2360 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
2371 * pci_pme_capable - check the capability of PCI device to generate PME#
2377 if (!dev->pm_cap) in pci_pme_capable()
2380 return !!(dev->pme_support & (1 << state)); in pci_pme_capable()
2390 if (pme_dev->dev->pme_poll) { in pci_pme_list_scan()
2393 bridge = pme_dev->dev->bus->self; in pci_pme_list_scan()
2399 if (bridge && bridge->current_state != PCI_D0) in pci_pme_list_scan()
2405 if (pme_dev->dev->current_state == PCI_D3cold) in pci_pme_list_scan()
2408 pci_pme_wakeup(pme_dev->dev, NULL); in pci_pme_list_scan()
2410 list_del(&pme_dev->list); in pci_pme_list_scan()
2424 if (!dev->pme_support) in __pci_pme_active()
2427 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); in __pci_pme_active()
2433 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); in __pci_pme_active()
2437 * pci_pme_restore - Restore PME configuration after config space restore.
2444 if (!dev->pme_support) in pci_pme_restore()
2447 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); in pci_pme_restore()
2448 if (dev->wakeup_prepared) { in pci_pme_restore()
2455 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); in pci_pme_restore()
2459 * pci_pme_active - enable or disable PCI device's PME# function
2481 * Although PCIe uses in-band PME message instead of PME# line in pci_pme_active()
2490 if (dev->pme_poll) { in pci_pme_active()
2499 pme_dev->dev = dev; in pci_pme_active()
2501 list_add(&pme_dev->list, &pci_pme_list); in pci_pme_active()
2510 if (pme_dev->dev == dev) { in pci_pme_active()
2511 list_del(&pme_dev->list); in pci_pme_active()
2525 * __pci_enable_wake - enable PCI device as wakeup event source
2531 * When such events involves platform-specific hooks, those hooks are
2539 * -EINVAL is returned if device is not supposed to wake up the system
2541 * the native mechanism fail to enable the generation of wake-up events
2548 * Bridges that are not power-manageable directly only signal in __pci_enable_wake()
2551 * power-manageable may signal wakeup for themselves (for example, in __pci_enable_wake()
2558 if (!!enable == !!dev->wakeup_prepared) in __pci_enable_wake()
2564 * enable. To disable wake-up we call the platform first, for symmetry. in __pci_enable_wake()
2585 dev->wakeup_prepared = true; in __pci_enable_wake()
2589 dev->wakeup_prepared = false; in __pci_enable_wake()
2596 * pci_enable_wake - change wakeup settings for a PCI device
2606 if (enable && !device_may_wakeup(&pci_dev->dev)) in pci_enable_wake()
2607 return -EINVAL; in pci_enable_wake()
2614 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
2616 * @enable: True to enable wake-up event generation; false to disable
2619 * and this function allows them to set that up cleanly - pci_enable_wake()
2620 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
2625 * D3_hot and D3_cold and the platform is unable to enable wake-up power for it.
2636 * pci_target_state - find an appropriate low power state for a given PCI dev
2667 * If the device is in D3cold even though it's not power-manageable by in pci_target_state()
2668 * the platform, it may have been powered down by non-standard means. in pci_target_state()
2671 if (dev->current_state == PCI_D3cold) in pci_target_state()
2673 else if (!dev->pm_cap) in pci_target_state()
2676 if (wakeup && dev->pme_support) { in pci_target_state()
2683 while (state && !(dev->pme_support & (1 << state))) in pci_target_state()
2684 state--; in pci_target_state()
2688 else if (dev->pme_support & 1) in pci_target_state()
2696 * pci_prepare_to_sleep - prepare PCI device for system-wide transition
2706 bool wakeup = device_may_wakeup(&dev->dev); in pci_prepare_to_sleep()
2711 return -EIO; in pci_prepare_to_sleep()
2725 * pci_back_from_sleep - turn PCI device on during system-wide transition
2729 * Disable device's system wake-up capability and put it into D0.
2744 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
2747 * Prepare @dev to generate wake-up events at run time and put it into a low
2755 target_state = pci_target_state(dev, device_can_wakeup(&dev->dev)); in pci_finish_runtime_suspend()
2757 return -EIO; in pci_finish_runtime_suspend()
2770 * pci_dev_run_wake - Check if device can generate run-time wake-up events.
2773 * Return true if the device itself is capable of generating wake-up events
2775 * PME and one of its upstream bridges can generate wake-up events.
2779 struct pci_bus *bus = dev->bus; in pci_dev_run_wake()
2781 if (!dev->pme_support) in pci_dev_run_wake()
2784 /* PME-capable in principle, but not from the target power state */ in pci_dev_run_wake()
2788 if (device_can_wakeup(&dev->dev)) in pci_dev_run_wake()
2791 while (bus->parent) { in pci_dev_run_wake()
2792 struct pci_dev *bridge = bus->self; in pci_dev_run_wake()
2794 if (device_can_wakeup(&bridge->dev)) in pci_dev_run_wake()
2797 bus = bus->parent; in pci_dev_run_wake()
2801 if (bus->bridge) in pci_dev_run_wake()
2802 return device_can_wakeup(bus->bridge); in pci_dev_run_wake()
2809 * pci_dev_need_resume - Check if it is necessary to resume the device.
2812 * Return 'true' if the device is not runtime-suspended or it has to be
2815 * (system-wide) transition.
2819 struct device *dev = &pci_dev->dev; in pci_dev_need_resume()
2832 return target_state != pci_dev->current_state && in pci_dev_need_resume()
2834 pci_dev->current_state != PCI_D3hot; in pci_dev_need_resume()
2838 * pci_dev_adjust_pme - Adjust PME setting for a suspended device.
2850 struct device *dev = &pci_dev->dev; in pci_dev_adjust_pme()
2852 spin_lock_irq(&dev->power.lock); in pci_dev_adjust_pme()
2855 pci_dev->current_state < PCI_D3cold) in pci_dev_adjust_pme()
2858 spin_unlock_irq(&dev->power.lock); in pci_dev_adjust_pme()
2862 * pci_dev_complete_resume - Finalize resume from system sleep for a device.
2865 * If the device is runtime suspended and wakeup-capable, enable PME for it as
2871 struct device *dev = &pci_dev->dev; in pci_dev_complete_resume()
2876 spin_lock_irq(&dev->power.lock); in pci_dev_complete_resume()
2878 if (pm_runtime_suspended(dev) && pci_dev->current_state < PCI_D3cold) in pci_dev_complete_resume()
2881 spin_unlock_irq(&dev->power.lock); in pci_dev_complete_resume()
2885 * pci_choose_state - Choose the power state of a PCI device.
2902 struct device *dev = &pdev->dev; in pci_config_pm_runtime_get()
2903 struct device *parent = dev->parent; in pci_config_pm_runtime_get()
2909 * pdev->current_state is set to PCI_D3cold during suspending, in pci_config_pm_runtime_get()
2918 if (pdev->current_state == PCI_D3cold) in pci_config_pm_runtime_get()
2924 struct device *dev = &pdev->dev; in pci_config_pm_runtime_put()
2925 struct device *parent = dev->parent; in pci_config_pm_runtime_put()
2941 .ident = "X299 DESIGNARE EX-CF",
2944 DMI_MATCH(DMI_BOARD_NAME, "X299 DESIGNARE EX-CF"),
2964 * pci_bridge_d3_possible - Is it possible to put the bridge into D3
2984 * may not be put into D3 by the OS (Thunderbolt on non-Macs). in pci_bridge_d3_possible()
2986 if (bridge->is_hotplug_bridge && !pciehp_is_native(bridge)) in pci_bridge_d3_possible()
2993 if (bridge->is_thunderbolt) in pci_bridge_d3_possible()
3005 if (bridge->is_hotplug_bridge) in pci_bridge_d3_possible()
3028 dev->no_d3cold || !dev->d3cold_allowed || in pci_dev_check_d3cold()
3031 (device_may_wakeup(&dev->dev) && in pci_dev_check_d3cold()
3043 * pci_bridge_d3_update - Update bridge D3 capabilities
3052 bool remove = !device_is_registered(&dev->dev); in pci_bridge_d3_update()
3064 if (remove && bridge->bridge_d3) in pci_bridge_d3_update()
3084 if (d3cold_ok && !bridge->bridge_d3) in pci_bridge_d3_update()
3085 pci_walk_bus(bridge->subordinate, pci_dev_check_d3cold, in pci_bridge_d3_update()
3088 if (bridge->bridge_d3 != d3cold_ok) { in pci_bridge_d3_update()
3089 bridge->bridge_d3 = d3cold_ok; in pci_bridge_d3_update()
3096 * pci_d3cold_enable - Enable D3cold for device
3105 if (dev->no_d3cold) { in pci_d3cold_enable()
3106 dev->no_d3cold = false; in pci_d3cold_enable()
3113 * pci_d3cold_disable - Disable D3cold for device
3122 if (!dev->no_d3cold) { in pci_d3cold_disable()
3123 dev->no_d3cold = true; in pci_d3cold_disable()
3130 * pci_pm_init - Initialize PM functions of given PCI device
3139 pm_runtime_forbid(&dev->dev); in pci_pm_init()
3140 pm_runtime_set_active(&dev->dev); in pci_pm_init()
3141 pm_runtime_enable(&dev->dev); in pci_pm_init()
3142 device_enable_async_suspend(&dev->dev); in pci_pm_init()
3143 dev->wakeup_prepared = false; in pci_pm_init()
3145 dev->pm_cap = 0; in pci_pm_init()
3146 dev->pme_support = 0; in pci_pm_init()
3161 dev->pm_cap = pm; in pci_pm_init()
3162 dev->d3hot_delay = PCI_PM_D3HOT_WAIT; in pci_pm_init()
3163 dev->d3cold_delay = PCI_PM_D3COLD_WAIT; in pci_pm_init()
3164 dev->bridge_d3 = pci_bridge_d3_possible(dev); in pci_pm_init()
3165 dev->d3cold_allowed = true; in pci_pm_init()
3167 dev->d1_support = false; in pci_pm_init()
3168 dev->d2_support = false; in pci_pm_init()
3171 dev->d1_support = true; in pci_pm_init()
3173 dev->d2_support = true; in pci_pm_init()
3175 if (dev->d1_support || dev->d2_support) in pci_pm_init()
3177 dev->d1_support ? " D1" : "", in pci_pm_init()
3178 dev->d2_support ? " D2" : ""); in pci_pm_init()
3189 dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT; in pci_pm_init()
3190 dev->pme_poll = true; in pci_pm_init()
3192 * Make device's PM flags reflect the wake-up capability, but in pci_pm_init()
3195 device_set_wakeup_capable(&dev->dev, true); in pci_pm_init()
3202 dev->imm_ready = 1; in pci_pm_init()
3232 return &dev->resource[bei]; in pci_ea_get_resource()
3236 return &dev->resource[PCI_IOV_RESOURCES + in pci_ea_get_resource()
3237 bei - PCI_EA_BEI_VF_BAR0]; in pci_ea_get_resource()
3240 return &dev->resource[PCI_ROM_RESOURCE]; in pci_ea_get_resource()
3298 /* Read Base MSBs (if 64-bit entry) */ in pci_ea_read()
3307 /* entry starts above 32-bit boundary, can't use */ in pci_ea_read()
3317 /* Read MaxOffset MSBs (if 64-bit entry) */ in pci_ea_read()
3339 if (ent_size != ent_offset - offset) { in pci_ea_read()
3341 ent_size, ent_offset - offset); in pci_ea_read()
3345 res->name = pci_name(dev); in pci_ea_read()
3346 res->start = start; in pci_ea_read()
3347 res->end = end; in pci_ea_read()
3348 res->flags = flags; in pci_ea_read()
3358 bei - PCI_EA_BEI_VF_BAR0, res, prop); in pci_ea_read()
3381 pci_bus_read_config_byte(dev->bus, dev->devfn, ea + PCI_EA_NUM_ENT, in pci_ea_init()
3388 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) in pci_ea_init()
3399 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space); in pci_add_saved_cap()
3403 * _pci_add_cap_save_buffer - allocate buffer for saving given
3426 return -ENOMEM; in _pci_add_cap_save_buffer()
3428 save_state->cap.cap_nr = cap; in _pci_add_cap_save_buffer()
3429 save_state->cap.cap_extended = extended; in _pci_add_cap_save_buffer()
3430 save_state->cap.size = size; in _pci_add_cap_save_buffer()
3447 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
3461 pci_err(dev, "unable to preallocate PCI-X save buffer\n"); in pci_allocate_cap_save_buffers()
3471 pci_err(dev, "unable to allocate suspend buffer for ASPM-L1SS\n"); in pci_allocate_cap_save_buffers()
3481 hlist_for_each_entry_safe(tmp, n, &dev->saved_cap_space, next) in pci_free_cap_save_buffers()
3486 * pci_configure_ari - enable or disable ARI forwarding
3497 if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn) in pci_configure_ari()
3500 bridge = dev->bus->self; in pci_configure_ari()
3511 bridge->ari_enabled = 1; in pci_configure_ari()
3515 bridge->ari_enabled = 0; in pci_configure_ari()
3524 pos = pdev->acs_cap; in pci_acs_flags_enabled()
3531 * capability field can therefore be assumed as hard-wired enabled. in pci_acs_flags_enabled()
3541 * pci_acs_enabled - test ACS against required flags for a given device
3551 * opportunity for peer-to-peer access. We therefore return 'true'
3565 * Conventional PCI and PCI-X devices never support ACS, either in pci_acs_enabled()
3574 * PCI/X-to-PCIe bridges are not specifically mentioned by the spec, in pci_acs_enabled()
3576 * handle them as we would a non-PCIe device. in pci_acs_enabled()
3590 * implement ACS in order to indicate their peer-to-peer capabilities, in pci_acs_enabled()
3591 * regardless of whether they are single- or multi-function devices. in pci_acs_enabled()
3598 * implemented by the remaining PCIe types to indicate peer-to-peer in pci_acs_enabled()
3607 if (!pdev->multifunction) in pci_acs_enabled()
3621 * pci_acs_path_enabled - test ACS flags from start to end in a hierarchy
3640 if (pci_is_root_bus(pdev->bus)) in pci_acs_path_enabled()
3643 parent = pdev->bus->self; in pci_acs_path_enabled()
3650 * pci_acs_init - Initialize ACS if hardware supports it
3655 dev->acs_cap = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS); in pci_acs_init()
3667 * pci_rebar_find_pos - find position of resize ctrl reg for BAR
3672 * Returns -ENOTSUPP if resizable BARs are not supported at all.
3673 * Returns -ENOENT if no ctrl register for the BAR could be found.
3682 return -ENOTSUPP; in pci_rebar_find_pos()
3697 return -ENOENT; in pci_rebar_find_pos()
3701 * pci_rebar_get_possible_sizes - get possible sizes for BAR
3721 if (pdev->vendor == PCI_VENDOR_ID_ATI && pdev->device == 0x731f && in pci_rebar_get_possible_sizes()
3730 * pci_rebar_get_current_size - get the current size of a BAR
3751 * pci_rebar_set_size - set a new size for a BAR
3776 * pci_enable_atomic_ops_to_root - enable AtomicOp requests to root port
3785 * the requested completion capabilities (32-bit, 64-bit and/or 128-bit
3790 struct pci_bus *bus = dev->bus; in pci_enable_atomic_ops_to_root()
3799 if (dev->is_virtfn) in pci_enable_atomic_ops_to_root()
3800 return -EINVAL; in pci_enable_atomic_ops_to_root()
3803 return -EINVAL; in pci_enable_atomic_ops_to_root()
3809 * completers, and no peer-to-peer. in pci_enable_atomic_ops_to_root()
3818 return -EINVAL; in pci_enable_atomic_ops_to_root()
3821 while (bus->parent) { in pci_enable_atomic_ops_to_root()
3822 bridge = bus->self; in pci_enable_atomic_ops_to_root()
3831 return -EINVAL; in pci_enable_atomic_ops_to_root()
3837 return -EINVAL; in pci_enable_atomic_ops_to_root()
3846 return -EINVAL; in pci_enable_atomic_ops_to_root()
3849 bus = bus->parent; in pci_enable_atomic_ops_to_root()
3859 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
3864 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
3865 * behind bridges on add-in cards. For devices with ARI enabled, the slot
3873 if (pci_ari_enabled(dev->bus)) in pci_swizzle_interrupt_pin()
3876 slot = PCI_SLOT(dev->devfn); in pci_swizzle_interrupt_pin()
3878 return (((pin - 1) + slot) % 4) + 1; in pci_swizzle_interrupt_pin()
3885 pin = dev->pin; in pci_get_interrupt_pin()
3887 return -1; in pci_get_interrupt_pin()
3889 while (!pci_is_root_bus(dev->bus)) { in pci_get_interrupt_pin()
3891 dev = dev->bus->self; in pci_get_interrupt_pin()
3898 * pci_common_swizzle - swizzle INTx all the way to root bridge
3902 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
3909 while (!pci_is_root_bus(dev->bus)) { in pci_common_swizzle()
3911 dev = dev->bus->self; in pci_common_swizzle()
3914 return PCI_SLOT(dev->devfn); in pci_common_swizzle()
3919 * pci_release_region - Release a PCI bar
3943 dr->region_mask &= ~(1 << bar); in pci_release_region()
3948 * __pci_request_region - Reserved PCI I/O and memory resource
3987 dr->region_mask |= 1 << bar; in __pci_request_region()
3993 &pdev->resource[bar]); in __pci_request_region()
3994 return -EBUSY; in __pci_request_region()
3998 * pci_request_region - Reserve PCI I/O and memory resource
4018 * pci_release_selected_regions - Release selected PCI I/O and memory resources
4047 while (--i >= 0) in __pci_request_selected_regions()
4051 return -EBUSY; in __pci_request_selected_regions()
4056 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
4077 * pci_release_regions - Release reserved PCI I/O and memory resources
4088 pci_release_selected_regions(pdev, (1 << PCI_STD_NUM_BARS) - 1); in pci_release_regions()
4093 * pci_request_regions - Reserve PCI I/O and memory resources
4108 ((1 << PCI_STD_NUM_BARS) - 1), res_name); in pci_request_regions()
4113 * pci_request_regions_exclusive - Reserve PCI I/O and memory resources
4130 ((1 << PCI_STD_NUM_BARS) - 1), res_name); in pci_request_regions_exclusive()
4146 return -EINVAL; in pci_register_io_range()
4150 return -ENOMEM; in pci_register_io_range()
4152 range->fwnode = fwnode; in pci_register_io_range()
4153 range->size = size; in pci_register_io_range()
4154 range->hw_start = addr; in pci_register_io_range()
4155 range->flags = LOGIC_PIO_CPU_MMIO; in pci_register_io_range()
4162 if (ret == -EEXIST) in pci_register_io_range()
4190 return (unsigned long)-1; in pci_address_to_pio()
4197 * pci_remap_iospace - Remap the memory mapped I/O space
4210 unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start; in pci_remap_iospace()
4212 if (!(res->flags & IORESOURCE_IO)) in pci_remap_iospace()
4213 return -EINVAL; in pci_remap_iospace()
4215 if (res->end > IO_SPACE_LIMIT) in pci_remap_iospace()
4216 return -EINVAL; in pci_remap_iospace()
4226 return -ENODEV; in pci_remap_iospace()
4233 * pci_unmap_iospace - Unmap the memory mapped I/O space
4243 unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start; in pci_unmap_iospace()
4258 * devm_pci_remap_iospace - Managed pci_remap_iospace()
4274 return -ENOMEM; in devm_pci_remap_iospace()
4289 * devm_pci_remap_cfgspace - Managed pci_remap_cfgspace()
4319 * devm_pci_remap_cfg_resource - check, request region and ioremap cfg resource
4333 * base = devm_pci_remap_cfg_resource(&pdev->dev, res);
4348 return IOMEM_ERR_PTR(-EINVAL); in devm_pci_remap_cfg_resource()
4353 if (res->name) in devm_pci_remap_cfg_resource()
4355 res->name); in devm_pci_remap_cfg_resource()
4359 return IOMEM_ERR_PTR(-ENOMEM); in devm_pci_remap_cfg_resource()
4361 if (!devm_request_mem_region(dev, res->start, size, name)) { in devm_pci_remap_cfg_resource()
4363 return IOMEM_ERR_PTR(-EBUSY); in devm_pci_remap_cfg_resource()
4366 dest_ptr = devm_pci_remap_cfgspace(dev, res->start, size); in devm_pci_remap_cfg_resource()
4369 devm_release_mem_region(dev, res->start, size); in devm_pci_remap_cfg_resource()
4370 dest_ptr = IOMEM_ERR_PTR(-ENOMEM); in devm_pci_remap_cfg_resource()
4391 dev->is_busmaster = enable; in __pci_set_master()
4395 * pcibios_setup - process "pci=" kernel boot arguments
4407 * pcibios_set_master - enable PCI bus-mastering for device dev
4410 * Enables PCI bus-mastering for the device. This is the default
4434 * pci_set_master - enables bus-mastering for device dev
4437 * Enables bus-mastering on the device and calls pcibios_set_master()
4448 * pci_clear_master - disables bus-mastering for device dev
4458 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
4463 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
4465 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4472 return -EINVAL; in pci_set_cacheline_size()
4491 return -EINVAL; in pci_set_cacheline_size()
4496 * pci_set_mwi - enables memory-write-invalidate PCI transaction
4499 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
4501 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4517 pci_dbg(dev, "enabling Mem-Wr-Inval\n"); in pci_set_mwi()
4527 * pcim_set_mwi - a device-managed pci_set_mwi()
4532 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4540 return -ENOMEM; in pcim_set_mwi()
4542 dr->mwi = 1; in pcim_set_mwi()
4548 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
4551 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
4554 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4567 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
4570 * Disables PCI Memory-Write-Invalidate transaction on the device
4587 * pci_disable_parity - disable parity checking for device
4604 * pci_intx - enables/disables PCI INTx for device dev
4627 if (dr && !dr->restore_intx) { in pci_intx()
4628 dr->restore_intx = 1; in pci_intx()
4629 dr->orig_intx = !enable; in pci_intx()
4637 struct pci_bus *bus = dev->bus; in pci_check_and_set_intx_mask()
4653 bus->ops->read(bus, dev->devfn, PCI_COMMAND, 4, &cmd_status_dword); in pci_check_and_set_intx_mask()
4672 bus->ops->write(bus, dev->devfn, PCI_COMMAND, 2, newcmd); in pci_check_and_set_intx_mask()
4681 * pci_check_and_mask_intx - mask INTx on pending interrupt
4694 * pci_check_and_unmask_intx - unmask INTx if no interrupt is pending
4708 * pci_wait_for_pending_transaction - wait for pending transaction
4724 * pcie_flr - initiate a PCIe function level reset
4737 if (dev->imm_ready) in pcie_flr()
4742 * 100ms, but may silently discard requests while the FLR is in in pcie_flr()
4743 * progress. Wait 100ms before trying to access the device. in pcie_flr()
4752 * pcie_reset_flr - initiate a PCIe function level reset
4760 if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET) in pcie_reset_flr()
4761 return -ENOTTY; in pcie_reset_flr()
4763 if (!(dev->devcap & PCI_EXP_DEVCAP_FLR)) in pcie_reset_flr()
4764 return -ENOTTY; in pcie_reset_flr()
4780 return -ENOTTY; in pci_af_flr()
4782 if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET) in pci_af_flr()
4783 return -ENOTTY; in pci_af_flr()
4787 return -ENOTTY; in pci_af_flr()
4793 * Wait for Transaction Pending bit to clear. A word-aligned test in pci_af_flr()
4803 if (dev->imm_ready) in pci_af_flr()
4809 * 100ms, but may silently discard requests while the FLR is in in pci_af_flr()
4810 * progress. Wait 100ms before trying to access the device. in pci_af_flr()
4818 * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0.
4824 * PCI_D0. If that's the case and the device is not in a low-power state
4828 * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms
4836 if (!dev->pm_cap || dev->dev_flags & PCI_DEV_FLAGS_NO_PM_RESET) in pci_pm_reset()
4837 return -ENOTTY; in pci_pm_reset()
4839 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr); in pci_pm_reset()
4841 return -ENOTTY; in pci_pm_reset()
4846 if (dev->current_state != PCI_D0) in pci_pm_reset()
4847 return -EINVAL; in pci_pm_reset()
4851 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); in pci_pm_reset()
4856 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); in pci_pm_reset()
4859 return pci_dev_wait(dev, "PM D3hot->D0", PCIE_RESET_READY_POLL_MS); in pci_pm_reset()
4863 * pcie_wait_for_link_delay - Wait until link is active or inactive
4865 * @active: waiting for active or inactive?
4866 * @delay: Delay to wait after link has become active (in ms)
4868 * Use this to wait till link becomes active or inactive.
4871 int delay) in pcie_wait_for_link_delay() argument
4879 * case, we wait for 1000 ms + any delay requested by the caller. in pcie_wait_for_link_delay()
4881 if (!pdev->link_active_reporting) { in pcie_wait_for_link_delay()
4882 msleep(timeout + delay); in pcie_wait_for_link_delay()
4887 * PCIe r4.0 sec 6.6.1, a component must enter LTSSM Detect within 20ms, in pcie_wait_for_link_delay()
4889 * successful. If so, software must wait a minimum 100ms before sending in pcie_wait_for_link_delay()
4905 timeout -= 10; in pcie_wait_for_link_delay()
4908 msleep(delay); in pcie_wait_for_link_delay()
4914 * pcie_wait_for_link - Wait until link is active or inactive
4916 * @active: waiting for active or inactive?
4918 * Use this to wait till link becomes active or inactive.
4926 * Find maximum D3cold delay required by all the devices on the bus. The
4927 * spec says 100 ms, but firmware can lower it and we allow drivers to
4938 list_for_each_entry(pdev, &bus->devices, bus_list) { in pci_bus_max_d3cold_delay()
4939 if (pdev->d3cold_delay < min_delay) in pci_bus_max_d3cold_delay()
4940 min_delay = pdev->d3cold_delay; in pci_bus_max_d3cold_delay()
4941 if (pdev->d3cold_delay > max_delay) in pci_bus_max_d3cold_delay()
4942 max_delay = pdev->d3cold_delay; in pci_bus_max_d3cold_delay()
4949 * pci_bridge_wait_for_secondary_bus - Wait for secondary bus to be accessible
4962 int delay; in pci_bridge_wait_for_secondary_bus() local
4967 if (!pci_is_bridge(dev) || !dev->bridge_d3) in pci_bridge_wait_for_secondary_bus()
4974 * For any hot-added devices the access delay is handled in pciehp in pci_bridge_wait_for_secondary_bus()
4978 if (!dev->subordinate || list_empty(&dev->subordinate->devices)) { in pci_bridge_wait_for_secondary_bus()
4984 delay = pci_bus_max_d3cold_delay(dev->subordinate); in pci_bridge_wait_for_secondary_bus()
4985 if (!delay) { in pci_bridge_wait_for_secondary_bus()
4990 child = list_first_entry(&dev->subordinate->devices, struct pci_dev, in pci_bridge_wait_for_secondary_bus()
4995 * Conventional PCI and PCI-X we need to wait Tpvrh + Trhfa before in pci_bridge_wait_for_secondary_bus()
4996 * accessing the device after reset (that is 1000 ms + 100 ms). In in pci_bridge_wait_for_secondary_bus()
5001 pci_dbg(dev, "waiting %d ms for secondary bus\n", 1000 + delay); in pci_bridge_wait_for_secondary_bus()
5002 msleep(1000 + delay); in pci_bridge_wait_for_secondary_bus()
5008 * greater than 5 GT/s need to wait minimum 100 ms. For higher in pci_bridge_wait_for_secondary_bus()
5012 * However, 100 ms is the minimum and the PCIe spec says the in pci_bridge_wait_for_secondary_bus()
5015 * evidence that 100 ms is not always enough, for example certain in pci_bridge_wait_for_secondary_bus()
5017 * configuration requests if we only wait for 100 ms (see in pci_bridge_wait_for_secondary_bus()
5020 * Therefore we wait for 100 ms and check for the device presence. in pci_bridge_wait_for_secondary_bus()
5021 * If it is still not present give it an additional 100 ms. in pci_bridge_wait_for_secondary_bus()
5027 pci_dbg(dev, "waiting %d ms for downstream link\n", delay); in pci_bridge_wait_for_secondary_bus()
5028 msleep(delay); in pci_bridge_wait_for_secondary_bus()
5030 pci_dbg(dev, "waiting %d ms for downstream link, after activation\n", in pci_bridge_wait_for_secondary_bus()
5031 delay); in pci_bridge_wait_for_secondary_bus()
5032 if (!pcie_wait_for_link_delay(dev, true, delay)) { in pci_bridge_wait_for_secondary_bus()
5040 pci_dbg(child, "waiting additional %d ms to become accessible\n", delay); in pci_bridge_wait_for_secondary_bus()
5041 msleep(delay); in pci_bridge_wait_for_secondary_bus()
5054 * PCI spec v3.0 7.6.4.2 requires minimum Trst of 1ms. Double in pci_reset_secondary_bus()
5055 * this to 2ms to ensure that we meet the minimum requirement. in pci_reset_secondary_bus()
5065 * delay before we can consider subordinate devices to in pci_reset_secondary_bus()
5066 * be re-initialized. PCIe has some ways to shorten this, in pci_reset_secondary_bus()
5078 * pci_bridge_secondary_bus_reset - Reset the secondary bus on a PCI bridge.
5082 * Devices on the secondary bus are left in power-on state.
5096 if (pci_is_root_bus(dev->bus) || dev->subordinate || in pci_parent_bus_reset()
5097 !dev->bus->self || dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET) in pci_parent_bus_reset()
5098 return -ENOTTY; in pci_parent_bus_reset()
5100 list_for_each_entry(pdev, &dev->bus->devices, bus_list) in pci_parent_bus_reset()
5102 return -ENOTTY; in pci_parent_bus_reset()
5107 return pci_bridge_secondary_bus_reset(dev->bus->self); in pci_parent_bus_reset()
5112 int rc = -ENOTTY; in pci_reset_hotplug_slot()
5114 if (!hotplug || !try_module_get(hotplug->owner)) in pci_reset_hotplug_slot()
5117 if (hotplug->ops->reset_slot) in pci_reset_hotplug_slot()
5118 rc = hotplug->ops->reset_slot(hotplug, probe); in pci_reset_hotplug_slot()
5120 module_put(hotplug->owner); in pci_reset_hotplug_slot()
5127 if (dev->multifunction || dev->subordinate || !dev->slot || in pci_dev_reset_slot_function()
5128 dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET) in pci_dev_reset_slot_function()
5129 return -ENOTTY; in pci_dev_reset_slot_function()
5131 return pci_reset_hotplug_slot(dev->slot->hotplug, probe); in pci_dev_reset_slot_function()
5139 if (rc != -ENOTTY) in pci_reset_bus_function()
5147 device_lock(&dev->dev); in pci_dev_lock()
5155 if (device_trylock(&dev->dev)) { in pci_dev_trylock()
5158 device_unlock(&dev->dev); in pci_dev_trylock()
5168 device_unlock(&dev->dev); in pci_dev_unlock()
5175 dev->driver ? dev->driver->err_handler : NULL; in pci_dev_save_and_disable()
5178 * dev->driver->err_handler->reset_prepare() is protected against in pci_dev_save_and_disable()
5179 * races with ->remove() by the device lock, which must be held by in pci_dev_save_and_disable()
5182 if (err_handler && err_handler->reset_prepare) in pci_dev_save_and_disable()
5183 err_handler->reset_prepare(dev); in pci_dev_save_and_disable()
5186 * Wake-up device prior to save. PM registers default to D0 after in pci_dev_save_and_disable()
5188 * to a non-D0 state anyway. in pci_dev_save_and_disable()
5195 * INTx-disable which is set. This not only disables MMIO and I/O port in pci_dev_save_and_disable()
5197 * DMA from the device including MSI/MSI-X interrupts. For PCI 2.3 in pci_dev_save_and_disable()
5198 * compliant devices, INTx-disable prevents legacy interrupts. in pci_dev_save_and_disable()
5206 dev->driver ? dev->driver->err_handler : NULL; in pci_dev_restore()
5211 * dev->driver->err_handler->reset_done() is protected against in pci_dev_restore()
5212 * races with ->remove() by the device lock, which must be held by in pci_dev_restore()
5215 if (err_handler && err_handler->reset_done) in pci_dev_restore()
5216 err_handler->reset_done(dev); in pci_dev_restore()
5219 /* dev->reset_methods[] is a 0-terminated list of indices into this array */
5238 m = pdev->reset_methods[i]; in reset_method_show()
5274 pdev->reset_methods[0] = 0; in reset_method_store()
5286 return -ENOMEM; in reset_method_store()
5306 if (n == PCI_NUM_RESET_METHODS - 1) { in reset_method_store()
5316 /* Warn if dev-specific supported but not highest priority */ in reset_method_store()
5319 pci_warn(pdev, "Device-specific reset disabled/de-prioritized by user"); in reset_method_store()
5320 memcpy(pdev->reset_methods, reset_methods, sizeof(pdev->reset_methods)); in reset_method_store()
5327 return -EINVAL; in reset_method_store()
5344 return a->mode; in pci_dev_reset_method_attr_is_visible()
5353 * __pci_reset_function_locked - reset a PCI device function while holding
5379 * A reset method returns -ENOTTY if it doesn't support this device and in __pci_reset_function_locked()
5387 m = dev->reset_methods[i]; in __pci_reset_function_locked()
5389 return -ENOTTY; in __pci_reset_function_locked()
5394 if (rc != -ENOTTY) in __pci_reset_function_locked()
5398 return -ENOTTY; in __pci_reset_function_locked()
5403 * pci_init_reset_methods - check whether device can be safely reset
5408 * other functions in the same device. The PCI device must be in D0-D3hot
5426 dev->reset_methods[i++] = m; in pci_init_reset_methods()
5427 else if (rc != -ENOTTY) in pci_init_reset_methods()
5431 dev->reset_methods[i] = 0; in pci_init_reset_methods()
5435 * pci_reset_function - quiesce and reset a PCI device function
5455 return -ENOTTY; in pci_reset_function()
5470 * pci_reset_function_locked - quiesce and reset a PCI device function
5491 return -ENOTTY; in pci_reset_function_locked()
5504 * pci_try_reset_function - quiesce and reset a PCI device function
5507 * Same as above, except return -EAGAIN if unable to lock device.
5514 return -ENOTTY; in pci_try_reset_function()
5517 return -EAGAIN; in pci_try_reset_function()
5534 if (bus->self && (bus->self->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)) in pci_bus_resetable()
5537 list_for_each_entry(dev, &bus->devices, bus_list) { in pci_bus_resetable()
5538 if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET || in pci_bus_resetable()
5539 (dev->subordinate && !pci_bus_resetable(dev->subordinate))) in pci_bus_resetable()
5551 list_for_each_entry(dev, &bus->devices, bus_list) { in pci_bus_lock()
5553 if (dev->subordinate) in pci_bus_lock()
5554 pci_bus_lock(dev->subordinate); in pci_bus_lock()
5563 list_for_each_entry(dev, &bus->devices, bus_list) { in pci_bus_unlock()
5564 if (dev->subordinate) in pci_bus_unlock()
5565 pci_bus_unlock(dev->subordinate); in pci_bus_unlock()
5575 list_for_each_entry(dev, &bus->devices, bus_list) { in pci_bus_trylock()
5578 if (dev->subordinate) { in pci_bus_trylock()
5579 if (!pci_bus_trylock(dev->subordinate)) { in pci_bus_trylock()
5588 list_for_each_entry_continue_reverse(dev, &bus->devices, bus_list) { in pci_bus_trylock()
5589 if (dev->subordinate) in pci_bus_trylock()
5590 pci_bus_unlock(dev->subordinate); in pci_bus_trylock()
5601 if (slot->bus->self && in pci_slot_resetable()
5602 (slot->bus->self->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)) in pci_slot_resetable()
5605 list_for_each_entry(dev, &slot->bus->devices, bus_list) { in pci_slot_resetable()
5606 if (!dev->slot || dev->slot != slot) in pci_slot_resetable()
5608 if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET || in pci_slot_resetable()
5609 (dev->subordinate && !pci_bus_resetable(dev->subordinate))) in pci_slot_resetable()
5621 list_for_each_entry(dev, &slot->bus->devices, bus_list) { in pci_slot_lock()
5622 if (!dev->slot || dev->slot != slot) in pci_slot_lock()
5625 if (dev->subordinate) in pci_slot_lock()
5626 pci_bus_lock(dev->subordinate); in pci_slot_lock()
5635 list_for_each_entry(dev, &slot->bus->devices, bus_list) { in pci_slot_unlock()
5636 if (!dev->slot || dev->slot != slot) in pci_slot_unlock()
5638 if (dev->subordinate) in pci_slot_unlock()
5639 pci_bus_unlock(dev->subordinate); in pci_slot_unlock()
5649 list_for_each_entry(dev, &slot->bus->devices, bus_list) { in pci_slot_trylock()
5650 if (!dev->slot || dev->slot != slot) in pci_slot_trylock()
5654 if (dev->subordinate) { in pci_slot_trylock()
5655 if (!pci_bus_trylock(dev->subordinate)) { in pci_slot_trylock()
5665 &slot->bus->devices, bus_list) { in pci_slot_trylock()
5666 if (!dev->slot || dev->slot != slot) in pci_slot_trylock()
5668 if (dev->subordinate) in pci_slot_trylock()
5669 pci_bus_unlock(dev->subordinate); in pci_slot_trylock()
5683 list_for_each_entry(dev, &bus->devices, bus_list) { in pci_bus_save_and_disable_locked()
5685 if (dev->subordinate) in pci_bus_save_and_disable_locked()
5686 pci_bus_save_and_disable_locked(dev->subordinate); in pci_bus_save_and_disable_locked()
5699 list_for_each_entry(dev, &bus->devices, bus_list) { in pci_bus_restore_locked()
5701 if (dev->subordinate) in pci_bus_restore_locked()
5702 pci_bus_restore_locked(dev->subordinate); in pci_bus_restore_locked()
5714 list_for_each_entry(dev, &slot->bus->devices, bus_list) { in pci_slot_save_and_disable_locked()
5715 if (!dev->slot || dev->slot != slot) in pci_slot_save_and_disable_locked()
5718 if (dev->subordinate) in pci_slot_save_and_disable_locked()
5719 pci_bus_save_and_disable_locked(dev->subordinate); in pci_slot_save_and_disable_locked()
5732 list_for_each_entry(dev, &slot->bus->devices, bus_list) { in pci_slot_restore_locked()
5733 if (!dev->slot || dev->slot != slot) in pci_slot_restore_locked()
5736 if (dev->subordinate) in pci_slot_restore_locked()
5737 pci_bus_restore_locked(dev->subordinate); in pci_slot_restore_locked()
5746 return -ENOTTY; in pci_slot_reset()
5753 rc = pci_reset_hotplug_slot(slot->hotplug, probe); in pci_slot_reset()
5762 * pci_probe_reset_slot - probe whether a PCI slot can be reset
5774 * __pci_reset_slot - Try to reset a PCI slot
5786 * Same as above except return -EAGAIN if the slot cannot be locked
5799 rc = pci_reset_hotplug_slot(slot->hotplug, PCI_RESET_DO_RESET); in __pci_reset_slot()
5803 rc = -EAGAIN; in __pci_reset_slot()
5812 if (!bus->self || !pci_bus_resetable(bus)) in pci_bus_reset()
5813 return -ENOTTY; in pci_bus_reset()
5822 ret = pci_bridge_secondary_bus_reset(bus->self); in pci_bus_reset()
5830 * pci_bus_error_reset - reset the bridge's subordinate bus
5839 struct pci_bus *bus = bridge->subordinate; in pci_bus_error_reset()
5843 return -ENOTTY; in pci_bus_error_reset()
5846 if (list_empty(&bus->slots)) in pci_bus_error_reset()
5849 list_for_each_entry(slot, &bus->slots, list) in pci_bus_error_reset()
5853 list_for_each_entry(slot, &bus->slots, list) in pci_bus_error_reset()
5861 return pci_bus_reset(bridge->subordinate, PCI_RESET_DO_RESET); in pci_bus_error_reset()
5865 * pci_probe_reset_bus - probe whether a PCI bus can be reset
5877 * __pci_reset_bus - Try to reset a PCI bus
5880 * Same as above except return -EAGAIN if the bus cannot be locked
5893 rc = pci_bridge_secondary_bus_reset(bus->self); in __pci_reset_bus()
5897 rc = -EAGAIN; in __pci_reset_bus()
5903 * pci_reset_bus - Try to reset a PCI bus
5906 * Same as above except return -EAGAIN if the bus cannot be locked
5910 return (!pci_probe_reset_slot(pdev->slot)) ? in pci_reset_bus()
5911 __pci_reset_slot(pdev->slot) : __pci_reset_bus(pdev->bus); in pci_reset_bus()
5916 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
5929 return -EINVAL; in pcix_get_max_mmrbc()
5932 return -EINVAL; in pcix_get_max_mmrbc()
5939 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
5952 return -EINVAL; in pcix_get_mmrbc()
5955 return -EINVAL; in pcix_get_mmrbc()
5962 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
5977 return -EINVAL; in pcix_set_mmrbc()
5979 v = ffs(mmrbc) - 10; in pcix_set_mmrbc()
5983 return -EINVAL; in pcix_set_mmrbc()
5986 return -EINVAL; in pcix_set_mmrbc()
5989 return -E2BIG; in pcix_set_mmrbc()
5992 return -EINVAL; in pcix_set_mmrbc()
5996 if (v > o && (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC)) in pcix_set_mmrbc()
5997 return -EIO; in pcix_set_mmrbc()
6002 return -EIO; in pcix_set_mmrbc()
6009 * pcie_get_readrq - get PCI Express read request size
6025 * pcie_set_readrq - set PCI Express maximum memory read request
6038 return -EINVAL; in pcie_set_readrq()
6052 v = (ffs(rq) - 8) << 12; in pcie_set_readrq()
6062 * pcie_get_mps - get PCI Express maximum payload size
6078 * pcie_set_mps - set PCI Express maximum payload size
6091 return -EINVAL; in pcie_set_mps()
6093 v = ffs(mps) - 8; in pcie_set_mps()
6094 if (v > dev->pcie_mpss) in pcie_set_mps()
6095 return -EINVAL; in pcie_set_mps()
6106 * pcie_bandwidth_available - determine minimum link settings of a PCIe
6164 * pcie_get_speed_cap - query for the PCI device's link speed capability
6185 /* PCIe r3.0-compliant */ in pcie_get_speed_cap()
6200 * pcie_get_width_cap - query for the PCI device's link width capability
6219 * pcie_bandwidth_capable - calculate a PCI device's link bandwidth capability
6241 * __pcie_print_link_status - Report the PCI device's link speed and width
6274 * pcie_print_link_status - Report the PCI device's link speed and width
6286 * pci_select_bars - Make BAR mask from the type of resource
6320 * pci_set_vga_state - set VGA decode state on device and parents if requested
6354 bus = dev->bus; in pci_set_vga_state()
6356 bridge = bus->self; in pci_set_vga_state()
6367 bus = bus->parent; in pci_set_vga_state()
6380 adev = ACPI_COMPANION(&pdev->dev); in pci_pr3_present()
6384 return adev->power.flags.power_resources && in pci_pr3_present()
6385 acpi_has_method(adev->handle, "_PR3"); in pci_pr3_present()
6391 * pci_add_dma_alias - Add a DMA devfn alias for a device
6396 * This helper encodes an 8-bit devfn as a bit number in dma_alias_mask
6397 * which is used to program permissible bus-devfn source addresses for DMA
6400 * from their logical bus-devfn. Examples include device quirks where the
6401 * device simply uses the wrong devfn, as well as non-transparent bridges
6415 nr_devfns = min(nr_devfns, (unsigned int)MAX_NR_DEVFNS - devfn_from); in pci_add_dma_alias()
6416 devfn_to = devfn_from + nr_devfns - 1; in pci_add_dma_alias()
6418 if (!dev->dma_alias_mask) in pci_add_dma_alias()
6419 dev->dma_alias_mask = bitmap_zalloc(MAX_NR_DEVFNS, GFP_KERNEL); in pci_add_dma_alias()
6420 if (!dev->dma_alias_mask) { in pci_add_dma_alias()
6425 bitmap_set(dev->dma_alias_mask, devfn_from, nr_devfns); in pci_add_dma_alias()
6438 return (dev1->dma_alias_mask && in pci_devs_are_dma_aliases()
6439 test_bit(dev2->devfn, dev1->dma_alias_mask)) || in pci_devs_are_dma_aliases()
6440 (dev2->dma_alias_mask && in pci_devs_are_dma_aliases()
6441 test_bit(dev1->devfn, dev2->dma_alias_mask)) || in pci_devs_are_dma_aliases()
6452 return pci_bus_read_dev_vendor_id(pdev->bus, pdev->devfn, &v, 0); in pci_device_is_present()
6458 struct pci_dev *bridge = dev->bus->self; in pci_ignore_hotplug()
6460 dev->ignore_hotplug = 1; in pci_ignore_hotplug()
6463 bridge->ignore_hotplug = 1; in pci_ignore_hotplug()
6468 * pci_real_dma_dev - Get PCI DMA device for PCI device
6471 * Permits the platform to provide architecture-specific functionality to
6488 * Arches that don't want to expose struct resource to userland as-is in
6495 *start = rsrc->start; in pci_resource_to_user()
6496 *end = rsrc->end; in pci_resource_to_user()
6503 * pci_specified_resource_alignment - get resource alignment specified by user.
6567 struct resource *r = &dev->resource[bar]; in pci_request_resource_alignment()
6570 if (!(r->flags & IORESOURCE_MEM)) in pci_request_resource_alignment()
6573 if (r->flags & IORESOURCE_PCI_FIXED) { in pci_request_resource_alignment()
6600 * set r->start to the desired alignment. By itself this in pci_request_resource_alignment()
6615 r->start = 0; in pci_request_resource_alignment()
6616 r->end = align - 1; in pci_request_resource_alignment()
6618 r->flags &= ~IORESOURCE_SIZEALIGN; in pci_request_resource_alignment()
6619 r->flags |= IORESOURCE_STARTALIGN; in pci_request_resource_alignment()
6620 r->start = align; in pci_request_resource_alignment()
6621 r->end = r->start + size - 1; in pci_request_resource_alignment()
6623 r->flags |= IORESOURCE_UNSET; in pci_request_resource_alignment()
6630 * Later on, the kernel will assign page-aligned memory resource back
6642 * VF BARs are read-only zero according to SR-IOV spec r1.1, sec in pci_reassigndev_resource_alignment()
6644 * described by the VF BARx register in the PF's SR-IOV capability. in pci_reassigndev_resource_alignment()
6647 if (dev->is_virtfn) in pci_reassigndev_resource_alignment()
6655 if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL && in pci_reassigndev_resource_alignment()
6656 (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) { in pci_reassigndev_resource_alignment()
6673 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) { in pci_reassigndev_resource_alignment()
6675 r = &dev->resource[i]; in pci_reassigndev_resource_alignment()
6676 if (!(r->flags & IORESOURCE_MEM)) in pci_reassigndev_resource_alignment()
6678 r->flags |= IORESOURCE_UNSET; in pci_reassigndev_resource_alignment()
6679 r->end = resource_size(r) - 1; in pci_reassigndev_resource_alignment()
6680 r->start = 0; in pci_reassigndev_resource_alignment()
6703 if (count >= (PAGE_SIZE - 1)) in resource_alignment_store()
6704 return -EINVAL; in resource_alignment_store()
6708 return -ENOMEM; in resource_alignment_store()
6746 static atomic_t __domain_nr = ATOMIC_INIT(-1);
6755 static int use_dt_domains = -1; in of_pci_bus_find_domain_nr()
6756 int domain = -1; in of_pci_bus_find_domain_nr()
6759 domain = of_get_pci_domain_nr(parent->of_node); in of_pci_bus_find_domain_nr()
6784 * invalidating the domain value (domain = -1) and printing a in of_pci_bus_find_domain_nr()
6794 pr_err("Node %pOF has ", parent->of_node); in of_pci_bus_find_domain_nr()
6795 pr_err("Inconsistent \"linux,pci-domain\" property in DT\n"); in of_pci_bus_find_domain_nr()
6796 domain = -1; in of_pci_bus_find_domain_nr()
6810 * pci_ext_cfg_avail - can we access extended PCI config space?