Lines Matching +full:inactive +full:- +full:delay +full:- +full:ms

1 // SPDX-License-Identifier: GPL-2.0+
6 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
8 * Copyright (C) 2003-2004 Intel Corporation
36 * assert presence detect--and those will still work, they will
37 * just have a bit of extra delay before being probed.
50 return ctrl->pcie->port; in ctrl_dev()
59 int retval, irq = ctrl->pcie->irq; in pciehp_request_irq()
62 ctrl->poll_thread = kthread_run(&pciehp_poll, ctrl, in pciehp_request_irq()
63 "pciehp_poll-%s", in pciehp_request_irq()
65 return PTR_ERR_OR_ZERO(ctrl->poll_thread); in pciehp_request_irq()
80 kthread_stop(ctrl->poll_thread); in pciehp_free_irq()
82 free_irq(ctrl->pcie->irq, ctrl); in pciehp_free_irq()
101 ctrl->cmd_busy = 0; in pcie_poll_cmd()
106 timeout -= 10; in pcie_poll_cmd()
115 unsigned long cmd_timeout = ctrl->cmd_started + duration; in pcie_wait_cmd()
126 if (!ctrl->cmd_busy) in pcie_wait_cmd()
137 timeout = cmd_timeout - now; in pcie_wait_cmd()
139 if (ctrl->slot_ctrl & PCI_EXP_SLTCTL_HPIE && in pcie_wait_cmd()
140 ctrl->slot_ctrl & PCI_EXP_SLTCTL_CCIE) in pcie_wait_cmd()
141 rc = wait_event_timeout(ctrl->queue, !ctrl->cmd_busy, timeout); in pcie_wait_cmd()
147 ctrl->slot_ctrl, in pcie_wait_cmd()
148 jiffies_to_msecs(jiffies - ctrl->cmd_started)); in pcie_wait_cmd()
162 mutex_lock(&ctrl->ctrl_lock); in pcie_do_write_cmd()
178 ctrl->cmd_busy = 1; in pcie_do_write_cmd()
180 ctrl->slot_ctrl = slot_ctrl; in pcie_do_write_cmd()
182 ctrl->cmd_started = jiffies; in pcie_do_write_cmd()
191 if (pdev->broken_cmd_compl && in pcie_do_write_cmd()
193 ctrl->cmd_busy = 0; in pcie_do_write_cmd()
203 mutex_unlock(&ctrl->ctrl_lock); in pcie_do_write_cmd()
207 * pcie_write_cmd - Issue controller command
224 * pciehp_check_link_active() - Is the link active
232 * %-ENODEV.
242 return -ENODEV; in pciehp_check_link_active()
254 int delay = 1000, step = 20; in pci_bus_check_dev() local
265 delay -= step; in pci_bus_check_dev()
266 } while (delay > 0); in pci_bus_check_dev()
269 pr_debug("pci %04x:%02x:%02x.%d id reading try %d times with interval %d ms to get %08x\n", in pci_bus_check_dev()
270 pci_domain_nr(bus), bus->number, PCI_SLOT(devfn), in pci_bus_check_dev()
286 timeout -= 10; in pcie_wait_for_presence()
298 return -1; in pciehp_check_link_status()
301 if (ctrl->inband_presence_disabled) in pciehp_check_link_status()
304 found = pci_bus_check_dev(ctrl->pcie->port->subordinate, in pciehp_check_link_status()
310 &ctrl->pending_events); in pciehp_check_link_status()
318 return -1; in pciehp_check_link_status()
321 pcie_update_link_speed(ctrl->pcie->port->subordinate, lnk_status); in pciehp_check_link_status()
326 return -1; in pciehp_check_link_status()
378 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl); in pciehp_get_attention_status()
405 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl); in pciehp_get_power_status()
430 * pciehp_card_present() - Is the card present
439 * %-ENODEV.
449 return -ENODEV; in pciehp_card_present()
455 * pciehp_card_present_or_link_active() - whether given slot is occupied
464 * port is not present anymore returns %-ENODEV.
500 * pciehp_set_indicators() - set attention indicator, power indicator, or both
531 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, cmd); in pciehp_set_indicators()
541 /* Clear power-fault bit from previous power failures */ in pciehp_power_on_slot()
546 ctrl->power_fault_detected = 0; in pciehp_power_on_slot()
550 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, in pciehp_power_on_slot()
564 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, in pciehp_power_off_slot()
576 atomic_and(~PCI_EXP_SLTSTA_DLLSC, &ctrl->pending_events); in pciehp_ignore_dpc_link_change()
588 down_read_nested(&ctrl->reset_lock, ctrl->depth); in pciehp_ignore_dpc_link_change()
591 up_read(&ctrl->reset_lock); in pciehp_ignore_dpc_link_change()
598 struct device *parent = pdev->dev.parent; in pciehp_isr()
605 if (pdev->current_state == PCI_D3cold || in pciehp_isr()
606 (!(ctrl->slot_ctrl & PCI_EXP_SLTCTL_HPIE) && !pciehp_poll_mode)) in pciehp_isr()
619 atomic_or(RERUN_ISR, &ctrl->pending_events); in pciehp_isr()
645 if (ctrl->power_fault_detected) in pciehp_isr()
648 ctrl->power_fault_detected = true; in pciehp_isr()
663 * So re-read the Slot Status register in case a bit was set in pciehp_isr()
679 ctrl->cmd_busy = 0; in pciehp_isr()
681 wake_up(&ctrl->queue); in pciehp_isr()
689 if (pdev->ignore_hotplug) { in pciehp_isr()
695 atomic_or(events, &ctrl->pending_events); in pciehp_isr()
706 ctrl->ist_running = true; in pciehp_ist()
710 if (atomic_fetch_and(~RERUN_ISR, &ctrl->pending_events) & RERUN_ISR) { in pciehp_ist()
718 events = atomic_xchg(&ctrl->pending_events, 0); in pciehp_ist()
743 ctrl->state == ON_STATE) { in pciehp_ist()
752 down_read_nested(&ctrl->reset_lock, ctrl->depth); in pciehp_ist()
757 up_read(&ctrl->reset_lock); in pciehp_ist()
762 ctrl->ist_running = false; in pciehp_ist()
763 wake_up(&ctrl->requester); in pciehp_ist()
771 schedule_timeout_idle(10 * HZ); /* start with 10 sec delay */ in pciehp_poll()
776 atomic_read(&ctrl->pending_events)) in pciehp_poll()
804 * Always enable link events: thus link-up and link-down shall in pcie_enable_notification()
823 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, cmd); in pcie_enable_notification()
836 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 0); in pcie_disable_notification()
858 * Mask hot-plug interrupt to prevent it triggering immediately in pcie_disable_interrupt()
859 * when the link goes inactive (we still get PME when any of the in pcie_disable_interrupt()
862 * inactive so mask it as well. in pcie_disable_interrupt()
869 * pciehp_slot_reset() - ignore link event caused by error-induced hot reset
882 if (ctrl->state != ON_STATE) in pciehp_slot_reset()
885 pcie_capability_write_word(dev->port, PCI_EXP_SLTSTA, in pciehp_slot_reset()
897 * not seen as a hot-unplug, followed by the hot-plug of the device. Thus,
912 down_write_nested(&ctrl->reset_lock, ctrl->depth); in pciehp_reset_slot()
923 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 0); in pciehp_reset_slot()
925 rc = pci_bridge_secondary_bus_reset(ctrl->pcie->port); in pciehp_reset_slot()
930 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, ctrl_mask); in pciehp_reset_slot()
932 up_write(&ctrl->reset_lock); in pciehp_reset_slot()
939 return -1; in pcie_init_notification()
941 ctrl->notification_enabled = 1; in pcie_init_notification()
947 if (ctrl->notification_enabled) { in pcie_shutdown_notification()
950 ctrl->notification_enabled = 0; in pcie_shutdown_notification()
956 struct pci_dev *pdev = ctrl->pcie->port; in dbg_ctrl()
959 ctrl_dbg(ctrl, "Slot Capabilities : 0x%08x\n", ctrl->slot_cap); in dbg_ctrl()
966 #define FLAG(x, y) (((x) & (y)) ? '+' : '-')
970 struct pci_bus *bus = dev->bus; in pcie_hotplug_depth()
973 while (bus->parent) { in pcie_hotplug_depth()
974 bus = bus->parent; in pcie_hotplug_depth()
975 if (bus->self && bus->self->is_hotplug_bridge) in pcie_hotplug_depth()
987 struct pci_dev *pdev = dev->port; in pcie_init()
988 struct pci_bus *subordinate = pdev->subordinate; in pcie_init()
994 ctrl->pcie = dev; in pcie_init()
995 ctrl->depth = pcie_hotplug_depth(dev->port); in pcie_init()
998 if (pdev->hotplug_user_indicators) in pcie_init()
1005 if (pdev->is_thunderbolt) in pcie_init()
1008 ctrl->slot_cap = slot_cap; in pcie_init()
1009 mutex_init(&ctrl->ctrl_lock); in pcie_init()
1010 mutex_init(&ctrl->state_lock); in pcie_init()
1011 init_rwsem(&ctrl->reset_lock); in pcie_init()
1012 init_waitqueue_head(&ctrl->requester); in pcie_init()
1013 init_waitqueue_head(&ctrl->queue); in pcie_init()
1014 INIT_DELAYED_WORK(&ctrl->button_work, pciehp_queue_pushbutton_work); in pcie_init()
1018 ctrl->state = list_empty(&subordinate->devices) ? OFF_STATE : ON_STATE; in pcie_init()
1025 ctrl->inband_presence_disabled = 1; in pcie_init()
1029 ctrl->inband_presence_disabled = 1; in pcie_init()
1053 pdev->broken_cmd_compl ? " (with Cmd Compl erratum)" : ""); in pcie_init()
1072 cancel_delayed_work_sync(&ctrl->button_work); in pciehp_release_ctrl()
1084 pdev->broken_cmd_compl = 1; in quirk_cmd_compl()