Lines Matching +full:max +full:- +full:outbound +full:- +full:regions
1 // SPDX-License-Identifier: GPL-2.0+
7 * Author: Shawn Lin <shawn.lin@rock-chips.com>
8 * Simon Xue <xxm@rock-chips.com>
15 #include <linux/pci-epc.h>
17 #include <linux/pci-epf.h>
20 #include "pcie-rockchip.h"
23 * struct rockchip_pcie_ep - private data for PCIe endpoint controller driver
26 * @max_regions: maximum number of regions supported by hardware
27 * @ob_region_map: bitmask of mapped outbound regions
28 * @ob_addr: base addresses in the AXI bus where the outbound regions start
30 * dedicated outbound regions is mapped.
35 * dedicated outbound region.
37 * the MSI/legacy IRQ dedicated outbound region.
74 u64 sz = 1ULL << fls64(size - 1); in rockchip_pcie_prog_ep_ob_atu()
83 cpu_addr -= rockchip->mem_res->start; in rockchip_pcie_prog_ep_ob_atu()
84 addr0 = ((is_nor_msg ? 0x10 : (num_pass_bits - 1)) & in rockchip_pcie_prog_ep_ob_atu()
112 ((num_pass_bits - 1) & PCIE_CORE_OB_REGION_ADDR0_NUM_BITS) | in rockchip_pcie_prog_ep_ob_atu()
129 struct rockchip_pcie *rockchip = &ep->rockchip; in rockchip_pcie_ep_write_header()
133 u32 vid_regs = (hdr->vendorid & GENMASK(15, 0)) | in rockchip_pcie_ep_write_header()
134 (hdr->subsys_vendor_id & GENMASK(31, 16)) << 16; in rockchip_pcie_ep_write_header()
140 rockchip_pcie_write(rockchip, hdr->deviceid << 16, in rockchip_pcie_ep_write_header()
144 hdr->revid | in rockchip_pcie_ep_write_header()
145 hdr->progif_code << 8 | in rockchip_pcie_ep_write_header()
146 hdr->subclass_code << 16 | in rockchip_pcie_ep_write_header()
147 hdr->baseclass_code << 24, in rockchip_pcie_ep_write_header()
149 rockchip_pcie_write(rockchip, hdr->cache_line_size, in rockchip_pcie_ep_write_header()
152 rockchip_pcie_write(rockchip, hdr->subsys_id << 16, in rockchip_pcie_ep_write_header()
155 rockchip_pcie_write(rockchip, hdr->interrupt_pin << 8, in rockchip_pcie_ep_write_header()
166 struct rockchip_pcie *rockchip = &ep->rockchip; in rockchip_pcie_ep_set_bar()
167 dma_addr_t bar_phys = epf_bar->phys_addr; in rockchip_pcie_ep_set_bar()
168 enum pci_barno bar = epf_bar->barno; in rockchip_pcie_ep_set_bar()
169 int flags = epf_bar->flags; in rockchip_pcie_ep_set_bar()
174 sz = max_t(size_t, epf_bar->size, MIN_EP_APERTURE); in rockchip_pcie_ep_set_bar()
180 sz = 1ULL << fls64(sz - 1); in rockchip_pcie_ep_set_bar()
181 aperture = ilog2(sz) - 7; /* 128B -> 0, 256B -> 1, 512B -> 2, ... */ in rockchip_pcie_ep_set_bar()
190 return -EINVAL; in rockchip_pcie_ep_set_bar()
209 b = bar - BAR_4; in rockchip_pcie_ep_set_bar()
234 struct rockchip_pcie *rockchip = &ep->rockchip; in rockchip_pcie_ep_clear_bar()
236 enum pci_barno bar = epf_bar->barno; in rockchip_pcie_ep_clear_bar()
243 b = bar - BAR_4; in rockchip_pcie_ep_clear_bar()
264 struct rockchip_pcie *pcie = &ep->rockchip; in rockchip_pcie_ep_map_addr()
267 r = find_first_zero_bit(&ep->ob_region_map, BITS_PER_LONG); in rockchip_pcie_ep_map_addr()
272 if (r >= ep->max_regions - 1) { in rockchip_pcie_ep_map_addr()
273 dev_err(&epc->dev, "no free outbound region\n"); in rockchip_pcie_ep_map_addr()
274 return -EINVAL; in rockchip_pcie_ep_map_addr()
280 set_bit(r, &ep->ob_region_map); in rockchip_pcie_ep_map_addr()
281 ep->ob_addr[r] = addr; in rockchip_pcie_ep_map_addr()
290 struct rockchip_pcie *rockchip = &ep->rockchip; in rockchip_pcie_ep_unmap_addr()
293 for (r = 0; r < ep->max_regions - 1; r++) in rockchip_pcie_ep_unmap_addr()
294 if (ep->ob_addr[r] == addr) in rockchip_pcie_ep_unmap_addr()
301 if (r == ep->max_regions - 1) in rockchip_pcie_ep_unmap_addr()
306 ep->ob_addr[r] = 0; in rockchip_pcie_ep_unmap_addr()
307 clear_bit(r, &ep->ob_region_map); in rockchip_pcie_ep_unmap_addr()
314 struct rockchip_pcie *rockchip = &ep->rockchip; in rockchip_pcie_ep_set_msi()
334 struct rockchip_pcie *rockchip = &ep->rockchip; in rockchip_pcie_ep_get_msi()
341 return -EINVAL; in rockchip_pcie_ep_get_msi()
350 struct rockchip_pcie *rockchip = &ep->rockchip; in rockchip_pcie_ep_assert_intx()
351 u32 r = ep->max_regions - 1; in rockchip_pcie_ep_assert_intx()
356 if (unlikely(ep->irq_pci_addr != ROCKCHIP_PCIE_EP_PCI_LEGACY_IRQ_ADDR || in rockchip_pcie_ep_assert_intx()
357 ep->irq_pci_fn != fn)) { in rockchip_pcie_ep_assert_intx()
360 ep->irq_phys_addr, 0, 0); in rockchip_pcie_ep_assert_intx()
361 ep->irq_pci_addr = ROCKCHIP_PCIE_EP_PCI_LEGACY_IRQ_ADDR; in rockchip_pcie_ep_assert_intx()
362 ep->irq_pci_fn = fn; in rockchip_pcie_ep_assert_intx()
367 ep->irq_pending |= BIT(intx); in rockchip_pcie_ep_assert_intx()
370 ep->irq_pending &= ~BIT(intx); in rockchip_pcie_ep_assert_intx()
379 if ((status != 0) ^ (ep->irq_pending != 0)) { in rockchip_pcie_ep_assert_intx()
389 writel(0, ep->irq_cpu_addr + offset); in rockchip_pcie_ep_assert_intx()
397 cmd = rockchip_pcie_read(&ep->rockchip, in rockchip_pcie_ep_send_legacy_irq()
402 return -EINVAL; in rockchip_pcie_ep_send_legacy_irq()
418 struct rockchip_pcie *rockchip = &ep->rockchip; in rockchip_pcie_ep_send_msi_irq()
424 flags = rockchip_pcie_read(&ep->rockchip, in rockchip_pcie_ep_send_msi_irq()
428 return -EINVAL; in rockchip_pcie_ep_send_msi_irq()
435 return -EINVAL; in rockchip_pcie_ep_send_msi_irq()
438 data_mask = msi_count - 1; in rockchip_pcie_ep_send_msi_irq()
443 data = (data & ~data_mask) | ((interrupt_num - 1) & data_mask); in rockchip_pcie_ep_send_msi_irq()
457 /* Set the outbound region if needed. */ in rockchip_pcie_ep_send_msi_irq()
458 if (unlikely(ep->irq_pci_addr != (pci_addr & ~pci_addr_mask) || in rockchip_pcie_ep_send_msi_irq()
459 ep->irq_pci_fn != fn)) { in rockchip_pcie_ep_send_msi_irq()
460 rockchip_pcie_prog_ep_ob_atu(rockchip, fn, ep->max_regions - 1, in rockchip_pcie_ep_send_msi_irq()
462 ep->irq_phys_addr, in rockchip_pcie_ep_send_msi_irq()
465 ep->irq_pci_addr = (pci_addr & ~pci_addr_mask); in rockchip_pcie_ep_send_msi_irq()
466 ep->irq_pci_fn = fn; in rockchip_pcie_ep_send_msi_irq()
469 writew(data, ep->irq_cpu_addr + (pci_addr & pci_addr_mask)); in rockchip_pcie_ep_send_msi_irq()
485 return -EINVAL; in rockchip_pcie_ep_raise_irq()
492 struct rockchip_pcie *rockchip = &ep->rockchip; in rockchip_pcie_ep_start()
497 list_for_each_entry(epf, &epc->pci_epf, list) in rockchip_pcie_ep_start()
498 cfg |= BIT(epf->func_no); in rockchip_pcie_ep_start()
533 struct device *dev = rockchip->dev; in rockchip_pcie_parse_ep_dt()
544 err = of_property_read_u32(dev->of_node, in rockchip_pcie_parse_ep_dt()
545 "rockchip,max-outbound-regions", in rockchip_pcie_parse_ep_dt()
546 &ep->max_regions); in rockchip_pcie_parse_ep_dt()
547 if (err < 0 || ep->max_regions > MAX_REGION_LIMIT) in rockchip_pcie_parse_ep_dt()
548 ep->max_regions = MAX_REGION_LIMIT; in rockchip_pcie_parse_ep_dt()
550 err = of_property_read_u8(dev->of_node, "max-functions", in rockchip_pcie_parse_ep_dt()
551 &ep->epc->max_functions); in rockchip_pcie_parse_ep_dt()
553 ep->epc->max_functions = 1; in rockchip_pcie_parse_ep_dt()
559 { .compatible = "rockchip,rk3399-pcie-ep"},
565 struct device *dev = &pdev->dev; in rockchip_pcie_ep_probe()
574 return -ENOMEM; in rockchip_pcie_ep_probe()
576 rockchip = &ep->rockchip; in rockchip_pcie_ep_probe()
577 rockchip->is_rc = false; in rockchip_pcie_ep_probe()
578 rockchip->dev = dev; in rockchip_pcie_ep_probe()
586 ep->epc = epc; in rockchip_pcie_ep_probe()
605 max_regions = ep->max_regions; in rockchip_pcie_ep_probe()
606 ep->ob_addr = devm_kcalloc(dev, max_regions, sizeof(*ep->ob_addr), in rockchip_pcie_ep_probe()
609 if (!ep->ob_addr) { in rockchip_pcie_ep_probe()
610 err = -ENOMEM; in rockchip_pcie_ep_probe()
617 err = pci_epc_mem_init(epc, rockchip->mem_res->start, in rockchip_pcie_ep_probe()
618 resource_size(rockchip->mem_res), PAGE_SIZE); in rockchip_pcie_ep_probe()
624 ep->irq_cpu_addr = pci_epc_mem_alloc_addr(epc, &ep->irq_phys_addr, in rockchip_pcie_ep_probe()
626 if (!ep->irq_cpu_addr) { in rockchip_pcie_ep_probe()
628 err = -ENOMEM; in rockchip_pcie_ep_probe()
632 ep->irq_pci_addr = ROCKCHIP_PCIE_EP_DUMMY_IRQ_ADDR; in rockchip_pcie_ep_probe()
646 .name = "rockchip-pcie-ep",