Lines Matching full:pcie
3 * PCIe driver for Renesas R-Car SoCs
7 * arch/sh/drivers/pci/pcie-sh7786.c
33 #include "pcie-rcar.h"
46 * Here we keep a static copy of the remapped PCIe controller address.
48 * PCIe controller, to provide quick access to the PCIe controller in
53 * Static copy of PCIe device pointer, so we can check whether the
59 /* Structure representing the PCIe interface */
61 struct rcar_pcie pcie; member
86 * Test if the PCIe controller received PM_ENTER_L1 DLLP and in rcar_pcie_wakeup()
87 * the PCIe controller is not in L1 link state. If true, apply in rcar_pcie_wakeup()
109 static u32 rcar_read_conf(struct rcar_pcie *pcie, int where) in rcar_read_conf() argument
112 u32 val = rcar_pci_read_reg(pcie, where & ~3); in rcar_read_conf()
134 static int rcar_pci_write_reg_workaround(struct rcar_pcie *pcie, u32 val, in rcar_pci_write_reg_workaround() argument
141 : "+r"(error):"r"(val), "r"(pcie->base + reg) : "memory"); in rcar_pci_write_reg_workaround()
143 rcar_pci_write_reg(pcie, val, reg); in rcar_pci_write_reg_workaround()
148 static int rcar_pci_read_reg_workaround(struct rcar_pcie *pcie, u32 *val, in rcar_pci_read_reg_workaround() argument
155 : "+r"(error), "=r"(*val) : "r"(pcie->base + reg) : "memory"); in rcar_pci_read_reg_workaround()
160 *val = rcar_pci_read_reg(pcie, reg); in rcar_pci_read_reg_workaround()
170 struct rcar_pcie *pcie = &host->pcie; in rcar_pcie_config_access() local
175 ret = rcar_pcie_wakeup(pcie->dev, pcie->base); in rcar_pcie_config_access()
206 *data = rcar_pci_read_reg(pcie, PCICONF(index)); in rcar_pcie_config_access()
208 rcar_pci_write_reg(pcie, *data, PCICONF(index)); in rcar_pcie_config_access()
214 rcar_pci_write_reg(pcie, rcar_pci_read_reg(pcie, PCIEERRFR), PCIEERRFR); in rcar_pcie_config_access()
217 rcar_pci_write_reg(pcie, PCIE_CONF_BUS(bus->number) | in rcar_pcie_config_access()
222 rcar_pci_write_reg(pcie, CONFIG_SEND_ENABLE | TYPE0, PCIECCTLR); in rcar_pcie_config_access()
224 rcar_pci_write_reg(pcie, CONFIG_SEND_ENABLE | TYPE1, PCIECCTLR); in rcar_pcie_config_access()
227 if (rcar_pci_read_reg(pcie, PCIEERRFR) & UNSUPPORTED_REQUEST) in rcar_pcie_config_access()
231 if (rcar_read_conf(pcie, RCONF(PCI_STATUS)) & in rcar_pcie_config_access()
236 ret = rcar_pci_read_reg_workaround(pcie, data, PCIECDR); in rcar_pcie_config_access()
238 ret = rcar_pci_write_reg_workaround(pcie, *data, PCIECDR); in rcar_pcie_config_access()
241 rcar_pci_write_reg(pcie, 0, PCIECCTLR); in rcar_pcie_config_access()
262 dev_dbg(&bus->dev, "pcie-config-read: bus=%3d devfn=0x%04x where=0x%04x size=%d val=0x%08x\n", in rcar_pcie_read_conf()
282 dev_dbg(&bus->dev, "pcie-config-write: bus=%3d devfn=0x%04x where=0x%04x size=%d val=0x%08x\n", in rcar_pcie_write_conf()
307 static void rcar_pcie_force_speedup(struct rcar_pcie *pcie) in rcar_pcie_force_speedup() argument
309 struct device *dev = pcie->dev; in rcar_pcie_force_speedup()
313 if ((rcar_pci_read_reg(pcie, MACS2R) & LINK_SPEED) != LINK_SPEED_5_0GTS) in rcar_pcie_force_speedup()
316 if (rcar_pci_read_reg(pcie, MACCTLR) & SPEED_CHANGE) { in rcar_pcie_force_speedup()
321 macsr = rcar_pci_read_reg(pcie, MACSR); in rcar_pcie_force_speedup()
326 rcar_rmw32(pcie, EXPCAP(12), PCI_EXP_LNKSTA_CLS, in rcar_pcie_force_speedup()
330 rcar_rmw32(pcie, MACCGSPSETR, SPCNGRSN, 0); in rcar_pcie_force_speedup()
334 rcar_pci_write_reg(pcie, macsr, MACSR); in rcar_pcie_force_speedup()
337 rcar_rmw32(pcie, MACCTLR, SPEED_CHANGE, SPEED_CHANGE); in rcar_pcie_force_speedup()
340 macsr = rcar_pci_read_reg(pcie, MACSR); in rcar_pcie_force_speedup()
343 rcar_pci_write_reg(pcie, macsr, MACSR); in rcar_pcie_force_speedup()
363 struct rcar_pcie *pcie = &host->pcie; in rcar_pcie_hw_enable() local
370 rcar_pcie_force_speedup(pcie); in rcar_pcie_hw_enable()
382 rcar_pcie_set_outbound(pcie, i, win); in rcar_pcie_hw_enable()
403 static int phy_wait_for_ack(struct rcar_pcie *pcie) in phy_wait_for_ack() argument
405 struct device *dev = pcie->dev; in phy_wait_for_ack()
409 if (rcar_pci_read_reg(pcie, H1_PCIEPHYADRR) & PHY_ACK) in phy_wait_for_ack()
415 dev_err(dev, "Access to PCIe phy timed out\n"); in phy_wait_for_ack()
420 static void phy_write_reg(struct rcar_pcie *pcie, in phy_write_reg() argument
432 rcar_pci_write_reg(pcie, data, H1_PCIEPHYDOUTR); in phy_write_reg()
433 rcar_pci_write_reg(pcie, phyaddr, H1_PCIEPHYADRR); in phy_write_reg()
436 phy_wait_for_ack(pcie); in phy_write_reg()
439 rcar_pci_write_reg(pcie, 0, H1_PCIEPHYDOUTR); in phy_write_reg()
440 rcar_pci_write_reg(pcie, 0, H1_PCIEPHYADRR); in phy_write_reg()
443 phy_wait_for_ack(pcie); in phy_write_reg()
446 static int rcar_pcie_hw_init(struct rcar_pcie *pcie) in rcar_pcie_hw_init() argument
451 rcar_pci_write_reg(pcie, 0, PCIETCTLR); in rcar_pcie_hw_init()
454 rcar_pci_write_reg(pcie, 1, PCIEMSR); in rcar_pcie_hw_init()
456 err = rcar_pcie_wait_for_phyrdy(pcie); in rcar_pcie_hw_init()
465 rcar_pci_write_reg(pcie, PCI_CLASS_BRIDGE_PCI_NORMAL << 8, IDSETR1); in rcar_pcie_hw_init()
471 rcar_rmw32(pcie, RCONF(PCI_SECONDARY_BUS), 0xff, 1); in rcar_pcie_hw_init()
472 rcar_rmw32(pcie, RCONF(PCI_SUBORDINATE_BUS), 0xff, 1); in rcar_pcie_hw_init()
475 rcar_rmw32(pcie, REXPCAP(0), 0xff, PCI_CAP_ID_EXP); in rcar_pcie_hw_init()
476 rcar_rmw32(pcie, REXPCAP(PCI_EXP_FLAGS), in rcar_pcie_hw_init()
478 rcar_rmw32(pcie, RCONF(PCI_HEADER_TYPE), 0x7f, in rcar_pcie_hw_init()
482 rcar_rmw32(pcie, REXPCAP(PCI_EXP_LNKCAP), PCI_EXP_LNKCAP_DLLLARC, in rcar_pcie_hw_init()
486 rcar_rmw32(pcie, REXPCAP(PCI_EXP_SLTCAP), PCI_EXP_SLTCAP_PSN, 0); in rcar_pcie_hw_init()
489 rcar_rmw32(pcie, TLCTLR + 1, 0x3f, 50); in rcar_pcie_hw_init()
492 rcar_rmw32(pcie, RVCCAP(0), 0xfff00000, 0); in rcar_pcie_hw_init()
496 rcar_pci_write_reg(pcie, 0x801f0000, PCIEMSITXR); in rcar_pcie_hw_init()
498 rcar_pci_write_reg(pcie, MACCTLR_INIT_VAL, MACCTLR); in rcar_pcie_hw_init()
501 rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR); in rcar_pcie_hw_init()
504 err = rcar_pcie_wait_for_dl(pcie); in rcar_pcie_hw_init()
509 rcar_rmw32(pcie, PCIEINTXR, 0, 0xF << 8); in rcar_pcie_hw_init()
518 struct rcar_pcie *pcie = &host->pcie; in rcar_pcie_phy_init_h1() local
521 phy_write_reg(pcie, 0, 0x42, 0x1, 0x0EC34191); in rcar_pcie_phy_init_h1()
522 phy_write_reg(pcie, 1, 0x42, 0x1, 0x0EC34180); in rcar_pcie_phy_init_h1()
523 phy_write_reg(pcie, 0, 0x43, 0x1, 0x00210188); in rcar_pcie_phy_init_h1()
524 phy_write_reg(pcie, 1, 0x43, 0x1, 0x00210188); in rcar_pcie_phy_init_h1()
525 phy_write_reg(pcie, 0, 0x44, 0x1, 0x015C0014); in rcar_pcie_phy_init_h1()
526 phy_write_reg(pcie, 1, 0x44, 0x1, 0x015C0014); in rcar_pcie_phy_init_h1()
527 phy_write_reg(pcie, 1, 0x4C, 0x1, 0x786174A0); in rcar_pcie_phy_init_h1()
528 phy_write_reg(pcie, 1, 0x4D, 0x1, 0x048000BB); in rcar_pcie_phy_init_h1()
529 phy_write_reg(pcie, 0, 0x51, 0x1, 0x079EC062); in rcar_pcie_phy_init_h1()
530 phy_write_reg(pcie, 0, 0x52, 0x1, 0x20000000); in rcar_pcie_phy_init_h1()
531 phy_write_reg(pcie, 1, 0x52, 0x1, 0x20000000); in rcar_pcie_phy_init_h1()
532 phy_write_reg(pcie, 1, 0x56, 0x1, 0x00003806); in rcar_pcie_phy_init_h1()
534 phy_write_reg(pcie, 0, 0x60, 0x1, 0x004B03A5); in rcar_pcie_phy_init_h1()
535 phy_write_reg(pcie, 0, 0x64, 0x1, 0x3F0F1F0F); in rcar_pcie_phy_init_h1()
536 phy_write_reg(pcie, 0, 0x66, 0x1, 0x00008000); in rcar_pcie_phy_init_h1()
543 struct rcar_pcie *pcie = &host->pcie; in rcar_pcie_phy_init_gen2() local
549 rcar_pci_write_reg(pcie, 0x000f0030, GEN2_PCIEPHYADDR); in rcar_pcie_phy_init_gen2()
550 rcar_pci_write_reg(pcie, 0x00381203, GEN2_PCIEPHYDATA); in rcar_pcie_phy_init_gen2()
551 rcar_pci_write_reg(pcie, 0x00000001, GEN2_PCIEPHYCTRL); in rcar_pcie_phy_init_gen2()
552 rcar_pci_write_reg(pcie, 0x00000006, GEN2_PCIEPHYCTRL); in rcar_pcie_phy_init_gen2()
554 rcar_pci_write_reg(pcie, 0x000f0054, GEN2_PCIEPHYADDR); in rcar_pcie_phy_init_gen2()
556 rcar_pci_write_reg(pcie, 0x13802007, GEN2_PCIEPHYDATA); in rcar_pcie_phy_init_gen2()
557 rcar_pci_write_reg(pcie, 0x00000001, GEN2_PCIEPHYCTRL); in rcar_pcie_phy_init_gen2()
558 rcar_pci_write_reg(pcie, 0x00000006, GEN2_PCIEPHYCTRL); in rcar_pcie_phy_init_gen2()
581 struct rcar_pcie *pcie = &host->pcie; in rcar_pcie_msi_irq() local
583 struct device *dev = pcie->dev; in rcar_pcie_msi_irq()
586 reg = rcar_pci_read_reg(pcie, PCIEMSIFR); in rcar_pcie_msi_irq()
600 rcar_pci_write_reg(pcie, BIT(index), PCIEMSIFR); in rcar_pcie_msi_irq()
604 reg = rcar_pci_read_reg(pcie, PCIEMSIFR); in rcar_pcie_msi_irq()
628 .name = "PCIe MSI",
637 struct rcar_pcie *pcie = &msi_to_host(msi)->pcie; in rcar_msi_irq_ack() local
640 rcar_pci_write_reg(pcie, BIT(d->hwirq), PCIEMSIFR); in rcar_msi_irq_ack()
646 struct rcar_pcie *pcie = &msi_to_host(msi)->pcie; in rcar_msi_irq_mask() local
651 value = rcar_pci_read_reg(pcie, PCIEMSIIER); in rcar_msi_irq_mask()
653 rcar_pci_write_reg(pcie, value, PCIEMSIIER); in rcar_msi_irq_mask()
660 struct rcar_pcie *pcie = &msi_to_host(msi)->pcie; in rcar_msi_irq_unmask() local
665 value = rcar_pci_read_reg(pcie, PCIEMSIIER); in rcar_msi_irq_unmask()
667 rcar_pci_write_reg(pcie, value, PCIEMSIIER); in rcar_msi_irq_unmask()
679 struct rcar_pcie *pcie = &msi_to_host(msi)->pcie; in rcar_compose_msi_msg() local
681 msg->address_lo = rcar_pci_read_reg(pcie, PCIEMSIALR) & ~MSIFE; in rcar_compose_msi_msg()
682 msg->address_hi = rcar_pci_read_reg(pcie, PCIEMSIAUR); in rcar_compose_msi_msg()
745 struct rcar_pcie *pcie = &msi_to_host(msi)->pcie; in rcar_allocate_domains() local
746 struct fwnode_handle *fwnode = dev_fwnode(pcie->dev); in rcar_allocate_domains()
752 dev_err(pcie->dev, "failed to create IRQ domain\n"); in rcar_allocate_domains()
759 dev_err(pcie->dev, "failed to create MSI domain\n"); in rcar_allocate_domains()
777 struct rcar_pcie *pcie = &host->pcie; in rcar_pcie_enable_msi() local
778 struct device *dev = pcie->dev; in rcar_pcie_enable_msi()
812 rcar_pci_write_reg(pcie, 0, PCIEMSIIER); in rcar_pcie_enable_msi()
818 rcar_pci_write_reg(pcie, lower_32_bits(res.start) | MSIFE, PCIEMSIALR); in rcar_pcie_enable_msi()
819 rcar_pci_write_reg(pcie, upper_32_bits(res.start), PCIEMSIAUR); in rcar_pcie_enable_msi()
830 struct rcar_pcie *pcie = &host->pcie; in rcar_pcie_teardown_msi() local
833 rcar_pci_write_reg(pcie, 0, PCIEMSIIER); in rcar_pcie_teardown_msi()
836 rcar_pci_write_reg(pcie, 0, PCIEMSIALR); in rcar_pcie_teardown_msi()
843 struct rcar_pcie *pcie = &host->pcie; in rcar_pcie_get_resources() local
844 struct device *dev = pcie->dev; in rcar_pcie_get_resources()
848 host->phy = devm_phy_optional_get(dev, "pcie"); in rcar_pcie_get_resources()
856 pcie->base = devm_ioremap_resource(dev, &res); in rcar_pcie_get_resources()
857 if (IS_ERR(pcie->base)) in rcar_pcie_get_resources()
858 return PTR_ERR(pcie->base); in rcar_pcie_get_resources()
862 dev_err(dev, "cannot get pcie bus clock\n"); in rcar_pcie_get_resources()
884 pcie_base = pcie->base; in rcar_pcie_get_resources()
885 pcie_dev = pcie->dev; in rcar_pcie_get_resources()
896 static int rcar_pcie_inbound_ranges(struct rcar_pcie *pcie, in rcar_pcie_inbound_ranges() argument
914 dev_err(pcie->dev, "Failed to map inbound regions!\n"); in rcar_pcie_inbound_ranges()
934 rcar_pcie_set_inbound(pcie, cpu_addr, pci_addr, in rcar_pcie_inbound_ranges()
953 err = rcar_pcie_inbound_ranges(&host->pcie, entry, &index); in rcar_pcie_parse_map_dma_ranges()
962 { .compatible = "renesas,pcie-r8a7779",
964 { .compatible = "renesas,pcie-r8a7790",
966 { .compatible = "renesas,pcie-r8a7791",
968 { .compatible = "renesas,pcie-rcar-gen2",
970 { .compatible = "renesas,pcie-r8a7795",
972 { .compatible = "renesas,pcie-rcar-gen3",
981 struct rcar_pcie *pcie; in rcar_pcie_probe() local
991 pcie = &host->pcie; in rcar_pcie_probe()
992 pcie->dev = dev; in rcar_pcie_probe()
995 pm_runtime_enable(pcie->dev); in rcar_pcie_probe()
996 err = pm_runtime_get_sync(pcie->dev); in rcar_pcie_probe()
998 dev_err(pcie->dev, "pm_runtime_get_sync failed\n"); in rcar_pcie_probe()
1021 dev_err(dev, "failed to init PCIe PHY\n"); in rcar_pcie_probe()
1026 if (rcar_pcie_hw_init(pcie)) { in rcar_pcie_probe()
1027 dev_info(dev, "PCIe link down\n"); in rcar_pcie_probe()
1032 data = rcar_pci_read_reg(pcie, MACSR); in rcar_pcie_probe()
1033 dev_info(dev, "PCIe x%d: link up\n", (data >> 20) & 0x3f); in rcar_pcie_probe()
1078 struct rcar_pcie *pcie = &host->pcie; in rcar_pcie_resume() local
1089 dev_info(dev, "PCIe link down\n"); in rcar_pcie_resume()
1093 data = rcar_pci_read_reg(pcie, MACSR); in rcar_pcie_resume()
1094 dev_info(dev, "PCIe x%d: link up\n", (data >> 20) & 0x3f); in rcar_pcie_resume()
1102 rcar_pci_write_reg(pcie, upper_32_bits(res.start), PCIEMSIAUR); in rcar_pcie_resume()
1103 rcar_pci_write_reg(pcie, lower_32_bits(res.start) | MSIFE, PCIEMSIALR); in rcar_pcie_resume()
1106 rcar_pci_write_reg(pcie, val, PCIEMSIIER); in rcar_pcie_resume()
1117 struct rcar_pcie *pcie = &host->pcie; in rcar_pcie_resume_noirq() local
1119 if (rcar_pci_read_reg(pcie, PMSR) && in rcar_pcie_resume_noirq()
1120 !(rcar_pci_read_reg(pcie, PCIETCTLR) & DL_DOWN)) in rcar_pcie_resume_noirq()
1123 /* Re-establish the PCIe link */ in rcar_pcie_resume_noirq()
1124 rcar_pci_write_reg(pcie, MACCTLR_INIT_VAL, MACCTLR); in rcar_pcie_resume_noirq()
1125 rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR); in rcar_pcie_resume_noirq()
1126 return rcar_pcie_wait_for_dl(pcie); in rcar_pcie_resume_noirq()
1136 .name = "rcar-pcie",
1152 { .compatible = "renesas,pcie-r8a7779" },
1153 { .compatible = "renesas,pcie-r8a7790" },
1154 { .compatible = "renesas,pcie-r8a7791" },
1155 { .compatible = "renesas,pcie-rcar-gen2" },