Lines Matching +full:pcie +full:- +full:ob +full:- +full:axi +full:- +full:offset
1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2014 Hauke Mehrtens <hauke@hauke-m.de>
9 #include <linux/pci-ecam.h>
17 #include <linux/irqchip/arm-gic-v3.h>
25 #include "pcie-iproc.h"
92 * struct iproc_pcie_ob_map - iProc PCIe outbound mapping controller-specific
139 * enum iproc_pcie_ib_map_type - iProc PCIe inbound mapping type
151 * struct iproc_pcie_ib_map - iProc PCIe inbound mapping controller-specific
160 * @imap_addr_offset: register offset between the upper and lower 32-bit
162 * @imap_window_offset: register offset between each IMAP window
230 * iProc PCIe host registers
307 /* iProc PCIe PAXB BCMA registers */
318 /* iProc PCIe PAXB registers */
334 /* iProc PCIe PAXB v2 registers */
365 /* iProc PCIe PAXC v1 registers */
374 /* iProc PCIe PAXC v2 registers */
401 struct iproc_pcie *pcie = bus->sysdata; in iproc_data() local
402 return pcie; in iproc_data()
410 static inline u16 iproc_pcie_reg_offset(struct iproc_pcie *pcie, in iproc_pcie_reg_offset() argument
413 return pcie->reg_offsets[reg]; in iproc_pcie_reg_offset()
416 static inline u32 iproc_pcie_read_reg(struct iproc_pcie *pcie, in iproc_pcie_read_reg() argument
419 u16 offset = iproc_pcie_reg_offset(pcie, reg); in iproc_pcie_read_reg() local
421 if (iproc_pcie_reg_is_invalid(offset)) in iproc_pcie_read_reg()
424 return readl(pcie->base + offset); in iproc_pcie_read_reg()
427 static inline void iproc_pcie_write_reg(struct iproc_pcie *pcie, in iproc_pcie_write_reg() argument
430 u16 offset = iproc_pcie_reg_offset(pcie, reg); in iproc_pcie_write_reg() local
432 if (iproc_pcie_reg_is_invalid(offset)) in iproc_pcie_write_reg()
435 writel(val, pcie->base + offset); in iproc_pcie_write_reg()
441 * (typically seen during enumeration with multi-function devices) from
447 struct iproc_pcie *pcie = iproc_data(bus); in iproc_pcie_apb_err_disable() local
450 if (bus->number && pcie->has_apb_err_disable) { in iproc_pcie_apb_err_disable()
451 val = iproc_pcie_read_reg(pcie, IPROC_PCIE_APB_ERR_EN); in iproc_pcie_apb_err_disable()
456 iproc_pcie_write_reg(pcie, IPROC_PCIE_APB_ERR_EN, val); in iproc_pcie_apb_err_disable()
460 static void __iomem *iproc_pcie_map_ep_cfg_reg(struct iproc_pcie *pcie, in iproc_pcie_map_ep_cfg_reg() argument
465 u16 offset; in iproc_pcie_map_ep_cfg_reg() local
472 iproc_pcie_write_reg(pcie, IPROC_PCIE_CFG_ADDR, val); in iproc_pcie_map_ep_cfg_reg()
473 offset = iproc_pcie_reg_offset(pcie, IPROC_PCIE_CFG_DATA); in iproc_pcie_map_ep_cfg_reg()
475 if (iproc_pcie_reg_is_invalid(offset)) in iproc_pcie_map_ep_cfg_reg()
478 return (pcie->base + offset); in iproc_pcie_map_ep_cfg_reg()
481 static unsigned int iproc_pcie_cfg_retry(struct iproc_pcie *pcie, in iproc_pcie_cfg_retry() argument
489 * As per PCIe spec r3.1, sec 2.3.2, CRS Software Visibility only in iproc_pcie_cfg_retry()
500 * Note that a non-Vendor ID config register may have a value of in iproc_pcie_cfg_retry()
506 while (data == CFG_RETRY_STATUS && timeout--) { in iproc_pcie_cfg_retry()
512 status = iproc_pcie_read_reg(pcie, IPROC_PCIE_CFG_RD_STATUS); in iproc_pcie_cfg_retry()
526 static void iproc_pcie_fix_cap(struct iproc_pcie *pcie, int where, u32 *val) in iproc_pcie_fix_cap() argument
540 pcie->fix_paxc_cap = true; in iproc_pcie_fix_cap()
544 if (pcie->fix_paxc_cap) { in iproc_pcie_fix_cap()
545 /* advertise PM, force next capability to PCIe */ in iproc_pcie_fix_cap()
552 if (pcie->fix_paxc_cap) { in iproc_pcie_fix_cap()
572 struct iproc_pcie *pcie = iproc_data(bus); in iproc_pcie_config_read() local
573 unsigned int busno = bus->number; in iproc_pcie_config_read()
582 iproc_pcie_fix_cap(pcie, where, val); in iproc_pcie_config_read()
587 cfg_data_p = iproc_pcie_map_ep_cfg_reg(pcie, busno, devfn, where); in iproc_pcie_config_read()
592 data = iproc_pcie_cfg_retry(pcie, cfg_data_p); in iproc_pcie_config_read()
596 *val = (data >> (8 * (where & 3))) & ((1 << (size * 8)) - 1); in iproc_pcie_config_read()
611 if (pcie->rej_unconfig_pf && in iproc_pcie_config_read()
624 static void __iomem *iproc_pcie_map_cfg_bus(struct iproc_pcie *pcie, in iproc_pcie_map_cfg_bus() argument
628 u16 offset; in iproc_pcie_map_cfg_bus() local
635 iproc_pcie_write_reg(pcie, IPROC_PCIE_CFG_IND_ADDR, in iproc_pcie_map_cfg_bus()
637 offset = iproc_pcie_reg_offset(pcie, IPROC_PCIE_CFG_IND_DATA); in iproc_pcie_map_cfg_bus()
638 if (iproc_pcie_reg_is_invalid(offset)) in iproc_pcie_map_cfg_bus()
641 return (pcie->base + offset); in iproc_pcie_map_cfg_bus()
644 return iproc_pcie_map_ep_cfg_reg(pcie, busno, devfn, where); in iproc_pcie_map_cfg_bus()
651 return iproc_pcie_map_cfg_bus(iproc_data(bus), bus->number, devfn, in iproc_pcie_bus_map_cfg_bus()
655 static int iproc_pci_raw_config_read32(struct iproc_pcie *pcie, in iproc_pci_raw_config_read32() argument
661 addr = iproc_pcie_map_cfg_bus(pcie, 0, devfn, where & ~0x3); in iproc_pci_raw_config_read32()
668 *val = (*val >> (8 * (where & 3))) & ((1 << (size * 8)) - 1); in iproc_pci_raw_config_read32()
673 static int iproc_pci_raw_config_write32(struct iproc_pcie *pcie, in iproc_pci_raw_config_write32() argument
680 addr = iproc_pcie_map_cfg_bus(pcie, 0, devfn, where & ~0x3); in iproc_pci_raw_config_write32()
689 mask = ~(((1 << (size * 8)) - 1) << ((where & 0x3) * 8)); in iproc_pci_raw_config_write32()
701 struct iproc_pcie *pcie = iproc_data(bus); in iproc_pcie_config_read32() local
704 if (pcie->iproc_cfg_read) in iproc_pcie_config_read32()
731 static void iproc_pcie_perst_ctrl(struct iproc_pcie *pcie, bool assert) in iproc_pcie_perst_ctrl() argument
740 if (pcie->ep_is_internal) in iproc_pcie_perst_ctrl()
744 val = iproc_pcie_read_reg(pcie, IPROC_PCIE_CLK_CTRL); in iproc_pcie_perst_ctrl()
747 iproc_pcie_write_reg(pcie, IPROC_PCIE_CLK_CTRL, val); in iproc_pcie_perst_ctrl()
750 val = iproc_pcie_read_reg(pcie, IPROC_PCIE_CLK_CTRL); in iproc_pcie_perst_ctrl()
752 iproc_pcie_write_reg(pcie, IPROC_PCIE_CLK_CTRL, val); in iproc_pcie_perst_ctrl()
757 int iproc_pcie_shutdown(struct iproc_pcie *pcie) in iproc_pcie_shutdown() argument
759 iproc_pcie_perst_ctrl(pcie, true); in iproc_pcie_shutdown()
766 static int iproc_pcie_check_link(struct iproc_pcie *pcie) in iproc_pcie_check_link() argument
768 struct device *dev = pcie->dev; in iproc_pcie_check_link()
776 if (pcie->ep_is_internal) in iproc_pcie_check_link()
779 val = iproc_pcie_read_reg(pcie, IPROC_PCIE_LINK_STATUS); in iproc_pcie_check_link()
782 return -ENODEV; in iproc_pcie_check_link()
786 iproc_pci_raw_config_read32(pcie, 0, PCI_HEADER_TYPE, 1, &hdr_type); in iproc_pcie_check_link()
789 return -EFAULT; in iproc_pcie_check_link()
795 iproc_pci_raw_config_read32(pcie, 0, PCI_BRIDGE_CTRL_REG_OFFSET, in iproc_pcie_check_link()
799 iproc_pci_raw_config_write32(pcie, 0, PCI_BRIDGE_CTRL_REG_OFFSET, in iproc_pcie_check_link()
803 iproc_pci_raw_config_read32(pcie, 0, IPROC_PCI_EXP_CAP + PCI_EXP_LNKSTA, in iproc_pcie_check_link()
813 iproc_pci_raw_config_read32(pcie, 0, in iproc_pcie_check_link()
820 iproc_pci_raw_config_write32(pcie, 0, in iproc_pcie_check_link()
825 iproc_pci_raw_config_read32(pcie, 0, in iproc_pcie_check_link()
835 return link_is_active ? 0 : -ENODEV; in iproc_pcie_check_link()
838 static void iproc_pcie_enable(struct iproc_pcie *pcie) in iproc_pcie_enable() argument
840 iproc_pcie_write_reg(pcie, IPROC_PCIE_INTX_EN, SYS_RC_INTX_MASK); in iproc_pcie_enable()
843 static inline bool iproc_pcie_ob_is_valid(struct iproc_pcie *pcie, in iproc_pcie_ob_is_valid() argument
848 val = iproc_pcie_read_reg(pcie, MAP_REG(IPROC_PCIE_OARR0, window_idx)); in iproc_pcie_ob_is_valid()
853 static inline int iproc_pcie_ob_write(struct iproc_pcie *pcie, int window_idx, in iproc_pcie_ob_write() argument
856 struct device *dev = pcie->dev; in iproc_pcie_ob_write()
860 * Derive the OARR/OMAP offset from the first pair (OARR0/OMAP0) based in iproc_pcie_ob_write()
863 oarr_offset = iproc_pcie_reg_offset(pcie, MAP_REG(IPROC_PCIE_OARR0, in iproc_pcie_ob_write()
865 omap_offset = iproc_pcie_reg_offset(pcie, MAP_REG(IPROC_PCIE_OMAP0, in iproc_pcie_ob_write()
869 return -EINVAL; in iproc_pcie_ob_write()
872 * Program the OARR registers. The upper 32-bit OARR register is in iproc_pcie_ob_write()
873 * always right after the lower 32-bit OARR register. in iproc_pcie_ob_write()
876 OARR_VALID, pcie->base + oarr_offset); in iproc_pcie_ob_write()
877 writel(upper_32_bits(axi_addr), pcie->base + oarr_offset + 4); in iproc_pcie_ob_write()
880 writel(lower_32_bits(pci_addr), pcie->base + omap_offset); in iproc_pcie_ob_write()
881 writel(upper_32_bits(pci_addr), pcie->base + omap_offset + 4); in iproc_pcie_ob_write()
883 dev_dbg(dev, "ob window [%d]: offset 0x%x axi %pap pci %pap\n", in iproc_pcie_ob_write()
886 readl(pcie->base + oarr_offset), in iproc_pcie_ob_write()
887 readl(pcie->base + oarr_offset + 4)); in iproc_pcie_ob_write()
889 readl(pcie->base + omap_offset), in iproc_pcie_ob_write()
890 readl(pcie->base + omap_offset + 4)); in iproc_pcie_ob_write()
900 * iproc_pcie_address = axi_address - axi_offset
904 * axi_addr -> iproc_pcie_address -> OARR -> OMAP -> pci_address
906 static int iproc_pcie_setup_ob(struct iproc_pcie *pcie, u64 axi_addr, in iproc_pcie_setup_ob() argument
909 struct iproc_pcie_ob *ob = &pcie->ob; in iproc_pcie_setup_ob() local
910 struct device *dev = pcie->dev; in iproc_pcie_setup_ob()
911 int ret = -EINVAL, window_idx, size_idx; in iproc_pcie_setup_ob()
913 if (axi_addr < ob->axi_offset) { in iproc_pcie_setup_ob()
914 dev_err(dev, "axi address %pap less than offset %pap\n", in iproc_pcie_setup_ob()
915 &axi_addr, &ob->axi_offset); in iproc_pcie_setup_ob()
916 return -EINVAL; in iproc_pcie_setup_ob()
920 * Translate the AXI address to the internal address used by the iProc in iproc_pcie_setup_ob()
921 * PCIe core before programming the OARR in iproc_pcie_setup_ob()
923 axi_addr -= ob->axi_offset; in iproc_pcie_setup_ob()
926 for (window_idx = ob->nr_windows - 1; window_idx >= 0; window_idx--) { in iproc_pcie_setup_ob()
928 &pcie->ob_map[window_idx]; in iproc_pcie_setup_ob()
934 if (iproc_pcie_ob_is_valid(pcie, window_idx)) in iproc_pcie_setup_ob()
942 for (size_idx = ob_map->nr_sizes - 1; size_idx >= 0; in iproc_pcie_setup_ob()
943 size_idx--) { in iproc_pcie_setup_ob()
945 ob_map->window_sizes[size_idx] * SZ_1M; in iproc_pcie_setup_ob()
970 "axi %pap or pci %pap not aligned\n", in iproc_pcie_setup_ob()
972 return -EINVAL; in iproc_pcie_setup_ob()
979 ret = iproc_pcie_ob_write(pcie, window_idx, size_idx, in iproc_pcie_setup_ob()
984 size -= window_size; in iproc_pcie_setup_ob()
1002 "axi %pap, axi offset %pap, pci %pap, res size %pap\n", in iproc_pcie_setup_ob()
1003 &axi_addr, &ob->axi_offset, &pci_addr, &size); in iproc_pcie_setup_ob()
1008 static int iproc_pcie_map_ranges(struct iproc_pcie *pcie, in iproc_pcie_map_ranges() argument
1011 struct device *dev = pcie->dev; in iproc_pcie_map_ranges()
1016 struct resource *res = window->res; in iproc_pcie_map_ranges()
1024 ret = iproc_pcie_setup_ob(pcie, res->start, in iproc_pcie_map_ranges()
1025 res->start - window->offset, in iproc_pcie_map_ranges()
1032 return -EINVAL; in iproc_pcie_map_ranges()
1039 static inline bool iproc_pcie_ib_is_in_use(struct iproc_pcie *pcie, in iproc_pcie_ib_is_in_use() argument
1042 const struct iproc_pcie_ib_map *ib_map = &pcie->ib_map[region_idx]; in iproc_pcie_ib_is_in_use()
1045 val = iproc_pcie_read_reg(pcie, MAP_REG(IPROC_PCIE_IARR0, region_idx)); in iproc_pcie_ib_is_in_use()
1047 return !!(val & (BIT(ib_map->nr_sizes) - 1)); in iproc_pcie_ib_is_in_use()
1053 return !!(ib_map->type == type); in iproc_pcie_ib_check_type()
1056 static int iproc_pcie_ib_write(struct iproc_pcie *pcie, int region_idx, in iproc_pcie_ib_write() argument
1060 struct device *dev = pcie->dev; in iproc_pcie_ib_write()
1061 const struct iproc_pcie_ib_map *ib_map = &pcie->ib_map[region_idx]; in iproc_pcie_ib_write()
1066 iarr_offset = iproc_pcie_reg_offset(pcie, in iproc_pcie_ib_write()
1068 imap_offset = iproc_pcie_reg_offset(pcie, in iproc_pcie_ib_write()
1072 return -EINVAL; in iproc_pcie_ib_write()
1074 dev_dbg(dev, "ib region [%d]: offset 0x%x axi %pap pci %pap\n", in iproc_pcie_ib_write()
1078 * Program the IARR registers. The upper 32-bit IARR register is in iproc_pcie_ib_write()
1079 * always right after the lower 32-bit IARR register. in iproc_pcie_ib_write()
1082 pcie->base + iarr_offset); in iproc_pcie_ib_write()
1083 writel(upper_32_bits(pci_addr), pcie->base + iarr_offset + 4); in iproc_pcie_ib_write()
1086 readl(pcie->base + iarr_offset), in iproc_pcie_ib_write()
1087 readl(pcie->base + iarr_offset + 4)); in iproc_pcie_ib_write()
1095 val = readl(pcie->base + imap_offset); in iproc_pcie_ib_write()
1097 writel(val, pcie->base + imap_offset); in iproc_pcie_ib_write()
1099 pcie->base + imap_offset + ib_map->imap_addr_offset); in iproc_pcie_ib_write()
1102 window_idx, readl(pcie->base + imap_offset), in iproc_pcie_ib_write()
1103 readl(pcie->base + imap_offset + in iproc_pcie_ib_write()
1104 ib_map->imap_addr_offset)); in iproc_pcie_ib_write()
1106 imap_offset += ib_map->imap_window_offset; in iproc_pcie_ib_write()
1113 static int iproc_pcie_setup_ib(struct iproc_pcie *pcie, in iproc_pcie_setup_ib() argument
1117 struct device *dev = pcie->dev; in iproc_pcie_setup_ib()
1118 struct iproc_pcie_ib *ib = &pcie->ib; in iproc_pcie_setup_ib()
1121 u64 axi_addr = entry->res->start; in iproc_pcie_setup_ib()
1122 u64 pci_addr = entry->res->start - entry->offset; in iproc_pcie_setup_ib()
1123 resource_size_t size = resource_size(entry->res); in iproc_pcie_setup_ib()
1126 for (region_idx = 0; region_idx < ib->nr_regions; region_idx++) { in iproc_pcie_setup_ib()
1128 &pcie->ib_map[region_idx]; in iproc_pcie_setup_ib()
1134 if (iproc_pcie_ib_is_in_use(pcie, region_idx) || in iproc_pcie_setup_ib()
1139 for (size_idx = 0; size_idx < ib_map->nr_sizes; size_idx++) { in iproc_pcie_setup_ib()
1141 ib_map->region_sizes[size_idx] * ib_map->size_unit; in iproc_pcie_setup_ib()
1149 "axi %pap or pci %pap not aligned\n", in iproc_pcie_setup_ib()
1151 return -EINVAL; in iproc_pcie_setup_ib()
1155 ret = iproc_pcie_ib_write(pcie, region_idx, size_idx, in iproc_pcie_setup_ib()
1156 ib_map->nr_windows, axi_addr, in iproc_pcie_setup_ib()
1165 ret = -EINVAL; in iproc_pcie_setup_ib()
1169 dev_err(dev, "axi %pap, pci %pap, res size %pap\n", in iproc_pcie_setup_ib()
1175 static int iproc_pcie_map_dma_ranges(struct iproc_pcie *pcie) in iproc_pcie_map_dma_ranges() argument
1177 struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie); in iproc_pcie_map_dma_ranges()
1181 resource_list_for_each_entry(entry, &host->dma_ranges) { in iproc_pcie_map_dma_ranges()
1183 ret = iproc_pcie_setup_ib(pcie, entry, IPROC_PCIE_IB_MAP_MEM); in iproc_pcie_map_dma_ranges()
1191 static void iproc_pcie_invalidate_mapping(struct iproc_pcie *pcie) in iproc_pcie_invalidate_mapping() argument
1193 struct iproc_pcie_ib *ib = &pcie->ib; in iproc_pcie_invalidate_mapping()
1194 struct iproc_pcie_ob *ob = &pcie->ob; in iproc_pcie_invalidate_mapping() local
1197 if (pcie->ep_is_internal) in iproc_pcie_invalidate_mapping()
1200 if (pcie->need_ob_cfg) { in iproc_pcie_invalidate_mapping()
1202 for (idx = ob->nr_windows - 1; idx >= 0; idx--) { in iproc_pcie_invalidate_mapping()
1203 iproc_pcie_write_reg(pcie, in iproc_pcie_invalidate_mapping()
1208 if (pcie->need_ib_cfg) { in iproc_pcie_invalidate_mapping()
1210 for (idx = 0; idx < ib->nr_regions; idx++) { in iproc_pcie_invalidate_mapping()
1211 iproc_pcie_write_reg(pcie, in iproc_pcie_invalidate_mapping()
1217 static int iproce_pcie_get_msi(struct iproc_pcie *pcie, in iproce_pcie_get_msi() argument
1221 struct device *dev = pcie->dev; in iproce_pcie_get_msi()
1226 * Check if 'msi-map' points to ARM GICv3 ITS, which is the only in iproce_pcie_get_msi()
1229 if (!of_device_is_compatible(msi_node, "arm,gic-v3-its")) { in iproce_pcie_get_msi()
1231 return -ENODEV; in iproce_pcie_get_msi()
1245 static int iproc_pcie_paxb_v2_msi_steer(struct iproc_pcie *pcie, u64 msi_addr) in iproc_pcie_paxb_v2_msi_steer() argument
1253 msi_addr &= ~(SZ_32K - 1); in iproc_pcie_paxb_v2_msi_steer()
1254 entry.res->start = msi_addr; in iproc_pcie_paxb_v2_msi_steer()
1255 entry.res->end = msi_addr + SZ_32K - 1; in iproc_pcie_paxb_v2_msi_steer()
1257 ret = iproc_pcie_setup_ib(pcie, &entry, IPROC_PCIE_IB_MAP_IO); in iproc_pcie_paxb_v2_msi_steer()
1261 static void iproc_pcie_paxc_v2_msi_steer(struct iproc_pcie *pcie, u64 msi_addr, in iproc_pcie_paxc_v2_msi_steer() argument
1269 * treated as non-MSI transfers in iproc_pcie_paxc_v2_msi_steer()
1271 val = iproc_pcie_read_reg(pcie, IPROC_PCIE_MSI_EN_CFG); in iproc_pcie_paxc_v2_msi_steer()
1273 iproc_pcie_write_reg(pcie, IPROC_PCIE_MSI_EN_CFG, val); in iproc_pcie_paxc_v2_msi_steer()
1280 * based SoCs, all I/O register bases are well below the 32-bit in iproc_pcie_paxc_v2_msi_steer()
1283 iproc_pcie_write_reg(pcie, IPROC_PCIE_MSI_BASE_ADDR, in iproc_pcie_paxc_v2_msi_steer()
1287 iproc_pcie_write_reg(pcie, IPROC_PCIE_MSI_WINDOW_SIZE, 0); in iproc_pcie_paxc_v2_msi_steer()
1290 val = iproc_pcie_read_reg(pcie, IPROC_PCIE_MSI_GIC_MODE); in iproc_pcie_paxc_v2_msi_steer()
1292 iproc_pcie_write_reg(pcie, IPROC_PCIE_MSI_GIC_MODE, val); in iproc_pcie_paxc_v2_msi_steer()
1299 iproc_pcie_write_reg(pcie, IPROC_PCIE_MSI_ADDR_HI, in iproc_pcie_paxc_v2_msi_steer()
1301 iproc_pcie_write_reg(pcie, IPROC_PCIE_MSI_ADDR_LO, in iproc_pcie_paxc_v2_msi_steer()
1305 val = iproc_pcie_read_reg(pcie, IPROC_PCIE_MSI_EN_CFG); in iproc_pcie_paxc_v2_msi_steer()
1307 iproc_pcie_write_reg(pcie, IPROC_PCIE_MSI_EN_CFG, val); in iproc_pcie_paxc_v2_msi_steer()
1310 static int iproc_pcie_msi_steer(struct iproc_pcie *pcie, in iproc_pcie_msi_steer() argument
1313 struct device *dev = pcie->dev; in iproc_pcie_msi_steer()
1317 ret = iproce_pcie_get_msi(pcie, msi_node, &msi_addr); in iproc_pcie_msi_steer()
1323 switch (pcie->type) { in iproc_pcie_msi_steer()
1325 ret = iproc_pcie_paxb_v2_msi_steer(pcie, msi_addr); in iproc_pcie_msi_steer()
1330 iproc_pcie_paxc_v2_msi_steer(pcie, msi_addr, true); in iproc_pcie_msi_steer()
1333 return -EINVAL; in iproc_pcie_msi_steer()
1339 static int iproc_pcie_msi_enable(struct iproc_pcie *pcie) in iproc_pcie_msi_enable() argument
1345 * Either the "msi-parent" or the "msi-map" phandle needs to exist in iproc_pcie_msi_enable()
1349 msi_node = of_parse_phandle(pcie->dev->of_node, "msi-parent", 0); in iproc_pcie_msi_enable()
1355 msi_map = of_get_property(pcie->dev->of_node, "msi-map", &len); in iproc_pcie_msi_enable()
1357 return -ENODEV; in iproc_pcie_msi_enable()
1362 return -ENODEV; in iproc_pcie_msi_enable()
1366 * Certain revisions of the iProc PCIe controller require additional in iproc_pcie_msi_enable()
1370 if (pcie->need_msi_steer) { in iproc_pcie_msi_enable()
1371 ret = iproc_pcie_msi_steer(pcie, msi_node); in iproc_pcie_msi_enable()
1380 ret = iproc_msi_init(pcie, msi_node); in iproc_pcie_msi_enable()
1387 static void iproc_pcie_msi_disable(struct iproc_pcie *pcie) in iproc_pcie_msi_disable() argument
1389 iproc_msi_exit(pcie); in iproc_pcie_msi_disable()
1392 static int iproc_pcie_rev_init(struct iproc_pcie *pcie) in iproc_pcie_rev_init() argument
1394 struct device *dev = pcie->dev; in iproc_pcie_rev_init()
1398 switch (pcie->type) { in iproc_pcie_rev_init()
1404 pcie->has_apb_err_disable = true; in iproc_pcie_rev_init()
1405 if (pcie->need_ob_cfg) { in iproc_pcie_rev_init()
1406 pcie->ob_map = paxb_ob_map; in iproc_pcie_rev_init()
1407 pcie->ob.nr_windows = ARRAY_SIZE(paxb_ob_map); in iproc_pcie_rev_init()
1412 pcie->iproc_cfg_read = true; in iproc_pcie_rev_init()
1413 pcie->has_apb_err_disable = true; in iproc_pcie_rev_init()
1414 if (pcie->need_ob_cfg) { in iproc_pcie_rev_init()
1415 pcie->ob_map = paxb_v2_ob_map; in iproc_pcie_rev_init()
1416 pcie->ob.nr_windows = ARRAY_SIZE(paxb_v2_ob_map); in iproc_pcie_rev_init()
1418 pcie->ib.nr_regions = ARRAY_SIZE(paxb_v2_ib_map); in iproc_pcie_rev_init()
1419 pcie->ib_map = paxb_v2_ib_map; in iproc_pcie_rev_init()
1420 pcie->need_msi_steer = true; in iproc_pcie_rev_init()
1426 pcie->ep_is_internal = true; in iproc_pcie_rev_init()
1427 pcie->iproc_cfg_read = true; in iproc_pcie_rev_init()
1428 pcie->rej_unconfig_pf = true; in iproc_pcie_rev_init()
1432 pcie->ep_is_internal = true; in iproc_pcie_rev_init()
1433 pcie->iproc_cfg_read = true; in iproc_pcie_rev_init()
1434 pcie->rej_unconfig_pf = true; in iproc_pcie_rev_init()
1435 pcie->need_msi_steer = true; in iproc_pcie_rev_init()
1438 dev_err(dev, "incompatible iProc PCIe interface\n"); in iproc_pcie_rev_init()
1439 return -EINVAL; in iproc_pcie_rev_init()
1442 pcie->reg_offsets = devm_kcalloc(dev, IPROC_PCIE_MAX_NUM_REG, in iproc_pcie_rev_init()
1443 sizeof(*pcie->reg_offsets), in iproc_pcie_rev_init()
1445 if (!pcie->reg_offsets) in iproc_pcie_rev_init()
1446 return -ENOMEM; in iproc_pcie_rev_init()
1449 pcie->reg_offsets[0] = (pcie->type == IPROC_PCIE_PAXC_V2) ? in iproc_pcie_rev_init()
1452 pcie->reg_offsets[reg_idx] = regs[reg_idx] ? in iproc_pcie_rev_init()
1458 int iproc_pcie_setup(struct iproc_pcie *pcie, struct list_head *res) in iproc_pcie_setup() argument
1463 struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie); in iproc_pcie_setup()
1465 dev = pcie->dev; in iproc_pcie_setup()
1467 ret = iproc_pcie_rev_init(pcie); in iproc_pcie_setup()
1473 ret = phy_init(pcie->phy); in iproc_pcie_setup()
1475 dev_err(dev, "unable to initialize PCIe PHY\n"); in iproc_pcie_setup()
1479 ret = phy_power_on(pcie->phy); in iproc_pcie_setup()
1481 dev_err(dev, "unable to power on PCIe PHY\n"); in iproc_pcie_setup()
1485 iproc_pcie_perst_ctrl(pcie, true); in iproc_pcie_setup()
1486 iproc_pcie_perst_ctrl(pcie, false); in iproc_pcie_setup()
1488 iproc_pcie_invalidate_mapping(pcie); in iproc_pcie_setup()
1490 if (pcie->need_ob_cfg) { in iproc_pcie_setup()
1491 ret = iproc_pcie_map_ranges(pcie, res); in iproc_pcie_setup()
1498 if (pcie->need_ib_cfg) { in iproc_pcie_setup()
1499 ret = iproc_pcie_map_dma_ranges(pcie); in iproc_pcie_setup()
1500 if (ret && ret != -ENOENT) in iproc_pcie_setup()
1504 ret = iproc_pcie_check_link(pcie); in iproc_pcie_setup()
1506 dev_err(dev, "no PCIe EP device detected\n"); in iproc_pcie_setup()
1510 iproc_pcie_enable(pcie); in iproc_pcie_setup()
1513 if (iproc_pcie_msi_enable(pcie)) in iproc_pcie_setup()
1516 host->ops = &iproc_pcie_ops; in iproc_pcie_setup()
1517 host->sysdata = pcie; in iproc_pcie_setup()
1518 host->map_irq = pcie->map_irq; in iproc_pcie_setup()
1526 for_each_pci_bridge(pdev, host->bus) { in iproc_pcie_setup()
1534 phy_power_off(pcie->phy); in iproc_pcie_setup()
1536 phy_exit(pcie->phy); in iproc_pcie_setup()
1541 int iproc_pcie_remove(struct iproc_pcie *pcie) in iproc_pcie_remove() argument
1543 struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie); in iproc_pcie_remove()
1545 pci_stop_root_bus(host->bus); in iproc_pcie_remove()
1546 pci_remove_root_bus(host->bus); in iproc_pcie_remove()
1548 iproc_pcie_msi_disable(pcie); in iproc_pcie_remove()
1550 phy_power_off(pcie->phy); in iproc_pcie_remove()
1551 phy_exit(pcie->phy); in iproc_pcie_remove()
1563 struct iproc_pcie *pcie = iproc_data(pdev->bus); in quirk_paxc_disable_msi_parsing() local
1565 if (pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE) in quirk_paxc_disable_msi_parsing()
1566 iproc_pcie_paxc_v2_msi_steer(pcie, 0, false); in quirk_paxc_disable_msi_parsing()
1582 if (pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE) in quirk_paxc_bridge()
1583 pdev->class = PCI_CLASS_BRIDGE_PCI_NORMAL; in quirk_paxc_bridge()
1591 pdev->pcie_mpss = 2; in quirk_paxc_bridge()
1600 MODULE_DESCRIPTION("Broadcom iPROC PCIe common driver");