Lines Matching +full:iproc +full:- +full:pcie
1 // SPDX-License-Identifier: GPL-2.0
14 #include "pcie-iproc.h"
52 * struct iproc_msi_grp - iProc MSI group
54 * One MSI group is allocated per GIC interrupt, serviced by one iProc MSI
57 * @msi: pointer to iProc MSI data
68 * struct iproc_msi - iProc event queue based MSI
73 * @pcie: pointer to iProc PCIe data
94 struct iproc_pcie *pcie; member
132 struct iproc_pcie *pcie = msi->pcie; in iproc_msi_read_reg() local
134 return readl_relaxed(pcie->base + msi->reg_offsets[eq][reg]); in iproc_msi_read_reg()
141 struct iproc_pcie *pcie = msi->pcie; in iproc_msi_write_reg() local
143 writel_relaxed(val, pcie->base + msi->reg_offsets[eq][reg]); in iproc_msi_write_reg()
148 return (hwirq % msi->nr_irqs); in hwirq_to_group()
154 if (msi->nr_msi_region > 1) in iproc_msi_addr_offset()
162 if (msi->nr_eq_region > 1) in iproc_msi_eq_offset()
169 .name = "iProc-MSI",
179 * In iProc PCIe core, each MSI group is serviced by a GIC interrupt and a
182 * The number of MSI groups varies between different iProc SoCs. The total
188 * - the number of MSI groups is M
189 * - the number of CPU cores is N
190 * - M is always a multiple of N
197 return (hwirq % msi->nr_cpus); in hwirq_to_cpu()
203 return (hwirq - hwirq_to_cpu(msi, hwirq)); in hwirq_to_canonical_hwirq()
214 curr_cpu = hwirq_to_cpu(msi, data->hwirq); in iproc_msi_irq_set_affinity()
219 data->hwirq = hwirq_to_canonical_hwirq(msi, data->hwirq) + target_cpu; in iproc_msi_irq_set_affinity()
234 addr = msi->msi_addr + iproc_msi_addr_offset(msi, data->hwirq); in iproc_msi_irq_compose_msi_msg()
235 msg->address_lo = lower_32_bits(addr); in iproc_msi_irq_compose_msi_msg()
236 msg->address_hi = upper_32_bits(addr); in iproc_msi_irq_compose_msi_msg()
237 msg->data = data->hwirq << 5; in iproc_msi_irq_compose_msi_msg()
250 struct iproc_msi *msi = domain->host_data; in iproc_msi_irq_domain_alloc()
253 if (msi->nr_cpus > 1 && nr_irqs > 1) in iproc_msi_irq_domain_alloc()
254 return -EINVAL; in iproc_msi_irq_domain_alloc()
256 mutex_lock(&msi->bitmap_lock); in iproc_msi_irq_domain_alloc()
262 hwirq = bitmap_find_free_region(msi->bitmap, msi->nr_msi_vecs, in iproc_msi_irq_domain_alloc()
263 order_base_2(msi->nr_cpus * nr_irqs)); in iproc_msi_irq_domain_alloc()
265 mutex_unlock(&msi->bitmap_lock); in iproc_msi_irq_domain_alloc()
268 return -ENOSPC; in iproc_msi_irq_domain_alloc()
273 domain->host_data, handle_simple_irq, in iproc_msi_irq_domain_alloc()
287 mutex_lock(&msi->bitmap_lock); in iproc_msi_irq_domain_free()
289 hwirq = hwirq_to_canonical_hwirq(msi, data->hwirq); in iproc_msi_irq_domain_free()
290 bitmap_release_region(msi->bitmap, hwirq, in iproc_msi_irq_domain_free()
291 order_base_2(msi->nr_cpus * nr_irqs)); in iproc_msi_irq_domain_free()
293 mutex_unlock(&msi->bitmap_lock); in iproc_msi_irq_domain_free()
310 msg = (u32 __iomem *)(msi->eq_cpu + offs); in decode_msi_hwirq()
333 msi = grp->msi; in iproc_msi_handler()
334 eq = grp->eq; in iproc_msi_handler()
337 * iProc MSI event queue is tracked by head and tail pointers. Head in iproc_msi_handler()
339 * the queue and needs to be updated by SW. iProc MSI core uses the in iproc_msi_handler()
344 * pointer is updated by the iProc MSI core. in iproc_msi_handler()
357 (EQ_LEN - (head - tail)) : (tail - head); in iproc_msi_handler()
362 while (nr_events--) { in iproc_msi_handler()
364 generic_handle_domain_irq(msi->inner_domain, hwirq); in iproc_msi_handler()
391 for (i = 0; i < msi->nr_eq_region; i++) { in iproc_msi_enable()
392 dma_addr_t addr = msi->eq_dma + (i * EQ_MEM_REGION_SIZE); in iproc_msi_enable()
401 for (i = 0; i < msi->nr_msi_region; i++) { in iproc_msi_enable()
402 phys_addr_t addr = msi->msi_addr + (i * MSI_MEM_REGION_SIZE); in iproc_msi_enable()
410 for (eq = 0; eq < msi->nr_irqs; eq++) { in iproc_msi_enable()
420 if (msi->has_inten_reg) { in iproc_msi_enable()
432 for (eq = 0; eq < msi->nr_irqs; eq++) { in iproc_msi_disable()
433 if (msi->has_inten_reg) { in iproc_msi_disable()
449 msi->inner_domain = irq_domain_add_linear(NULL, msi->nr_msi_vecs, in iproc_msi_alloc_domains()
451 if (!msi->inner_domain) in iproc_msi_alloc_domains()
452 return -ENOMEM; in iproc_msi_alloc_domains()
454 msi->msi_domain = pci_msi_create_irq_domain(of_node_to_fwnode(node), in iproc_msi_alloc_domains()
456 msi->inner_domain); in iproc_msi_alloc_domains()
457 if (!msi->msi_domain) { in iproc_msi_alloc_domains()
458 irq_domain_remove(msi->inner_domain); in iproc_msi_alloc_domains()
459 return -ENOMEM; in iproc_msi_alloc_domains()
467 if (msi->msi_domain) in iproc_msi_free_domains()
468 irq_domain_remove(msi->msi_domain); in iproc_msi_free_domains()
470 if (msi->inner_domain) in iproc_msi_free_domains()
471 irq_domain_remove(msi->inner_domain); in iproc_msi_free_domains()
478 for (i = cpu; i < msi->nr_irqs; i += msi->nr_cpus) { in iproc_msi_irq_free()
479 irq_set_chained_handler_and_data(msi->grps[i].gic_irq, in iproc_msi_irq_free()
488 struct iproc_pcie *pcie = msi->pcie; in iproc_msi_irq_setup() local
490 for (i = cpu; i < msi->nr_irqs; i += msi->nr_cpus) { in iproc_msi_irq_setup()
491 irq_set_chained_handler_and_data(msi->grps[i].gic_irq, in iproc_msi_irq_setup()
493 &msi->grps[i]); in iproc_msi_irq_setup()
498 ret = irq_set_affinity(msi->grps[i].gic_irq, mask); in iproc_msi_irq_setup()
500 dev_err(pcie->dev, in iproc_msi_irq_setup()
502 msi->grps[i].gic_irq); in iproc_msi_irq_setup()
505 dev_err(pcie->dev, "failed to alloc CPU mask\n"); in iproc_msi_irq_setup()
506 ret = -EINVAL; in iproc_msi_irq_setup()
519 int iproc_msi_init(struct iproc_pcie *pcie, struct device_node *node) in iproc_msi_init() argument
525 if (!of_device_is_compatible(node, "brcm,iproc-msi")) in iproc_msi_init()
526 return -ENODEV; in iproc_msi_init()
528 if (!of_find_property(node, "msi-controller", NULL)) in iproc_msi_init()
529 return -ENODEV; in iproc_msi_init()
531 if (pcie->msi) in iproc_msi_init()
532 return -EBUSY; in iproc_msi_init()
534 msi = devm_kzalloc(pcie->dev, sizeof(*msi), GFP_KERNEL); in iproc_msi_init()
536 return -ENOMEM; in iproc_msi_init()
538 msi->pcie = pcie; in iproc_msi_init()
539 pcie->msi = msi; in iproc_msi_init()
540 msi->msi_addr = pcie->base_addr; in iproc_msi_init()
541 mutex_init(&msi->bitmap_lock); in iproc_msi_init()
542 msi->nr_cpus = num_possible_cpus(); in iproc_msi_init()
544 if (msi->nr_cpus == 1) in iproc_msi_init()
547 msi->nr_irqs = of_irq_count(node); in iproc_msi_init()
548 if (!msi->nr_irqs) { in iproc_msi_init()
549 dev_err(pcie->dev, "found no MSI GIC interrupt\n"); in iproc_msi_init()
550 return -ENODEV; in iproc_msi_init()
553 if (msi->nr_irqs > NR_HW_IRQS) { in iproc_msi_init()
554 dev_warn(pcie->dev, "too many MSI GIC interrupts defined %d\n", in iproc_msi_init()
555 msi->nr_irqs); in iproc_msi_init()
556 msi->nr_irqs = NR_HW_IRQS; in iproc_msi_init()
559 if (msi->nr_irqs < msi->nr_cpus) { in iproc_msi_init()
560 dev_err(pcie->dev, in iproc_msi_init()
562 return -EINVAL; in iproc_msi_init()
565 if (msi->nr_irqs % msi->nr_cpus != 0) { in iproc_msi_init()
566 msi->nr_irqs -= msi->nr_irqs % msi->nr_cpus; in iproc_msi_init()
567 dev_warn(pcie->dev, "Reducing number of interrupts to %d\n", in iproc_msi_init()
568 msi->nr_irqs); in iproc_msi_init()
571 switch (pcie->type) { in iproc_msi_init()
574 msi->reg_offsets = iproc_msi_reg_paxb; in iproc_msi_init()
575 msi->nr_eq_region = 1; in iproc_msi_init()
576 msi->nr_msi_region = 1; in iproc_msi_init()
579 msi->reg_offsets = iproc_msi_reg_paxc; in iproc_msi_init()
580 msi->nr_eq_region = msi->nr_irqs; in iproc_msi_init()
581 msi->nr_msi_region = msi->nr_irqs; in iproc_msi_init()
584 dev_err(pcie->dev, "incompatible iProc PCIe interface\n"); in iproc_msi_init()
585 return -EINVAL; in iproc_msi_init()
588 if (of_find_property(node, "brcm,pcie-msi-inten", NULL)) in iproc_msi_init()
589 msi->has_inten_reg = true; in iproc_msi_init()
591 msi->nr_msi_vecs = msi->nr_irqs * EQ_LEN; in iproc_msi_init()
592 msi->bitmap = devm_bitmap_zalloc(pcie->dev, msi->nr_msi_vecs, in iproc_msi_init()
594 if (!msi->bitmap) in iproc_msi_init()
595 return -ENOMEM; in iproc_msi_init()
597 msi->grps = devm_kcalloc(pcie->dev, msi->nr_irqs, sizeof(*msi->grps), in iproc_msi_init()
599 if (!msi->grps) in iproc_msi_init()
600 return -ENOMEM; in iproc_msi_init()
602 for (i = 0; i < msi->nr_irqs; i++) { in iproc_msi_init()
606 dev_err(pcie->dev, "unable to parse/map interrupt\n"); in iproc_msi_init()
607 ret = -ENODEV; in iproc_msi_init()
610 msi->grps[i].gic_irq = irq; in iproc_msi_init()
611 msi->grps[i].msi = msi; in iproc_msi_init()
612 msi->grps[i].eq = i; in iproc_msi_init()
616 msi->eq_cpu = dma_alloc_coherent(pcie->dev, in iproc_msi_init()
617 msi->nr_eq_region * EQ_MEM_REGION_SIZE, in iproc_msi_init()
618 &msi->eq_dma, GFP_KERNEL); in iproc_msi_init()
619 if (!msi->eq_cpu) { in iproc_msi_init()
620 ret = -ENOMEM; in iproc_msi_init()
626 dev_err(pcie->dev, "failed to create MSI domains\n"); in iproc_msi_init()
646 dma_free_coherent(pcie->dev, msi->nr_eq_region * EQ_MEM_REGION_SIZE, in iproc_msi_init()
647 msi->eq_cpu, msi->eq_dma); in iproc_msi_init()
650 for (i = 0; i < msi->nr_irqs; i++) { in iproc_msi_init()
651 if (msi->grps[i].gic_irq) in iproc_msi_init()
652 irq_dispose_mapping(msi->grps[i].gic_irq); in iproc_msi_init()
654 pcie->msi = NULL; in iproc_msi_init()
659 void iproc_msi_exit(struct iproc_pcie *pcie) in iproc_msi_exit() argument
661 struct iproc_msi *msi = pcie->msi; in iproc_msi_exit()
674 dma_free_coherent(pcie->dev, msi->nr_eq_region * EQ_MEM_REGION_SIZE, in iproc_msi_exit()
675 msi->eq_cpu, msi->eq_dma); in iproc_msi_exit()
677 for (i = 0; i < msi->nr_irqs; i++) { in iproc_msi_exit()
678 if (msi->grps[i].gic_irq) in iproc_msi_exit()
679 irq_dispose_mapping(msi->grps[i].gic_irq); in iproc_msi_exit()