Lines Matching full:pcie
39 /* Broadcom STB PCIe Register Offsets */
144 /* PCIe parameters */
178 #define IDX_ADDR(pcie) (pcie->reg_offsets[EXT_CFG_INDEX]) argument
179 #define DATA_ADDR(pcie) (pcie->reg_offsets[EXT_CFG_DATA]) argument
180 #define PCIE_RGR1_SW_INIT_1(pcie) (pcie->reg_offsets[RGR1_SW_INIT_1]) argument
218 void (*perst_set)(struct brcm_pcie *pcie, u32 val);
219 void (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val);
245 /* Internal PCIe Host Controller Information.*/
262 void (*perst_set)(struct brcm_pcie *pcie, u32 val);
263 void (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val);
268 static inline bool is_bmips(const struct brcm_pcie *pcie) in is_bmips() argument
270 return pcie->type == BCM7435 || pcie->type == BCM7425; in is_bmips()
347 static int brcm_pcie_set_ssc(struct brcm_pcie *pcie) in brcm_pcie_set_ssc() argument
353 ret = brcm_pcie_mdio_write(pcie->base, MDIO_PORT0, SET_ADDR_OFFSET, in brcm_pcie_set_ssc()
358 ret = brcm_pcie_mdio_read(pcie->base, MDIO_PORT0, in brcm_pcie_set_ssc()
365 ret = brcm_pcie_mdio_write(pcie->base, MDIO_PORT0, in brcm_pcie_set_ssc()
371 ret = brcm_pcie_mdio_read(pcie->base, MDIO_PORT0, in brcm_pcie_set_ssc()
383 static void brcm_pcie_set_gen(struct brcm_pcie *pcie, int gen) in brcm_pcie_set_gen() argument
385 u16 lnkctl2 = readw(pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2); in brcm_pcie_set_gen()
386 u32 lnkcap = readl(pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCAP); in brcm_pcie_set_gen()
389 writel(lnkcap, pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCAP); in brcm_pcie_set_gen()
392 writew(lnkctl2, pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2); in brcm_pcie_set_gen()
395 static void brcm_pcie_set_outbound_win(struct brcm_pcie *pcie, in brcm_pcie_set_outbound_win() argument
405 writel(lower_32_bits(pcie_addr), pcie->base + PCIE_MEM_WIN0_LO(win)); in brcm_pcie_set_outbound_win()
406 writel(upper_32_bits(pcie_addr), pcie->base + PCIE_MEM_WIN0_HI(win)); in brcm_pcie_set_outbound_win()
412 tmp = readl(pcie->base + PCIE_MEM_WIN0_BASE_LIMIT(win)); in brcm_pcie_set_outbound_win()
417 writel(tmp, pcie->base + PCIE_MEM_WIN0_BASE_LIMIT(win)); in brcm_pcie_set_outbound_win()
419 if (is_bmips(pcie)) in brcm_pcie_set_outbound_win()
427 tmp = readl(pcie->base + PCIE_MEM_WIN0_BASE_HI(win)); in brcm_pcie_set_outbound_win()
430 writel(tmp, pcie->base + PCIE_MEM_WIN0_BASE_HI(win)); in brcm_pcie_set_outbound_win()
433 tmp = readl(pcie->base + PCIE_MEM_WIN0_LIMIT_HI(win)); in brcm_pcie_set_outbound_win()
436 writel(tmp, pcie->base + PCIE_MEM_WIN0_LIMIT_HI(win)); in brcm_pcie_set_outbound_win()
440 .name = "BRCM STB PCIe MSI",
586 static void brcm_msi_remove(struct brcm_pcie *pcie) in brcm_msi_remove() argument
588 struct brcm_msi *msi = pcie->msi; in brcm_msi_remove()
617 static int brcm_pcie_enable_msi(struct brcm_pcie *pcie) in brcm_pcie_enable_msi() argument
621 struct device *dev = pcie->dev; in brcm_pcie_enable_msi()
635 msi->base = pcie->base; in brcm_pcie_enable_msi()
636 msi->np = pcie->np; in brcm_pcie_enable_msi()
637 msi->target_addr = pcie->msi_target_addr; in brcm_pcie_enable_msi()
639 msi->legacy = pcie->hw_rev < BRCM_PCIE_HW_REV_33; in brcm_pcie_enable_msi()
664 pcie->msi = msi; in brcm_pcie_enable_msi()
670 static bool brcm_pcie_rc_mode(struct brcm_pcie *pcie) in brcm_pcie_rc_mode() argument
672 void __iomem *base = pcie->base; in brcm_pcie_rc_mode()
678 static bool brcm_pcie_link_up(struct brcm_pcie *pcie) in brcm_pcie_link_up() argument
680 u32 val = readl(pcie->base + PCIE_MISC_PCIE_STATUS); in brcm_pcie_link_up()
690 struct brcm_pcie *pcie = bus->sysdata; in brcm_pcie_map_bus() local
691 void __iomem *base = pcie->base; in brcm_pcie_map_bus()
699 if (!brcm_pcie_link_up(pcie)) in brcm_pcie_map_bus()
704 writel(idx, pcie->base + PCIE_EXT_CFG_INDEX); in brcm_pcie_map_bus()
711 struct brcm_pcie *pcie = bus->sysdata; in brcm7425_pcie_map_bus() local
712 void __iomem *base = pcie->base; in brcm7425_pcie_map_bus()
720 if (!brcm_pcie_link_up(pcie)) in brcm7425_pcie_map_bus()
725 writel(idx, base + IDX_ADDR(pcie)); in brcm7425_pcie_map_bus()
726 return base + DATA_ADDR(pcie); in brcm7425_pcie_map_bus()
729 static inline void brcm_pcie_bridge_sw_init_set_generic(struct brcm_pcie *pcie, u32 val) in brcm_pcie_bridge_sw_init_set_generic() argument
734 tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); in brcm_pcie_bridge_sw_init_set_generic()
736 writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); in brcm_pcie_bridge_sw_init_set_generic()
739 static inline void brcm_pcie_bridge_sw_init_set_7278(struct brcm_pcie *pcie, u32 val) in brcm_pcie_bridge_sw_init_set_7278() argument
744 tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); in brcm_pcie_bridge_sw_init_set_7278()
746 writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); in brcm_pcie_bridge_sw_init_set_7278()
749 static inline void brcm_pcie_perst_set_4908(struct brcm_pcie *pcie, u32 val) in brcm_pcie_perst_set_4908() argument
751 if (WARN_ONCE(!pcie->perst_reset, "missing PERST# reset controller\n")) in brcm_pcie_perst_set_4908()
755 reset_control_assert(pcie->perst_reset); in brcm_pcie_perst_set_4908()
757 reset_control_deassert(pcie->perst_reset); in brcm_pcie_perst_set_4908()
760 static inline void brcm_pcie_perst_set_7278(struct brcm_pcie *pcie, u32 val) in brcm_pcie_perst_set_7278() argument
765 tmp = readl(pcie->base + PCIE_MISC_PCIE_CTRL); in brcm_pcie_perst_set_7278()
767 writel(tmp, pcie->base + PCIE_MISC_PCIE_CTRL); in brcm_pcie_perst_set_7278()
770 static inline void brcm_pcie_perst_set_generic(struct brcm_pcie *pcie, u32 val) in brcm_pcie_perst_set_generic() argument
774 tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); in brcm_pcie_perst_set_generic()
776 writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); in brcm_pcie_perst_set_generic()
779 static inline int brcm_pcie_get_rc_bar2_size_and_offset(struct brcm_pcie *pcie, in brcm_pcie_get_rc_bar2_size_and_offset() argument
783 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie); in brcm_pcie_get_rc_bar2_size_and_offset()
785 struct device *dev = pcie->dev; in brcm_pcie_get_rc_bar2_size_and_offset()
803 ret = of_property_read_variable_u64_array(pcie->np, "brcm,scb-sizes", pcie->memc_size, 1, in brcm_pcie_get_rc_bar2_size_and_offset()
808 pcie->num_memc = 1; in brcm_pcie_get_rc_bar2_size_and_offset()
809 pcie->memc_size[0] = 1ULL << fls64(size - 1); in brcm_pcie_get_rc_bar2_size_and_offset()
811 pcie->num_memc = ret; in brcm_pcie_get_rc_bar2_size_and_offset()
815 for (i = 0, size = 0; i < pcie->num_memc; i++) in brcm_pcie_get_rc_bar2_size_and_offset()
816 size += pcie->memc_size[i]; in brcm_pcie_get_rc_bar2_size_and_offset()
818 /* System memory starts at this address in PCIe-space */ in brcm_pcie_get_rc_bar2_size_and_offset()
828 * PCIe controller integration, which prohibits any access above the in brcm_pcie_get_rc_bar2_size_and_offset()
833 * The PCIe host controller by design must set the inbound viewport to in brcm_pcie_get_rc_bar2_size_and_offset()
836 * matters, the viewport must start on a pcie-address that is aligned in brcm_pcie_get_rc_bar2_size_and_offset()
847 * region in the first 4GB of pcie-space, as some legacy devices can in brcm_pcie_get_rc_bar2_size_and_offset()
866 static int brcm_pcie_setup(struct brcm_pcie *pcie) in brcm_pcie_setup() argument
869 void __iomem *base = pcie->base; in brcm_pcie_setup()
877 pcie->bridge_sw_init_set(pcie, 1); in brcm_pcie_setup()
881 pcie->bridge_sw_init_set(pcie, 0); in brcm_pcie_setup()
884 if (is_bmips(pcie)) in brcm_pcie_setup()
897 if (is_bmips(pcie)) in brcm_pcie_setup()
899 else if (pcie->type == BCM2711) in brcm_pcie_setup()
901 else if (pcie->type == BCM7278) in brcm_pcie_setup()
913 ret = brcm_pcie_get_rc_bar2_size_and_offset(pcie, &rc_bar2_size, in brcm_pcie_setup()
926 for (memc = 0; memc < pcie->num_memc; memc++) { in brcm_pcie_setup()
927 u32 scb_size_val = ilog2(pcie->memc_size[memc]) - 15; in brcm_pcie_setup()
946 pcie->msi_target_addr = BRCM_MSI_TARGET_ADDR_LT_4GB; in brcm_pcie_setup()
948 pcie->msi_target_addr = BRCM_MSI_TARGET_ADDR_GT_4GB; in brcm_pcie_setup()
950 if (!brcm_pcie_rc_mode(pcie)) { in brcm_pcie_setup()
951 dev_err(pcie->dev, "PCIe RC controller misconfigured as Endpoint\n"); in brcm_pcie_setup()
955 /* disable the PCIe->GISB memory window (RC_BAR1) */ in brcm_pcie_setup()
960 /* disable the PCIe->SCB memory window (RC_BAR3) */ in brcm_pcie_setup()
967 if (!of_property_read_bool(pcie->np, "aspm-no-l0s")) in brcm_pcie_setup()
976 * a PCIe-PCIe bridge (the default setting is to be EP mode). in brcm_pcie_setup()
983 bridge = pci_host_bridge_from_priv(pcie); in brcm_pcie_setup()
991 dev_err(pcie->dev, "too many outbound wins\n"); in brcm_pcie_setup()
995 if (is_bmips(pcie)) { in brcm_pcie_setup()
999 /* bmips PCIe outbound windows have a 128MB max size */ in brcm_pcie_setup()
1003 brcm_pcie_set_outbound_win(pcie, j, start, in brcm_pcie_setup()
1008 brcm_pcie_set_outbound_win(pcie, num_out_wins, res->start, in brcm_pcie_setup()
1014 /* PCIe->SCB endian mode for BAR */ in brcm_pcie_setup()
1023 static int brcm_pcie_start_link(struct brcm_pcie *pcie) in brcm_pcie_start_link() argument
1025 struct device *dev = pcie->dev; in brcm_pcie_start_link()
1026 void __iomem *base = pcie->base; in brcm_pcie_start_link()
1033 pcie->perst_set(pcie, 0); in brcm_pcie_start_link()
1039 for (i = 0; i < 100 && !brcm_pcie_link_up(pcie); i += 5) in brcm_pcie_start_link()
1042 if (!brcm_pcie_link_up(pcie)) { in brcm_pcie_start_link()
1047 if (pcie->gen) in brcm_pcie_start_link()
1048 brcm_pcie_set_gen(pcie, pcie->gen); in brcm_pcie_start_link()
1050 if (pcie->ssc) { in brcm_pcie_start_link()
1051 ret = brcm_pcie_set_ssc(pcie); in brcm_pcie_start_link()
1101 struct brcm_pcie *pcie = bus->sysdata; in brcm_pcie_add_bus() local
1116 pcie->sr = sr; in brcm_pcie_add_bus()
1128 pcie->sr = NULL; in brcm_pcie_add_bus()
1133 brcm_pcie_start_link(pcie); in brcm_pcie_add_bus()
1139 struct brcm_pcie *pcie = bus->sysdata; in brcm_pcie_remove_bus() local
1140 struct subdev_regulators *sr = pcie->sr; in brcm_pcie_remove_bus()
1149 pcie->sr = NULL; in brcm_pcie_remove_bus()
1152 /* L23 is a low-power PCIe link state */
1153 static void brcm_pcie_enter_l23(struct brcm_pcie *pcie) in brcm_pcie_enter_l23() argument
1155 void __iomem *base = pcie->base; in brcm_pcie_enter_l23()
1175 dev_err(pcie->dev, "failed to enter low-power link state\n"); in brcm_pcie_enter_l23()
1178 static int brcm_phy_cntl(struct brcm_pcie *pcie, const int start) in brcm_phy_cntl() argument
1192 void __iomem *base = pcie->base; in brcm_phy_cntl()
1209 dev_err(pcie->dev, "failed to %s phy\n", (start ? "start" : "stop")); in brcm_phy_cntl()
1214 static inline int brcm_phy_start(struct brcm_pcie *pcie) in brcm_phy_start() argument
1216 return pcie->rescal ? brcm_phy_cntl(pcie, 1) : 0; in brcm_phy_start()
1219 static inline int brcm_phy_stop(struct brcm_pcie *pcie) in brcm_phy_stop() argument
1221 return pcie->rescal ? brcm_phy_cntl(pcie, 0) : 0; in brcm_phy_stop()
1224 static void brcm_pcie_turn_off(struct brcm_pcie *pcie) in brcm_pcie_turn_off() argument
1226 void __iomem *base = pcie->base; in brcm_pcie_turn_off()
1229 if (brcm_pcie_link_up(pcie)) in brcm_pcie_turn_off()
1230 brcm_pcie_enter_l23(pcie); in brcm_pcie_turn_off()
1232 pcie->perst_set(pcie, 1); in brcm_pcie_turn_off()
1244 /* Shutdown PCIe bridge */ in brcm_pcie_turn_off()
1245 pcie->bridge_sw_init_set(pcie, 1); in brcm_pcie_turn_off()
1261 struct brcm_pcie *pcie = dev_get_drvdata(dev); in brcm_pcie_suspend_noirq() local
1262 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie); in brcm_pcie_suspend_noirq()
1265 brcm_pcie_turn_off(pcie); in brcm_pcie_suspend_noirq()
1271 if (brcm_phy_stop(pcie)) in brcm_pcie_suspend_noirq()
1274 ret = reset_control_rearm(pcie->rescal); in brcm_pcie_suspend_noirq()
1280 if (pcie->sr) { in brcm_pcie_suspend_noirq()
1286 pcie->ep_wakeup_capable = false; in brcm_pcie_suspend_noirq()
1288 &pcie->ep_wakeup_capable); in brcm_pcie_suspend_noirq()
1289 if (!pcie->ep_wakeup_capable) { in brcm_pcie_suspend_noirq()
1290 ret = regulator_bulk_disable(pcie->sr->num_supplies, in brcm_pcie_suspend_noirq()
1291 pcie->sr->supplies); in brcm_pcie_suspend_noirq()
1294 reset_control_reset(pcie->rescal); in brcm_pcie_suspend_noirq()
1299 clk_disable_unprepare(pcie->clk); in brcm_pcie_suspend_noirq()
1306 struct brcm_pcie *pcie = dev_get_drvdata(dev); in brcm_pcie_resume_noirq() local
1311 base = pcie->base; in brcm_pcie_resume_noirq()
1312 ret = clk_prepare_enable(pcie->clk); in brcm_pcie_resume_noirq()
1316 ret = reset_control_reset(pcie->rescal); in brcm_pcie_resume_noirq()
1320 ret = brcm_phy_start(pcie); in brcm_pcie_resume_noirq()
1325 pcie->bridge_sw_init_set(pcie, 0); in brcm_pcie_resume_noirq()
1335 ret = brcm_pcie_setup(pcie); in brcm_pcie_resume_noirq()
1339 if (pcie->sr) { in brcm_pcie_resume_noirq()
1340 if (pcie->ep_wakeup_capable) { in brcm_pcie_resume_noirq()
1347 pcie->ep_wakeup_capable = false; in brcm_pcie_resume_noirq()
1349 ret = regulator_bulk_enable(pcie->sr->num_supplies, in brcm_pcie_resume_noirq()
1350 pcie->sr->supplies); in brcm_pcie_resume_noirq()
1358 ret = brcm_pcie_start_link(pcie); in brcm_pcie_resume_noirq()
1362 if (pcie->msi) in brcm_pcie_resume_noirq()
1363 brcm_msi_set_regs(pcie->msi); in brcm_pcie_resume_noirq()
1368 if (pcie->sr) in brcm_pcie_resume_noirq()
1369 regulator_bulk_disable(pcie->sr->num_supplies, pcie->sr->supplies); in brcm_pcie_resume_noirq()
1371 reset_control_rearm(pcie->rescal); in brcm_pcie_resume_noirq()
1373 clk_disable_unprepare(pcie->clk); in brcm_pcie_resume_noirq()
1377 static void __brcm_pcie_remove(struct brcm_pcie *pcie) in __brcm_pcie_remove() argument
1379 brcm_msi_remove(pcie); in __brcm_pcie_remove()
1380 brcm_pcie_turn_off(pcie); in __brcm_pcie_remove()
1381 if (brcm_phy_stop(pcie)) in __brcm_pcie_remove()
1382 dev_err(pcie->dev, "Could not stop phy\n"); in __brcm_pcie_remove()
1383 if (reset_control_rearm(pcie->rescal)) in __brcm_pcie_remove()
1384 dev_err(pcie->dev, "Could not rearm rescal reset\n"); in __brcm_pcie_remove()
1385 clk_disable_unprepare(pcie->clk); in __brcm_pcie_remove()
1390 struct brcm_pcie *pcie = platform_get_drvdata(pdev); in brcm_pcie_remove() local
1391 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie); in brcm_pcie_remove()
1395 __brcm_pcie_remove(pcie); in brcm_pcie_remove()
1461 { .compatible = "brcm,bcm2711-pcie", .data = &bcm2711_cfg },
1462 { .compatible = "brcm,bcm4908-pcie", .data = &bcm4908_cfg },
1463 { .compatible = "brcm,bcm7211-pcie", .data = &generic_cfg },
1464 { .compatible = "brcm,bcm7278-pcie", .data = &bcm7278_cfg },
1465 { .compatible = "brcm,bcm7216-pcie", .data = &bcm7278_cfg },
1466 { .compatible = "brcm,bcm7445-pcie", .data = &generic_cfg },
1467 { .compatible = "brcm,bcm7435-pcie", .data = &bcm7435_cfg },
1468 { .compatible = "brcm,bcm7425-pcie", .data = &bcm7425_cfg },
1493 struct brcm_pcie *pcie; in brcm_pcie_probe() local
1496 bridge = devm_pci_alloc_host_bridge(&pdev->dev, sizeof(*pcie)); in brcm_pcie_probe()
1506 pcie = pci_host_bridge_priv(bridge); in brcm_pcie_probe()
1507 pcie->dev = &pdev->dev; in brcm_pcie_probe()
1508 pcie->np = np; in brcm_pcie_probe()
1509 pcie->reg_offsets = data->offsets; in brcm_pcie_probe()
1510 pcie->type = data->type; in brcm_pcie_probe()
1511 pcie->perst_set = data->perst_set; in brcm_pcie_probe()
1512 pcie->bridge_sw_init_set = data->bridge_sw_init_set; in brcm_pcie_probe()
1514 pcie->base = devm_platform_ioremap_resource(pdev, 0); in brcm_pcie_probe()
1515 if (IS_ERR(pcie->base)) in brcm_pcie_probe()
1516 return PTR_ERR(pcie->base); in brcm_pcie_probe()
1518 pcie->clk = devm_clk_get_optional(&pdev->dev, "sw_pcie"); in brcm_pcie_probe()
1519 if (IS_ERR(pcie->clk)) in brcm_pcie_probe()
1520 return PTR_ERR(pcie->clk); in brcm_pcie_probe()
1523 pcie->gen = (ret < 0) ? 0 : ret; in brcm_pcie_probe()
1525 pcie->ssc = of_property_read_bool(np, "brcm,enable-ssc"); in brcm_pcie_probe()
1527 ret = clk_prepare_enable(pcie->clk); in brcm_pcie_probe()
1532 pcie->rescal = devm_reset_control_get_optional_shared(&pdev->dev, "rescal"); in brcm_pcie_probe()
1533 if (IS_ERR(pcie->rescal)) { in brcm_pcie_probe()
1534 clk_disable_unprepare(pcie->clk); in brcm_pcie_probe()
1535 return PTR_ERR(pcie->rescal); in brcm_pcie_probe()
1537 pcie->perst_reset = devm_reset_control_get_optional_exclusive(&pdev->dev, "perst"); in brcm_pcie_probe()
1538 if (IS_ERR(pcie->perst_reset)) { in brcm_pcie_probe()
1539 clk_disable_unprepare(pcie->clk); in brcm_pcie_probe()
1540 return PTR_ERR(pcie->perst_reset); in brcm_pcie_probe()
1543 ret = reset_control_reset(pcie->rescal); in brcm_pcie_probe()
1547 ret = brcm_phy_start(pcie); in brcm_pcie_probe()
1549 reset_control_rearm(pcie->rescal); in brcm_pcie_probe()
1550 clk_disable_unprepare(pcie->clk); in brcm_pcie_probe()
1554 ret = brcm_pcie_setup(pcie); in brcm_pcie_probe()
1558 pcie->hw_rev = readl(pcie->base + PCIE_MISC_REVISION); in brcm_pcie_probe()
1559 if (pcie->type == BCM4908 && pcie->hw_rev >= BRCM_PCIE_HW_REV_3_20) { in brcm_pcie_probe()
1560 dev_err(pcie->dev, "hardware revision with unsupported PERST# setup\n"); in brcm_pcie_probe()
1565 msi_np = of_parse_phandle(pcie->np, "msi-parent", 0); in brcm_pcie_probe()
1566 if (pci_msi_enabled() && msi_np == pcie->np) { in brcm_pcie_probe()
1567 ret = brcm_pcie_enable_msi(pcie); in brcm_pcie_probe()
1569 dev_err(pcie->dev, "probe of internal MSI failed"); in brcm_pcie_probe()
1574 bridge->ops = pcie->type == BCM7425 ? &brcm7425_pcie_ops : &brcm_pcie_ops; in brcm_pcie_probe()
1575 bridge->sysdata = pcie; in brcm_pcie_probe()
1577 platform_set_drvdata(pdev, pcie); in brcm_pcie_probe()
1580 if (!ret && !brcm_pcie_link_up(pcie)) in brcm_pcie_probe()
1591 __brcm_pcie_remove(pcie); in brcm_pcie_probe()
1606 .name = "brcm-pcie",
1614 MODULE_DESCRIPTION("Broadcom STB PCIe RC driver");