Lines Matching +full:msi +full:- +full:x
1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright (C) 2009 - 2019 Broadcom */
19 #include <linux/msi.h>
25 #include <linux/pci-ecam.h>
36 /* BRCM_PCIE_CAP_REGS - Offset for the mandatory capability config regs */
62 #define SCB_SIZE_MASK(x) PCIE_MISC_MISC_CTRL_SCB ## x ## _SIZE_MASK argument
149 #define BRCM_INT_PCI_MSI_MASK GENMASK(BRCM_INT_PCI_MSI_NR - 1, 0)
151 32 - BRCM_INT_PCI_MSI_LEGACY_NR)
153 /* MSI target addresses */
166 #define MDIO_RD_DONE(x) (((x) & MDIO_DATA_DONE_MASK) ? 1 : 0) argument
167 #define MDIO_WT_DONE(x) (((x) & MDIO_DATA_DONE_MASK) ? 0 : 1) argument
178 #define IDX_ADDR(pcie) (pcie->reg_offsets[EXT_CFG_INDEX])
179 #define DATA_ADDR(pcie) (pcie->reg_offsets[EXT_CFG_DATA])
180 #define PCIE_RGR1_SW_INIT_1(pcie) (pcie->reg_offsets[RGR1_SW_INIT_1])
240 int nr; /* No. of MSI available, depends on chip */
254 struct brcm_msi *msi; member
270 return pcie->type == BCM7435 || pcie->type == BCM7425; in is_bmips()
275 * non-linear values of PCIE_X_MISC_RC_BAR[123]_CONFIG_LO.SIZE
283 return (log2_in - 12) + 0x1c; in brcm_pcie_encode_ibar_size()
286 return log2_in - 15; in brcm_pcie_encode_ibar_size()
319 return MDIO_RD_DONE(data) ? 0 : -EIO; in brcm_pcie_mdio_read()
340 return MDIO_WT_DONE(data) ? 0 : -EIO; in brcm_pcie_mdio_write()
353 ret = brcm_pcie_mdio_write(pcie->base, MDIO_PORT0, SET_ADDR_OFFSET, in brcm_pcie_set_ssc()
358 ret = brcm_pcie_mdio_read(pcie->base, MDIO_PORT0, in brcm_pcie_set_ssc()
365 ret = brcm_pcie_mdio_write(pcie->base, MDIO_PORT0, in brcm_pcie_set_ssc()
371 ret = brcm_pcie_mdio_read(pcie->base, MDIO_PORT0, in brcm_pcie_set_ssc()
379 return ssc && pll ? 0 : -EIO; in brcm_pcie_set_ssc()
385 u16 lnkctl2 = readw(pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2); in brcm_pcie_set_gen()
386 u32 lnkcap = readl(pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCAP); in brcm_pcie_set_gen()
389 writel(lnkcap, pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCAP); in brcm_pcie_set_gen()
392 writew(lnkctl2, pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2); in brcm_pcie_set_gen()
405 writel(lower_32_bits(pcie_addr), pcie->base + PCIE_MEM_WIN0_LO(win)); in brcm_pcie_set_outbound_win()
406 writel(upper_32_bits(pcie_addr), pcie->base + PCIE_MEM_WIN0_HI(win)); in brcm_pcie_set_outbound_win()
410 limit_addr_mb = (cpu_addr + size - 1) / SZ_1M; in brcm_pcie_set_outbound_win()
412 tmp = readl(pcie->base + PCIE_MEM_WIN0_BASE_LIMIT(win)); in brcm_pcie_set_outbound_win()
417 writel(tmp, pcie->base + PCIE_MEM_WIN0_BASE_LIMIT(win)); in brcm_pcie_set_outbound_win()
427 tmp = readl(pcie->base + PCIE_MEM_WIN0_BASE_HI(win)); in brcm_pcie_set_outbound_win()
430 writel(tmp, pcie->base + PCIE_MEM_WIN0_BASE_HI(win)); in brcm_pcie_set_outbound_win()
433 tmp = readl(pcie->base + PCIE_MEM_WIN0_LIMIT_HI(win)); in brcm_pcie_set_outbound_win()
436 writel(tmp, pcie->base + PCIE_MEM_WIN0_LIMIT_HI(win)); in brcm_pcie_set_outbound_win()
440 .name = "BRCM STB PCIe MSI",
447 /* Multi MSI is supported by the controller, but not by this driver */
456 struct brcm_msi *msi; in brcm_pcie_msi_isr() local
461 msi = irq_desc_get_handler_data(desc); in brcm_pcie_msi_isr()
462 dev = msi->dev; in brcm_pcie_msi_isr()
464 status = readl(msi->intr_base + MSI_INT_STATUS); in brcm_pcie_msi_isr()
465 status >>= msi->legacy_shift; in brcm_pcie_msi_isr()
467 for_each_set_bit(bit, &status, msi->nr) { in brcm_pcie_msi_isr()
469 ret = generic_handle_domain_irq(msi->inner_domain, bit); in brcm_pcie_msi_isr()
471 dev_dbg(dev, "unexpected MSI\n"); in brcm_pcie_msi_isr()
479 struct brcm_msi *msi = irq_data_get_irq_chip_data(data); in brcm_msi_compose_msi_msg() local
481 msg->address_lo = lower_32_bits(msi->target_addr); in brcm_msi_compose_msi_msg()
482 msg->address_hi = upper_32_bits(msi->target_addr); in brcm_msi_compose_msi_msg()
483 msg->data = (0xffff & PCIE_MISC_MSI_DATA_CONFIG_VAL_32) | data->hwirq; in brcm_msi_compose_msi_msg()
489 return -EINVAL; in brcm_msi_set_affinity()
494 struct brcm_msi *msi = irq_data_get_irq_chip_data(data); in brcm_msi_ack_irq() local
495 const int shift_amt = data->hwirq + msi->legacy_shift; in brcm_msi_ack_irq()
497 writel(1 << shift_amt, msi->intr_base + MSI_INT_CLR); in brcm_msi_ack_irq()
502 .name = "BRCM STB MSI",
508 static int brcm_msi_alloc(struct brcm_msi *msi) in brcm_msi_alloc() argument
512 mutex_lock(&msi->lock); in brcm_msi_alloc()
513 hwirq = bitmap_find_free_region(msi->used, msi->nr, 0); in brcm_msi_alloc()
514 mutex_unlock(&msi->lock); in brcm_msi_alloc()
519 static void brcm_msi_free(struct brcm_msi *msi, unsigned long hwirq) in brcm_msi_free() argument
521 mutex_lock(&msi->lock); in brcm_msi_free()
522 bitmap_release_region(msi->used, hwirq, 0); in brcm_msi_free()
523 mutex_unlock(&msi->lock); in brcm_msi_free()
529 struct brcm_msi *msi = domain->host_data; in brcm_irq_domain_alloc() local
532 hwirq = brcm_msi_alloc(msi); in brcm_irq_domain_alloc()
538 &brcm_msi_bottom_irq_chip, domain->host_data, in brcm_irq_domain_alloc()
547 struct brcm_msi *msi = irq_data_get_irq_chip_data(d); in brcm_irq_domain_free() local
549 brcm_msi_free(msi, d->hwirq); in brcm_irq_domain_free()
557 static int brcm_allocate_domains(struct brcm_msi *msi) in brcm_allocate_domains() argument
559 struct fwnode_handle *fwnode = of_node_to_fwnode(msi->np); in brcm_allocate_domains()
560 struct device *dev = msi->dev; in brcm_allocate_domains()
562 msi->inner_domain = irq_domain_add_linear(NULL, msi->nr, &msi_domain_ops, msi); in brcm_allocate_domains()
563 if (!msi->inner_domain) { in brcm_allocate_domains()
565 return -ENOMEM; in brcm_allocate_domains()
568 msi->msi_domain = pci_msi_create_irq_domain(fwnode, in brcm_allocate_domains()
570 msi->inner_domain); in brcm_allocate_domains()
571 if (!msi->msi_domain) { in brcm_allocate_domains()
572 dev_err(dev, "failed to create MSI domain\n"); in brcm_allocate_domains()
573 irq_domain_remove(msi->inner_domain); in brcm_allocate_domains()
574 return -ENOMEM; in brcm_allocate_domains()
580 static void brcm_free_domains(struct brcm_msi *msi) in brcm_free_domains() argument
582 irq_domain_remove(msi->msi_domain); in brcm_free_domains()
583 irq_domain_remove(msi->inner_domain); in brcm_free_domains()
588 struct brcm_msi *msi = pcie->msi; in brcm_msi_remove() local
590 if (!msi) in brcm_msi_remove()
592 irq_set_chained_handler_and_data(msi->irq, NULL, NULL); in brcm_msi_remove()
593 brcm_free_domains(msi); in brcm_msi_remove()
596 static void brcm_msi_set_regs(struct brcm_msi *msi) in brcm_msi_set_regs() argument
598 u32 val = msi->legacy ? BRCM_INT_PCI_MSI_LEGACY_MASK : in brcm_msi_set_regs()
601 writel(val, msi->intr_base + MSI_INT_MASK_CLR); in brcm_msi_set_regs()
602 writel(val, msi->intr_base + MSI_INT_CLR); in brcm_msi_set_regs()
605 * The 0 bit of PCIE_MISC_MSI_BAR_CONFIG_LO is repurposed to MSI in brcm_msi_set_regs()
608 writel(lower_32_bits(msi->target_addr) | 0x1, in brcm_msi_set_regs()
609 msi->base + PCIE_MISC_MSI_BAR_CONFIG_LO); in brcm_msi_set_regs()
610 writel(upper_32_bits(msi->target_addr), in brcm_msi_set_regs()
611 msi->base + PCIE_MISC_MSI_BAR_CONFIG_HI); in brcm_msi_set_regs()
613 val = msi->legacy ? PCIE_MISC_MSI_DATA_CONFIG_VAL_8 : PCIE_MISC_MSI_DATA_CONFIG_VAL_32; in brcm_msi_set_regs()
614 writel(val, msi->base + PCIE_MISC_MSI_DATA_CONFIG); in brcm_msi_set_regs()
619 struct brcm_msi *msi; in brcm_pcie_enable_msi() local
621 struct device *dev = pcie->dev; in brcm_pcie_enable_msi()
623 irq = irq_of_parse_and_map(dev->of_node, 1); in brcm_pcie_enable_msi()
625 dev_err(dev, "cannot map MSI interrupt\n"); in brcm_pcie_enable_msi()
626 return -ENODEV; in brcm_pcie_enable_msi()
629 msi = devm_kzalloc(dev, sizeof(struct brcm_msi), GFP_KERNEL); in brcm_pcie_enable_msi()
630 if (!msi) in brcm_pcie_enable_msi()
631 return -ENOMEM; in brcm_pcie_enable_msi()
633 mutex_init(&msi->lock); in brcm_pcie_enable_msi()
634 msi->dev = dev; in brcm_pcie_enable_msi()
635 msi->base = pcie->base; in brcm_pcie_enable_msi()
636 msi->np = pcie->np; in brcm_pcie_enable_msi()
637 msi->target_addr = pcie->msi_target_addr; in brcm_pcie_enable_msi()
638 msi->irq = irq; in brcm_pcie_enable_msi()
639 msi->legacy = pcie->hw_rev < BRCM_PCIE_HW_REV_33; in brcm_pcie_enable_msi()
647 if (msi->legacy) { in brcm_pcie_enable_msi()
648 msi->intr_base = msi->base + PCIE_INTR2_CPU_BASE; in brcm_pcie_enable_msi()
649 msi->nr = BRCM_INT_PCI_MSI_LEGACY_NR; in brcm_pcie_enable_msi()
650 msi->legacy_shift = 24; in brcm_pcie_enable_msi()
652 msi->intr_base = msi->base + PCIE_MSI_INTR2_BASE; in brcm_pcie_enable_msi()
653 msi->nr = BRCM_INT_PCI_MSI_NR; in brcm_pcie_enable_msi()
654 msi->legacy_shift = 0; in brcm_pcie_enable_msi()
657 ret = brcm_allocate_domains(msi); in brcm_pcie_enable_msi()
661 irq_set_chained_handler_and_data(msi->irq, brcm_pcie_msi_isr, msi); in brcm_pcie_enable_msi()
663 brcm_msi_set_regs(msi); in brcm_pcie_enable_msi()
664 pcie->msi = msi; in brcm_pcie_enable_msi()
672 void __iomem *base = pcie->base; in brcm_pcie_rc_mode()
680 u32 val = readl(pcie->base + PCIE_MISC_PCIE_STATUS); in brcm_pcie_link_up()
690 struct brcm_pcie *pcie = bus->sysdata; in brcm_pcie_map_bus()
691 void __iomem *base = pcie->base; in brcm_pcie_map_bus()
698 /* An access to our HW w/o link-up will cause a CPU Abort */ in brcm_pcie_map_bus()
703 idx = PCIE_ECAM_OFFSET(bus->number, devfn, 0); in brcm_pcie_map_bus()
704 writel(idx, pcie->base + PCIE_EXT_CFG_INDEX); in brcm_pcie_map_bus()
711 struct brcm_pcie *pcie = bus->sysdata; in brcm7425_pcie_map_bus()
712 void __iomem *base = pcie->base; in brcm7425_pcie_map_bus()
719 /* An access to our HW w/o link-up will cause a CPU Abort */ in brcm7425_pcie_map_bus()
724 idx = PCIE_ECAM_OFFSET(bus->number, devfn, where); in brcm7425_pcie_map_bus()
734 tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); in brcm_pcie_bridge_sw_init_set_generic()
736 writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); in brcm_pcie_bridge_sw_init_set_generic()
744 tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); in brcm_pcie_bridge_sw_init_set_7278()
746 writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); in brcm_pcie_bridge_sw_init_set_7278()
751 if (WARN_ONCE(!pcie->perst_reset, "missing PERST# reset controller\n")) in brcm_pcie_perst_set_4908()
755 reset_control_assert(pcie->perst_reset); in brcm_pcie_perst_set_4908()
757 reset_control_deassert(pcie->perst_reset); in brcm_pcie_perst_set_4908()
765 tmp = readl(pcie->base + PCIE_MISC_PCIE_CTRL); in brcm_pcie_perst_set_7278()
767 writel(tmp, pcie->base + PCIE_MISC_PCIE_CTRL); in brcm_pcie_perst_set_7278()
774 tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); in brcm_pcie_perst_set_generic()
776 writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); in brcm_pcie_perst_set_generic()
785 struct device *dev = pcie->dev; in brcm_pcie_get_rc_bar2_size_and_offset()
790 resource_list_for_each_entry(entry, &bridge->dma_ranges) { in brcm_pcie_get_rc_bar2_size_and_offset()
791 u64 pcie_beg = entry->res->start - entry->offset; in brcm_pcie_get_rc_bar2_size_and_offset()
793 size += entry->res->end - entry->res->start + 1; in brcm_pcie_get_rc_bar2_size_and_offset()
799 dev_err(dev, "DT node has no dma-ranges\n"); in brcm_pcie_get_rc_bar2_size_and_offset()
800 return -EINVAL; in brcm_pcie_get_rc_bar2_size_and_offset()
803 ret = of_property_read_variable_u64_array(pcie->np, "brcm,scb-sizes", pcie->memc_size, 1, in brcm_pcie_get_rc_bar2_size_and_offset()
808 pcie->num_memc = 1; in brcm_pcie_get_rc_bar2_size_and_offset()
809 pcie->memc_size[0] = 1ULL << fls64(size - 1); in brcm_pcie_get_rc_bar2_size_and_offset()
811 pcie->num_memc = ret; in brcm_pcie_get_rc_bar2_size_and_offset()
815 for (i = 0, size = 0; i < pcie->num_memc; i++) in brcm_pcie_get_rc_bar2_size_and_offset()
816 size += pcie->memc_size[i]; in brcm_pcie_get_rc_bar2_size_and_offset()
818 /* System memory starts at this address in PCIe-space */ in brcm_pcie_get_rc_bar2_size_and_offset()
821 *rc_bar2_size = 1ULL << fls64(size - 1); in brcm_pcie_get_rc_bar2_size_and_offset()
825 * whatever the device-tree provides. This is because of an HW issue on in brcm_pcie_get_rc_bar2_size_and_offset()
827 * firmware has to dynamically edit dma-ranges due to a bug on the in brcm_pcie_get_rc_bar2_size_and_offset()
829 * lower 3GB of memory. Given this, we decided to keep the dma-ranges in brcm_pcie_get_rc_bar2_size_and_offset()
830 * in check, avoiding hard to debug device-tree related issues in the in brcm_pcie_get_rc_bar2_size_and_offset()
836 * matters, the viewport must start on a pcie-address that is aligned in brcm_pcie_get_rc_bar2_size_and_offset()
838 * represent system memory -- e.g. 3GB of memory requires a 4GB in brcm_pcie_get_rc_bar2_size_and_offset()
839 * viewport -- we can map the outbound memory in or after 3GB and even in brcm_pcie_get_rc_bar2_size_and_offset()
846 * - The best-case scenario, memory up to 3GB, is to place the inbound in brcm_pcie_get_rc_bar2_size_and_offset()
847 * region in the first 4GB of pcie-space, as some legacy devices can in brcm_pcie_get_rc_bar2_size_and_offset()
848 * only address 32bits. We would also like to put the MSI under 4GB in brcm_pcie_get_rc_bar2_size_and_offset()
849 * as well, since some devices require a 32bit MSI target address. in brcm_pcie_get_rc_bar2_size_and_offset()
851 * - If the system memory is 4GB or larger we cannot start the inbound in brcm_pcie_get_rc_bar2_size_and_offset()
853 * outbound memory @ 3GB). So instead it will start at the 1x in brcm_pcie_get_rc_bar2_size_and_offset()
856 if (!*rc_bar2_size || (*rc_bar2_offset & (*rc_bar2_size - 1)) || in brcm_pcie_get_rc_bar2_size_and_offset()
858 dev_err(dev, "Invalid rc_bar2_offset/size: size 0x%llx, off 0x%llx\n", in brcm_pcie_get_rc_bar2_size_and_offset()
860 return -EINVAL; in brcm_pcie_get_rc_bar2_size_and_offset()
869 void __iomem *base = pcie->base; in brcm_pcie_setup()
877 pcie->bridge_sw_init_set(pcie, 1); in brcm_pcie_setup()
881 pcie->bridge_sw_init_set(pcie, 0); in brcm_pcie_setup()
899 else if (pcie->type == BCM2711) in brcm_pcie_setup()
901 else if (pcie->type == BCM7278) in brcm_pcie_setup()
926 for (memc = 0; memc < pcie->num_memc; memc++) { in brcm_pcie_setup()
927 u32 scb_size_val = ilog2(pcie->memc_size[memc]) - 15; in brcm_pcie_setup()
939 * We ideally want the MSI target address to be located in the 32bit in brcm_pcie_setup()
943 * account the rounding-up we're forced to perform). in brcm_pcie_setup()
946 pcie->msi_target_addr = BRCM_MSI_TARGET_ADDR_LT_4GB; in brcm_pcie_setup()
948 pcie->msi_target_addr = BRCM_MSI_TARGET_ADDR_GT_4GB; in brcm_pcie_setup()
951 dev_err(pcie->dev, "PCIe RC controller misconfigured as Endpoint\n"); in brcm_pcie_setup()
952 return -EINVAL; in brcm_pcie_setup()
955 /* disable the PCIe->GISB memory window (RC_BAR1) */ in brcm_pcie_setup()
960 /* disable the PCIe->SCB memory window (RC_BAR3) */ in brcm_pcie_setup()
965 /* Don't advertise L0s capability if 'aspm-no-l0s' */ in brcm_pcie_setup()
967 if (!of_property_read_bool(pcie->np, "aspm-no-l0s")) in brcm_pcie_setup()
976 * a PCIe-PCIe bridge (the default setting is to be EP mode). in brcm_pcie_setup()
984 resource_list_for_each_entry(entry, &bridge->windows) { in brcm_pcie_setup()
985 struct resource *res = entry->res; in brcm_pcie_setup()
991 dev_err(pcie->dev, "too many outbound wins\n"); in brcm_pcie_setup()
992 return -EINVAL; in brcm_pcie_setup()
996 u64 start = res->start; in brcm_pcie_setup()
1004 start - entry->offset, in brcm_pcie_setup()
1008 brcm_pcie_set_outbound_win(pcie, num_out_wins, res->start, in brcm_pcie_setup()
1009 res->start - entry->offset, in brcm_pcie_setup()
1014 /* PCIe->SCB endian mode for BAR */ in brcm_pcie_setup()
1025 struct device *dev = pcie->dev; in brcm_pcie_start_link()
1026 void __iomem *base = pcie->base; in brcm_pcie_start_link()
1033 pcie->perst_set(pcie, 0); in brcm_pcie_start_link()
1037 * Intermittently check status for link-up, up to a total of 100ms. in brcm_pcie_start_link()
1044 return -ENODEV; in brcm_pcie_start_link()
1047 if (pcie->gen) in brcm_pcie_start_link()
1048 brcm_pcie_set_gen(pcie, pcie->gen); in brcm_pcie_start_link()
1050 if (pcie->ssc) { in brcm_pcie_start_link()
1061 dev_info(dev, "link up, %s x%u %s\n", in brcm_pcie_start_link()
1091 sr->num_supplies = ARRAY_SIZE(supplies); in alloc_subdev_regulators()
1093 sr->supplies[i].supply = supplies[i]; in alloc_subdev_regulators()
1101 struct brcm_pcie *pcie = bus->sysdata; in brcm_pcie_add_bus()
1102 struct device *dev = &bus->dev; in brcm_pcie_add_bus()
1106 if (!bus->parent || !pci_is_root_bus(bus->parent)) in brcm_pcie_add_bus()
1109 if (dev->of_node) { in brcm_pcie_add_bus()
1116 pcie->sr = sr; in brcm_pcie_add_bus()
1118 ret = regulator_bulk_get(dev, sr->num_supplies, sr->supplies); in brcm_pcie_add_bus()
1124 ret = regulator_bulk_enable(sr->num_supplies, sr->supplies); in brcm_pcie_add_bus()
1127 regulator_bulk_free(sr->num_supplies, sr->supplies); in brcm_pcie_add_bus()
1128 pcie->sr = NULL; in brcm_pcie_add_bus()
1139 struct brcm_pcie *pcie = bus->sysdata; in brcm_pcie_remove_bus()
1140 struct subdev_regulators *sr = pcie->sr; in brcm_pcie_remove_bus()
1141 struct device *dev = &bus->dev; in brcm_pcie_remove_bus()
1146 if (regulator_bulk_disable(sr->num_supplies, sr->supplies)) in brcm_pcie_remove_bus()
1148 regulator_bulk_free(sr->num_supplies, sr->supplies); in brcm_pcie_remove_bus()
1149 pcie->sr = NULL; in brcm_pcie_remove_bus()
1152 /* L23 is a low-power PCIe link state */
1155 void __iomem *base = pcie->base; in brcm_pcie_enter_l23()
1175 dev_err(pcie->dev, "failed to enter low-power link state\n"); in brcm_pcie_enter_l23()
1188 const int beg = start ? 0 : PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_NFLDS - 1; in brcm_phy_cntl()
1189 const int end = start ? PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_NFLDS : -1; in brcm_phy_cntl()
1192 void __iomem *base = pcie->base; in brcm_phy_cntl()
1195 for (i = beg; i != end; start ? i++ : i--) { in brcm_phy_cntl()
1207 ret = (tmp & combined_mask) == val ? 0 : -EIO; in brcm_phy_cntl()
1209 dev_err(pcie->dev, "failed to %s phy\n", (start ? "start" : "stop")); in brcm_phy_cntl()
1216 return pcie->rescal ? brcm_phy_cntl(pcie, 1) : 0; in brcm_phy_start()
1221 return pcie->rescal ? brcm_phy_cntl(pcie, 0) : 0; in brcm_phy_stop()
1226 void __iomem *base = pcie->base; in brcm_pcie_turn_off()
1232 pcie->perst_set(pcie, 1); in brcm_pcie_turn_off()
1245 pcie->bridge_sw_init_set(pcie, 1); in brcm_pcie_turn_off()
1252 if (device_may_wakeup(&dev->dev)) { in pci_dev_may_wakeup()
1254 dev_info(&dev->dev, "Possible wake-up device; regulators will not be disabled\n"); in pci_dev_may_wakeup()
1274 ret = reset_control_rearm(pcie->rescal); in brcm_pcie_suspend_noirq()
1280 if (pcie->sr) { in brcm_pcie_suspend_noirq()
1283 * downstream device is enabled as a wake-up source, do not in brcm_pcie_suspend_noirq()
1286 pcie->ep_wakeup_capable = false; in brcm_pcie_suspend_noirq()
1287 pci_walk_bus(bridge->bus, pci_dev_may_wakeup, in brcm_pcie_suspend_noirq()
1288 &pcie->ep_wakeup_capable); in brcm_pcie_suspend_noirq()
1289 if (!pcie->ep_wakeup_capable) { in brcm_pcie_suspend_noirq()
1290 ret = regulator_bulk_disable(pcie->sr->num_supplies, in brcm_pcie_suspend_noirq()
1291 pcie->sr->supplies); in brcm_pcie_suspend_noirq()
1294 reset_control_reset(pcie->rescal); in brcm_pcie_suspend_noirq()
1299 clk_disable_unprepare(pcie->clk); in brcm_pcie_suspend_noirq()
1311 base = pcie->base; in brcm_pcie_resume_noirq()
1312 ret = clk_prepare_enable(pcie->clk); in brcm_pcie_resume_noirq()
1316 ret = reset_control_reset(pcie->rescal); in brcm_pcie_resume_noirq()
1325 pcie->bridge_sw_init_set(pcie, 0); in brcm_pcie_resume_noirq()
1339 if (pcie->sr) { in brcm_pcie_resume_noirq()
1340 if (pcie->ep_wakeup_capable) { in brcm_pcie_resume_noirq()
1347 pcie->ep_wakeup_capable = false; in brcm_pcie_resume_noirq()
1349 ret = regulator_bulk_enable(pcie->sr->num_supplies, in brcm_pcie_resume_noirq()
1350 pcie->sr->supplies); in brcm_pcie_resume_noirq()
1362 if (pcie->msi) in brcm_pcie_resume_noirq()
1363 brcm_msi_set_regs(pcie->msi); in brcm_pcie_resume_noirq()
1368 if (pcie->sr) in brcm_pcie_resume_noirq()
1369 regulator_bulk_disable(pcie->sr->num_supplies, pcie->sr->supplies); in brcm_pcie_resume_noirq()
1371 reset_control_rearm(pcie->rescal); in brcm_pcie_resume_noirq()
1373 clk_disable_unprepare(pcie->clk); in brcm_pcie_resume_noirq()
1382 dev_err(pcie->dev, "Could not stop phy\n"); in __brcm_pcie_remove()
1383 if (reset_control_rearm(pcie->rescal)) in __brcm_pcie_remove()
1384 dev_err(pcie->dev, "Could not rearm rescal reset\n"); in __brcm_pcie_remove()
1385 clk_disable_unprepare(pcie->clk); in __brcm_pcie_remove()
1393 pci_stop_root_bus(bridge->bus); in brcm_pcie_remove()
1394 pci_remove_root_bus(bridge->bus); in brcm_pcie_remove()
1461 { .compatible = "brcm,bcm2711-pcie", .data = &bcm2711_cfg },
1462 { .compatible = "brcm,bcm4908-pcie", .data = &bcm4908_cfg },
1463 { .compatible = "brcm,bcm7211-pcie", .data = &generic_cfg },
1464 { .compatible = "brcm,bcm7278-pcie", .data = &bcm7278_cfg },
1465 { .compatible = "brcm,bcm7216-pcie", .data = &bcm7278_cfg },
1466 { .compatible = "brcm,bcm7445-pcie", .data = &generic_cfg },
1467 { .compatible = "brcm,bcm7435-pcie", .data = &bcm7435_cfg },
1468 { .compatible = "brcm,bcm7425-pcie", .data = &bcm7425_cfg },
1490 struct device_node *np = pdev->dev.of_node, *msi_np; in brcm_pcie_probe()
1496 bridge = devm_pci_alloc_host_bridge(&pdev->dev, sizeof(*pcie)); in brcm_pcie_probe()
1498 return -ENOMEM; in brcm_pcie_probe()
1500 data = of_device_get_match_data(&pdev->dev); in brcm_pcie_probe()
1503 return -EINVAL; in brcm_pcie_probe()
1507 pcie->dev = &pdev->dev; in brcm_pcie_probe()
1508 pcie->np = np; in brcm_pcie_probe()
1509 pcie->reg_offsets = data->offsets; in brcm_pcie_probe()
1510 pcie->type = data->type; in brcm_pcie_probe()
1511 pcie->perst_set = data->perst_set; in brcm_pcie_probe()
1512 pcie->bridge_sw_init_set = data->bridge_sw_init_set; in brcm_pcie_probe()
1514 pcie->base = devm_platform_ioremap_resource(pdev, 0); in brcm_pcie_probe()
1515 if (IS_ERR(pcie->base)) in brcm_pcie_probe()
1516 return PTR_ERR(pcie->base); in brcm_pcie_probe()
1518 pcie->clk = devm_clk_get_optional(&pdev->dev, "sw_pcie"); in brcm_pcie_probe()
1519 if (IS_ERR(pcie->clk)) in brcm_pcie_probe()
1520 return PTR_ERR(pcie->clk); in brcm_pcie_probe()
1523 pcie->gen = (ret < 0) ? 0 : ret; in brcm_pcie_probe()
1525 pcie->ssc = of_property_read_bool(np, "brcm,enable-ssc"); in brcm_pcie_probe()
1527 ret = clk_prepare_enable(pcie->clk); in brcm_pcie_probe()
1529 dev_err(&pdev->dev, "could not enable clock\n"); in brcm_pcie_probe()
1532 pcie->rescal = devm_reset_control_get_optional_shared(&pdev->dev, "rescal"); in brcm_pcie_probe()
1533 if (IS_ERR(pcie->rescal)) { in brcm_pcie_probe()
1534 clk_disable_unprepare(pcie->clk); in brcm_pcie_probe()
1535 return PTR_ERR(pcie->rescal); in brcm_pcie_probe()
1537 pcie->perst_reset = devm_reset_control_get_optional_exclusive(&pdev->dev, "perst"); in brcm_pcie_probe()
1538 if (IS_ERR(pcie->perst_reset)) { in brcm_pcie_probe()
1539 clk_disable_unprepare(pcie->clk); in brcm_pcie_probe()
1540 return PTR_ERR(pcie->perst_reset); in brcm_pcie_probe()
1543 ret = reset_control_reset(pcie->rescal); in brcm_pcie_probe()
1545 dev_err(&pdev->dev, "failed to deassert 'rescal'\n"); in brcm_pcie_probe()
1549 reset_control_rearm(pcie->rescal); in brcm_pcie_probe()
1550 clk_disable_unprepare(pcie->clk); in brcm_pcie_probe()
1558 pcie->hw_rev = readl(pcie->base + PCIE_MISC_REVISION); in brcm_pcie_probe()
1559 if (pcie->type == BCM4908 && pcie->hw_rev >= BRCM_PCIE_HW_REV_3_20) { in brcm_pcie_probe()
1560 dev_err(pcie->dev, "hardware revision with unsupported PERST# setup\n"); in brcm_pcie_probe()
1561 ret = -ENODEV; in brcm_pcie_probe()
1565 msi_np = of_parse_phandle(pcie->np, "msi-parent", 0); in brcm_pcie_probe()
1566 if (pci_msi_enabled() && msi_np == pcie->np) { in brcm_pcie_probe()
1569 dev_err(pcie->dev, "probe of internal MSI failed"); in brcm_pcie_probe()
1574 bridge->ops = pcie->type == BCM7425 ? &brcm7425_pcie_ops : &brcm_pcie_ops; in brcm_pcie_probe()
1575 bridge->sysdata = pcie; in brcm_pcie_probe()
1581 ret = -ENODEV; in brcm_pcie_probe()
1606 .name = "brcm-pcie",