54 	struct mobiveil_root_port *rp = &pcie->rp;  in mobiveil_pcie_map_bus()  local
76 	return rp->config_axi_slave_base + where;  in mobiveil_pcie_map_bus()
90 	struct mobiveil_root_port *rp = &pcie->rp;  in mobiveil_pcie_isr()  local
91 	struct mobiveil_msi *msi = &rp->msi;  in mobiveil_pcie_isr()
118 				ret = generic_handle_domain_irq(rp->intx_domain,  in mobiveil_pcie_isr()
173 	struct mobiveil_root_port *rp = &pcie->rp;  in mobiveil_pcie_parse_dt()  local
179 	rp->config_axi_slave_base = devm_pci_remap_cfg_resource(dev, res);  in mobiveil_pcie_parse_dt()
180 	if (IS_ERR(rp->config_axi_slave_base))  in mobiveil_pcie_parse_dt()
181 		return PTR_ERR(rp->config_axi_slave_base);  in mobiveil_pcie_parse_dt()
182 	rp->ob_io_res = res;  in mobiveil_pcie_parse_dt()
205 	struct mobiveil_msi *msi = &pcie->rp.msi;  in mobiveil_pcie_enable_msi()
220 	struct mobiveil_root_port *rp = &pcie->rp;  in mobiveil_host_init()  local
221 	struct pci_host_bridge *bridge = rp->bridge;  in mobiveil_host_init()
273 	program_ob_windows(pcie, WIN_NUM_0, rp->ob_io_res->start, 0,  in mobiveil_host_init()
274 			   CFG_WINDOW_TYPE, resource_size(rp->ob_io_res));  in mobiveil_host_init()
307 	struct mobiveil_root_port *rp;  in mobiveil_mask_intx_irq()  local
311 	rp = &pcie->rp;  in mobiveil_mask_intx_irq()
313 	raw_spin_lock_irqsave(&rp->intx_mask_lock, flags);  in mobiveil_mask_intx_irq()
317 	raw_spin_unlock_irqrestore(&rp->intx_mask_lock, flags);  in mobiveil_mask_intx_irq()
323 	struct mobiveil_root_port *rp;  in mobiveil_unmask_intx_irq()  local
327 	rp = &pcie->rp;  in mobiveil_unmask_intx_irq()
329 	raw_spin_lock_irqsave(&rp->intx_mask_lock, flags);  in mobiveil_unmask_intx_irq()
333 	raw_spin_unlock_irqrestore(&rp->intx_mask_lock, flags);  in mobiveil_unmask_intx_irq()
401 	struct mobiveil_msi *msi = &pcie->rp.msi;  in mobiveil_irq_msi_domain_alloc()
428 	struct mobiveil_msi *msi = &pcie->rp.msi;  in mobiveil_irq_msi_domain_free()
449 	struct mobiveil_msi *msi = &pcie->rp.msi;  in mobiveil_allocate_msi_domains()
475 	struct mobiveil_root_port *rp = &pcie->rp;  in mobiveil_pcie_init_irq_domain()  local
478 	rp->intx_domain = irq_domain_add_linear(node, PCI_NUM_INTX,  in mobiveil_pcie_init_irq_domain()
481 	if (!rp->intx_domain) {  in mobiveil_pcie_init_irq_domain()
486 	raw_spin_lock_init(&rp->intx_mask_lock);  in mobiveil_pcie_init_irq_domain()
496 	struct mobiveil_root_port *rp = &pcie->rp;  in mobiveil_pcie_integrated_interrupt_init()  local
509 	rp->irq = platform_get_irq(pdev, 0);  in mobiveil_pcie_integrated_interrupt_init()
510 	if (rp->irq < 0)  in mobiveil_pcie_integrated_interrupt_init()
511 		return rp->irq;  in mobiveil_pcie_integrated_interrupt_init()
520 	irq_set_chained_handler_and_data(rp->irq, mobiveil_pcie_isr, pcie);  in mobiveil_pcie_integrated_interrupt_init()
532 	struct mobiveil_root_port *rp = &pcie->rp;  in mobiveil_pcie_interrupt_init()  local
534 	if (rp->ops->interrupt_init)  in mobiveil_pcie_interrupt_init()
535 		return rp->ops->interrupt_init(pcie);  in mobiveil_pcie_interrupt_init()
552 	struct mobiveil_root_port *rp = &pcie->rp;  in mobiveil_pcie_host_probe()  local
553 	struct pci_host_bridge *bridge = rp->bridge;  in mobiveil_pcie_host_probe()