3  * PCIe host controller driver for Mobiveil PCIe Host controller
28 #include "pcie-mobiveil.h"
53 	struct mobiveil_pcie *pcie = bus->sysdata;  in mobiveil_pcie_map_bus()  local
54 	struct mobiveil_root_port *rp = &pcie->rp;  in mobiveil_pcie_map_bus()
62 		return pcie->csr_axi_slave_base + where;  in mobiveil_pcie_map_bus()
74 	mobiveil_csr_writel(pcie, value, PAB_AXI_AMAP_PEX_WIN_L(WIN_NUM_0));  in mobiveil_pcie_map_bus()
88 	struct mobiveil_pcie *pcie = irq_desc_get_handler_data(desc);  in mobiveil_pcie_isr()  local
89 	struct device *dev = &pcie->pdev->dev;  in mobiveil_pcie_isr()
90 	struct mobiveil_root_port *rp = &pcie->rp;  in mobiveil_pcie_isr()
105 	val = mobiveil_csr_readl(pcie, PAB_INTP_AMBA_MISC_STAT);  in mobiveil_pcie_isr()
106 	mask = mobiveil_csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB);  in mobiveil_pcie_isr()
111 		shifted_status = mobiveil_csr_readl(pcie,  in mobiveil_pcie_isr()
125 				mobiveil_csr_writel(pcie,  in mobiveil_pcie_isr()
130 			shifted_status = mobiveil_csr_readl(pcie,  in mobiveil_pcie_isr()
138 	msi_status = readl_relaxed(pcie->apb_csr_base + MSI_STATUS_OFFSET);  in mobiveil_pcie_isr()
142 		msi_data = readl_relaxed(pcie->apb_csr_base + MSI_DATA_OFFSET);  in mobiveil_pcie_isr()
150 		msi_addr_lo = readl_relaxed(pcie->apb_csr_base +  in mobiveil_pcie_isr()
152 		msi_addr_hi = readl_relaxed(pcie->apb_csr_base +  in mobiveil_pcie_isr()
159 		msi_status = readl_relaxed(pcie->apb_csr_base +  in mobiveil_pcie_isr()
164 	mobiveil_csr_writel(pcie, intr_status, PAB_INTP_AMBA_MISC_STAT);  in mobiveil_pcie_isr()
168 static int mobiveil_pcie_parse_dt(struct mobiveil_pcie *pcie)  in mobiveil_pcie_parse_dt()  argument
170 	struct device *dev = &pcie->pdev->dev;  in mobiveil_pcie_parse_dt()
171 	struct platform_device *pdev = pcie->pdev;  in mobiveil_pcie_parse_dt()
173 	struct mobiveil_root_port *rp = &pcie->rp;  in mobiveil_pcie_parse_dt()
187 	pcie->csr_axi_slave_base = devm_pci_remap_cfg_resource(dev, res);  in mobiveil_pcie_parse_dt()
188 	if (IS_ERR(pcie->csr_axi_slave_base))  in mobiveil_pcie_parse_dt()
189 		return PTR_ERR(pcie->csr_axi_slave_base);  in mobiveil_pcie_parse_dt()
190 	pcie->pcie_reg_base = res->start;  in mobiveil_pcie_parse_dt()
193 	if (of_property_read_u32(node, "apio-wins", &pcie->apio_wins))  in mobiveil_pcie_parse_dt()
194 		pcie->apio_wins = MAX_PIO_WINDOWS;  in mobiveil_pcie_parse_dt()
196 	if (of_property_read_u32(node, "ppio-wins", &pcie->ppio_wins))  in mobiveil_pcie_parse_dt()
197 		pcie->ppio_wins = MAX_PIO_WINDOWS;  in mobiveil_pcie_parse_dt()
202 static void mobiveil_pcie_enable_msi(struct mobiveil_pcie *pcie)  in mobiveil_pcie_enable_msi()  argument
204 	phys_addr_t msg_addr = pcie->pcie_reg_base;  in mobiveil_pcie_enable_msi()
205 	struct mobiveil_msi *msi = &pcie->rp.msi;  in mobiveil_pcie_enable_msi()
211 		       pcie->apb_csr_base + MSI_BASE_LO_OFFSET);  in mobiveil_pcie_enable_msi()
213 		       pcie->apb_csr_base + MSI_BASE_HI_OFFSET);  in mobiveil_pcie_enable_msi()
214 	writel_relaxed(4096, pcie->apb_csr_base + MSI_SIZE_OFFSET);  in mobiveil_pcie_enable_msi()
215 	writel_relaxed(1, pcie->apb_csr_base + MSI_ENABLE_OFFSET);  in mobiveil_pcie_enable_msi()
218 int mobiveil_host_init(struct mobiveil_pcie *pcie, bool reinit)  in mobiveil_host_init()  argument
220 	struct mobiveil_root_port *rp = &pcie->rp;  in mobiveil_host_init()
225 	pcie->ib_wins_configured = 0;  in mobiveil_host_init()
226 	pcie->ob_wins_configured = 0;  in mobiveil_host_init()
230 		value = mobiveil_csr_readl(pcie, PCI_PRIMARY_BUS);  in mobiveil_host_init()
233 		mobiveil_csr_writel(pcie, value, PCI_PRIMARY_BUS);  in mobiveil_host_init()
240 	value = mobiveil_csr_readl(pcie, PCI_COMMAND);  in mobiveil_host_init()
242 	mobiveil_csr_writel(pcie, value, PCI_COMMAND);  in mobiveil_host_init()
248 	pab_ctrl = mobiveil_csr_readl(pcie, PAB_CTRL);  in mobiveil_host_init()
250 	mobiveil_csr_writel(pcie, pab_ctrl, PAB_CTRL);  in mobiveil_host_init()
256 	value = mobiveil_csr_readl(pcie, PAB_AXI_PIO_CTRL);  in mobiveil_host_init()
258 	mobiveil_csr_writel(pcie, value, PAB_AXI_PIO_CTRL);  in mobiveil_host_init()
260 	/* Enable PCIe PIO master */  in mobiveil_host_init()
261 	value = mobiveil_csr_readl(pcie, PAB_PEX_PIO_CTRL);  in mobiveil_host_init()
263 	mobiveil_csr_writel(pcie, value, PAB_PEX_PIO_CTRL);  in mobiveil_host_init()
273 	program_ob_windows(pcie, WIN_NUM_0, rp->ob_io_res->start, 0,  in mobiveil_host_init()
277 	program_ib_windows(pcie, WIN_NUM_0, 0, 0, MEM_WINDOW_TYPE, IB_WIN_SIZE);  in mobiveil_host_init()
289 		program_ob_windows(pcie, pcie->ob_wins_configured,  in mobiveil_host_init()
295 	/* fixup for PCIe class register */  in mobiveil_host_init()
296 	value = mobiveil_csr_readl(pcie, PAB_INTP_AXI_PIO_CLASS);  in mobiveil_host_init()
299 	mobiveil_csr_writel(pcie, value, PAB_INTP_AXI_PIO_CLASS);  in mobiveil_host_init()
306 	struct mobiveil_pcie *pcie = irq_data_get_irq_chip_data(data);  in mobiveil_mask_intx_irq()  local
311 	rp = &pcie->rp;  in mobiveil_mask_intx_irq()
314 	shifted_val = mobiveil_csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB);  in mobiveil_mask_intx_irq()
316 	mobiveil_csr_writel(pcie, shifted_val, PAB_INTP_AMBA_MISC_ENB);  in mobiveil_mask_intx_irq()
322 	struct mobiveil_pcie *pcie = irq_data_get_irq_chip_data(data);  in mobiveil_unmask_intx_irq()  local
327 	rp = &pcie->rp;  in mobiveil_unmask_intx_irq()
330 	shifted_val = mobiveil_csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB);  in mobiveil_unmask_intx_irq()
332 	mobiveil_csr_writel(pcie, shifted_val, PAB_INTP_AMBA_MISC_ENB);  in mobiveil_unmask_intx_irq()
360 	.name = "Mobiveil PCIe MSI",
373 	struct mobiveil_pcie *pcie = irq_data_get_irq_chip_data(data);  in mobiveil_compose_msi_msg()  local
374 	phys_addr_t addr = pcie->pcie_reg_base + (data->hwirq * sizeof(int));  in mobiveil_compose_msi_msg()
380 	dev_dbg(&pcie->pdev->dev, "msi#%d address_hi %#x address_lo %#x\n",  in mobiveil_compose_msi_msg()
400 	struct mobiveil_pcie *pcie = domain->host_data;  in mobiveil_irq_msi_domain_alloc()  local
401 	struct mobiveil_msi *msi = &pcie->rp.msi;  in mobiveil_irq_msi_domain_alloc()
427 	struct mobiveil_pcie *pcie = irq_data_get_irq_chip_data(d);  in mobiveil_irq_msi_domain_free()  local
428 	struct mobiveil_msi *msi = &pcie->rp.msi;  in mobiveil_irq_msi_domain_free()
433 		dev_err(&pcie->pdev->dev, "trying to free unused MSI#%lu\n",  in mobiveil_irq_msi_domain_free()
445 static int mobiveil_allocate_msi_domains(struct mobiveil_pcie *pcie)  in mobiveil_allocate_msi_domains()  argument
447 	struct device *dev = &pcie->pdev->dev;  in mobiveil_allocate_msi_domains()
449 	struct mobiveil_msi *msi = &pcie->rp.msi;  in mobiveil_allocate_msi_domains()
453 						&msi_domain_ops, pcie);  in mobiveil_allocate_msi_domains()
471 static int mobiveil_pcie_init_irq_domain(struct mobiveil_pcie *pcie)  in mobiveil_pcie_init_irq_domain()  argument
473 	struct device *dev = &pcie->pdev->dev;  in mobiveil_pcie_init_irq_domain()
475 	struct mobiveil_root_port *rp = &pcie->rp;  in mobiveil_pcie_init_irq_domain()
479 						&intx_domain_ops, pcie);  in mobiveil_pcie_init_irq_domain()
489 	return mobiveil_allocate_msi_domains(pcie);  in mobiveil_pcie_init_irq_domain()
492 static int mobiveil_pcie_integrated_interrupt_init(struct mobiveil_pcie *pcie)  in mobiveil_pcie_integrated_interrupt_init()  argument
494 	struct platform_device *pdev = pcie->pdev;  in mobiveil_pcie_integrated_interrupt_init()
496 	struct mobiveil_root_port *rp = &pcie->rp;  in mobiveil_pcie_integrated_interrupt_init()
502 	pcie->apb_csr_base = devm_pci_remap_cfg_resource(dev, res);  in mobiveil_pcie_integrated_interrupt_init()
503 	if (IS_ERR(pcie->apb_csr_base))  in mobiveil_pcie_integrated_interrupt_init()
504 		return PTR_ERR(pcie->apb_csr_base);  in mobiveil_pcie_integrated_interrupt_init()
507 	mobiveil_pcie_enable_msi(pcie);  in mobiveil_pcie_integrated_interrupt_init()
514 	ret = mobiveil_pcie_init_irq_domain(pcie);  in mobiveil_pcie_integrated_interrupt_init()
520 	irq_set_chained_handler_and_data(rp->irq, mobiveil_pcie_isr, pcie);  in mobiveil_pcie_integrated_interrupt_init()
523 	mobiveil_csr_writel(pcie, (PAB_INTP_INTX_MASK | PAB_INTP_MSI_MASK),  in mobiveil_pcie_integrated_interrupt_init()
530 static int mobiveil_pcie_interrupt_init(struct mobiveil_pcie *pcie)  in mobiveil_pcie_interrupt_init()  argument
532 	struct mobiveil_root_port *rp = &pcie->rp;  in mobiveil_pcie_interrupt_init()
535 		return rp->ops->interrupt_init(pcie);  in mobiveil_pcie_interrupt_init()
537 	return mobiveil_pcie_integrated_interrupt_init(pcie);  in mobiveil_pcie_interrupt_init()
540 static bool mobiveil_pcie_is_bridge(struct mobiveil_pcie *pcie)  in mobiveil_pcie_is_bridge()  argument
544 	header_type = mobiveil_csr_readb(pcie, PCI_HEADER_TYPE);  in mobiveil_pcie_is_bridge()
550 int mobiveil_pcie_host_probe(struct mobiveil_pcie *pcie)  in mobiveil_pcie_host_probe()  argument
552 	struct mobiveil_root_port *rp = &pcie->rp;  in mobiveil_pcie_host_probe()
554 	struct device *dev = &pcie->pdev->dev;  in mobiveil_pcie_host_probe()
557 	ret = mobiveil_pcie_parse_dt(pcie);  in mobiveil_pcie_host_probe()
563 	if (!mobiveil_pcie_is_bridge(pcie))  in mobiveil_pcie_host_probe()
570 	ret = mobiveil_host_init(pcie, false);  in mobiveil_pcie_host_probe()
576 	ret = mobiveil_pcie_interrupt_init(pcie);  in mobiveil_pcie_host_probe()
583 	bridge->sysdata = pcie;  in mobiveil_pcie_host_probe()
586 	ret = mobiveil_bringup_link(pcie);  in mobiveil_pcie_host_probe()