Lines Matching +full:msi +full:- +full:x
1 // SPDX-License-Identifier: GPL-2.0
6 * Copyright 2019-2020 NXP
19 #include <linux/msi.h>
28 #include "pcie-mobiveil.h"
40 if ((bus->primary == to_pci_host_bridge(bus->bridge)->busnr) && (PCI_SLOT(devfn) > 0)) in mobiveil_pcie_valid_device()
47 * mobiveil_pcie_map_bus - routine to get the configuration base of either
53 struct mobiveil_pcie *pcie = bus->sysdata; in mobiveil_pcie_map_bus()
54 struct mobiveil_root_port *rp = &pcie->rp; in mobiveil_pcie_map_bus()
62 return pcie->csr_axi_slave_base + where; in mobiveil_pcie_map_bus()
70 value = bus->number << PAB_BUS_SHIFT | in mobiveil_pcie_map_bus()
76 return rp->config_axi_slave_base + where; in mobiveil_pcie_map_bus()
89 struct device *dev = &pcie->pdev->dev; in mobiveil_pcie_isr()
90 struct mobiveil_root_port *rp = &pcie->rp; in mobiveil_pcie_isr()
91 struct mobiveil_msi *msi = &rp->msi; in mobiveil_pcie_isr() local
98 * The core provides a single interrupt for both INTx/MSI messages. in mobiveil_pcie_isr()
99 * So we'll read both INTx and MSI status in mobiveil_pcie_isr()
118 ret = generic_handle_domain_irq(rp->intx_domain, in mobiveil_pcie_isr()
137 /* read extra MSI status register */ in mobiveil_pcie_isr()
138 msi_status = readl_relaxed(pcie->apb_csr_base + MSI_STATUS_OFFSET); in mobiveil_pcie_isr()
140 /* handle MSI interrupts */ in mobiveil_pcie_isr()
142 msi_data = readl_relaxed(pcie->apb_csr_base + MSI_DATA_OFFSET); in mobiveil_pcie_isr()
146 * once we pop not only the MSI data but also address in mobiveil_pcie_isr()
147 * from MSI hardware FIFO. So keeping these following in mobiveil_pcie_isr()
150 msi_addr_lo = readl_relaxed(pcie->apb_csr_base + in mobiveil_pcie_isr()
152 msi_addr_hi = readl_relaxed(pcie->apb_csr_base + in mobiveil_pcie_isr()
154 dev_dbg(dev, "MSI registers, data: %08x, addr: %08x:%08x\n", in mobiveil_pcie_isr()
157 generic_handle_domain_irq(msi->dev_domain, msi_data); in mobiveil_pcie_isr()
159 msi_status = readl_relaxed(pcie->apb_csr_base + in mobiveil_pcie_isr()
170 struct device *dev = &pcie->pdev->dev; in mobiveil_pcie_parse_dt()
171 struct platform_device *pdev = pcie->pdev; in mobiveil_pcie_parse_dt()
172 struct device_node *node = dev->of_node; in mobiveil_pcie_parse_dt()
173 struct mobiveil_root_port *rp = &pcie->rp; in mobiveil_pcie_parse_dt()
179 rp->config_axi_slave_base = devm_pci_remap_cfg_resource(dev, res); in mobiveil_pcie_parse_dt()
180 if (IS_ERR(rp->config_axi_slave_base)) in mobiveil_pcie_parse_dt()
181 return PTR_ERR(rp->config_axi_slave_base); in mobiveil_pcie_parse_dt()
182 rp->ob_io_res = res; in mobiveil_pcie_parse_dt()
187 pcie->csr_axi_slave_base = devm_pci_remap_cfg_resource(dev, res); in mobiveil_pcie_parse_dt()
188 if (IS_ERR(pcie->csr_axi_slave_base)) in mobiveil_pcie_parse_dt()
189 return PTR_ERR(pcie->csr_axi_slave_base); in mobiveil_pcie_parse_dt()
190 pcie->pcie_reg_base = res->start; in mobiveil_pcie_parse_dt()
193 if (of_property_read_u32(node, "apio-wins", &pcie->apio_wins)) in mobiveil_pcie_parse_dt()
194 pcie->apio_wins = MAX_PIO_WINDOWS; in mobiveil_pcie_parse_dt()
196 if (of_property_read_u32(node, "ppio-wins", &pcie->ppio_wins)) in mobiveil_pcie_parse_dt()
197 pcie->ppio_wins = MAX_PIO_WINDOWS; in mobiveil_pcie_parse_dt()
204 phys_addr_t msg_addr = pcie->pcie_reg_base; in mobiveil_pcie_enable_msi()
205 struct mobiveil_msi *msi = &pcie->rp.msi; in mobiveil_pcie_enable_msi() local
207 msi->num_of_vectors = PCI_NUM_MSI; in mobiveil_pcie_enable_msi()
208 msi->msi_pages_phys = (phys_addr_t)msg_addr; in mobiveil_pcie_enable_msi()
211 pcie->apb_csr_base + MSI_BASE_LO_OFFSET); in mobiveil_pcie_enable_msi()
213 pcie->apb_csr_base + MSI_BASE_HI_OFFSET); in mobiveil_pcie_enable_msi()
214 writel_relaxed(4096, pcie->apb_csr_base + MSI_SIZE_OFFSET); in mobiveil_pcie_enable_msi()
215 writel_relaxed(1, pcie->apb_csr_base + MSI_ENABLE_OFFSET); in mobiveil_pcie_enable_msi()
220 struct mobiveil_root_port *rp = &pcie->rp; in mobiveil_host_init()
221 struct pci_host_bridge *bridge = rp->bridge; in mobiveil_host_init()
225 pcie->ib_wins_configured = 0; in mobiveil_host_init()
226 pcie->ob_wins_configured = 0; in mobiveil_host_init()
273 program_ob_windows(pcie, WIN_NUM_0, rp->ob_io_res->start, 0, in mobiveil_host_init()
274 CFG_WINDOW_TYPE, resource_size(rp->ob_io_res)); in mobiveil_host_init()
280 resource_list_for_each_entry(win, &bridge->windows) { in mobiveil_host_init()
281 if (resource_type(win->res) == IORESOURCE_MEM) in mobiveil_host_init()
283 else if (resource_type(win->res) == IORESOURCE_IO) in mobiveil_host_init()
289 program_ob_windows(pcie, pcie->ob_wins_configured, in mobiveil_host_init()
290 win->res->start, in mobiveil_host_init()
291 win->res->start - win->offset, in mobiveil_host_init()
292 type, resource_size(win->res)); in mobiveil_host_init()
311 rp = &pcie->rp; in mobiveil_mask_intx_irq()
312 mask = 1 << ((data->hwirq + PAB_INTX_START) - 1); in mobiveil_mask_intx_irq()
313 raw_spin_lock_irqsave(&rp->intx_mask_lock, flags); in mobiveil_mask_intx_irq()
317 raw_spin_unlock_irqrestore(&rp->intx_mask_lock, flags); in mobiveil_mask_intx_irq()
327 rp = &pcie->rp; in mobiveil_unmask_intx_irq()
328 mask = 1 << ((data->hwirq + PAB_INTX_START) - 1); in mobiveil_unmask_intx_irq()
329 raw_spin_lock_irqsave(&rp->intx_mask_lock, flags); in mobiveil_unmask_intx_irq()
333 raw_spin_unlock_irqrestore(&rp->intx_mask_lock, flags); in mobiveil_unmask_intx_irq()
349 irq_set_chip_data(irq, domain->host_data); in mobiveil_pcie_intx_map()
360 .name = "Mobiveil PCIe MSI",
374 phys_addr_t addr = pcie->pcie_reg_base + (data->hwirq * sizeof(int)); in mobiveil_compose_msi_msg()
376 msg->address_lo = lower_32_bits(addr); in mobiveil_compose_msi_msg()
377 msg->address_hi = upper_32_bits(addr); in mobiveil_compose_msi_msg()
378 msg->data = data->hwirq; in mobiveil_compose_msi_msg()
380 dev_dbg(&pcie->pdev->dev, "msi#%d address_hi %#x address_lo %#x\n", in mobiveil_compose_msi_msg()
381 (int)data->hwirq, msg->address_hi, msg->address_lo); in mobiveil_compose_msi_msg()
387 return -EINVAL; in mobiveil_msi_set_affinity()
391 .name = "Mobiveil MSI",
400 struct mobiveil_pcie *pcie = domain->host_data; in mobiveil_irq_msi_domain_alloc()
401 struct mobiveil_msi *msi = &pcie->rp.msi; in mobiveil_irq_msi_domain_alloc() local
405 mutex_lock(&msi->lock); in mobiveil_irq_msi_domain_alloc()
407 bit = find_first_zero_bit(msi->msi_irq_in_use, msi->num_of_vectors); in mobiveil_irq_msi_domain_alloc()
408 if (bit >= msi->num_of_vectors) { in mobiveil_irq_msi_domain_alloc()
409 mutex_unlock(&msi->lock); in mobiveil_irq_msi_domain_alloc()
410 return -ENOSPC; in mobiveil_irq_msi_domain_alloc()
413 set_bit(bit, msi->msi_irq_in_use); in mobiveil_irq_msi_domain_alloc()
415 mutex_unlock(&msi->lock); in mobiveil_irq_msi_domain_alloc()
418 domain->host_data, handle_level_irq, NULL, NULL); in mobiveil_irq_msi_domain_alloc()
428 struct mobiveil_msi *msi = &pcie->rp.msi; in mobiveil_irq_msi_domain_free() local
430 mutex_lock(&msi->lock); in mobiveil_irq_msi_domain_free()
432 if (!test_bit(d->hwirq, msi->msi_irq_in_use)) in mobiveil_irq_msi_domain_free()
433 dev_err(&pcie->pdev->dev, "trying to free unused MSI#%lu\n", in mobiveil_irq_msi_domain_free()
434 d->hwirq); in mobiveil_irq_msi_domain_free()
436 __clear_bit(d->hwirq, msi->msi_irq_in_use); in mobiveil_irq_msi_domain_free()
438 mutex_unlock(&msi->lock); in mobiveil_irq_msi_domain_free()
447 struct device *dev = &pcie->pdev->dev; in mobiveil_allocate_msi_domains()
448 struct fwnode_handle *fwnode = of_node_to_fwnode(dev->of_node); in mobiveil_allocate_msi_domains()
449 struct mobiveil_msi *msi = &pcie->rp.msi; in mobiveil_allocate_msi_domains() local
451 mutex_init(&msi->lock); in mobiveil_allocate_msi_domains()
452 msi->dev_domain = irq_domain_add_linear(NULL, msi->num_of_vectors, in mobiveil_allocate_msi_domains()
454 if (!msi->dev_domain) { in mobiveil_allocate_msi_domains()
456 return -ENOMEM; in mobiveil_allocate_msi_domains()
459 msi->msi_domain = pci_msi_create_irq_domain(fwnode, in mobiveil_allocate_msi_domains()
461 msi->dev_domain); in mobiveil_allocate_msi_domains()
462 if (!msi->msi_domain) { in mobiveil_allocate_msi_domains()
463 dev_err(dev, "failed to create MSI domain\n"); in mobiveil_allocate_msi_domains()
464 irq_domain_remove(msi->dev_domain); in mobiveil_allocate_msi_domains()
465 return -ENOMEM; in mobiveil_allocate_msi_domains()
473 struct device *dev = &pcie->pdev->dev; in mobiveil_pcie_init_irq_domain()
474 struct device_node *node = dev->of_node; in mobiveil_pcie_init_irq_domain()
475 struct mobiveil_root_port *rp = &pcie->rp; in mobiveil_pcie_init_irq_domain()
478 rp->intx_domain = irq_domain_add_linear(node, PCI_NUM_INTX, in mobiveil_pcie_init_irq_domain()
481 if (!rp->intx_domain) { in mobiveil_pcie_init_irq_domain()
483 return -ENOMEM; in mobiveil_pcie_init_irq_domain()
486 raw_spin_lock_init(&rp->intx_mask_lock); in mobiveil_pcie_init_irq_domain()
488 /* setup MSI */ in mobiveil_pcie_init_irq_domain()
494 struct platform_device *pdev = pcie->pdev; in mobiveil_pcie_integrated_interrupt_init()
495 struct device *dev = &pdev->dev; in mobiveil_pcie_integrated_interrupt_init()
496 struct mobiveil_root_port *rp = &pcie->rp; in mobiveil_pcie_integrated_interrupt_init()
500 /* map MSI config resource */ in mobiveil_pcie_integrated_interrupt_init()
502 pcie->apb_csr_base = devm_pci_remap_cfg_resource(dev, res); in mobiveil_pcie_integrated_interrupt_init()
503 if (IS_ERR(pcie->apb_csr_base)) in mobiveil_pcie_integrated_interrupt_init()
504 return PTR_ERR(pcie->apb_csr_base); in mobiveil_pcie_integrated_interrupt_init()
506 /* setup MSI hardware registers */ in mobiveil_pcie_integrated_interrupt_init()
509 rp->irq = platform_get_irq(pdev, 0); in mobiveil_pcie_integrated_interrupt_init()
510 if (rp->irq < 0) in mobiveil_pcie_integrated_interrupt_init()
511 return rp->irq; in mobiveil_pcie_integrated_interrupt_init()
520 irq_set_chained_handler_and_data(rp->irq, mobiveil_pcie_isr, pcie); in mobiveil_pcie_integrated_interrupt_init()
532 struct mobiveil_root_port *rp = &pcie->rp; in mobiveil_pcie_interrupt_init()
534 if (rp->ops->interrupt_init) in mobiveil_pcie_interrupt_init()
535 return rp->ops->interrupt_init(pcie); in mobiveil_pcie_interrupt_init()
552 struct mobiveil_root_port *rp = &pcie->rp; in mobiveil_pcie_host_probe()
553 struct pci_host_bridge *bridge = rp->bridge; in mobiveil_pcie_host_probe()
554 struct device *dev = &pcie->pdev->dev; in mobiveil_pcie_host_probe()
559 dev_err(dev, "Parsing DT failed, ret: %x\n", ret); in mobiveil_pcie_host_probe()
564 return -ENODEV; in mobiveil_pcie_host_probe()
583 bridge->sysdata = pcie; in mobiveil_pcie_host_probe()
584 bridge->ops = &mobiveil_pcie_ops; in mobiveil_pcie_host_probe()
588 dev_info(dev, "link bring-up failed\n"); in mobiveil_pcie_host_probe()