1 // SPDX-License-Identifier: GPL-2.0
3  * PCIe Gen4 host controller driver for NXP Layerscape SoCs
5  * Copyright 2019-2020 NXP
20 #include <linux/mfd/syscon.h>
23 #include "pcie-mobiveil.h"
37 #define to_ls_g4_pcie(x)		platform_get_drvdata((x)->pdev)
45 static inline u32 ls_g4_pcie_pf_readl(struct ls_g4_pcie *pcie, u32 off)  in ls_g4_pcie_pf_readl()  argument
47 	return ioread32(pcie->pci.csr_axi_slave_base + PCIE_PF_OFF + off);  in ls_g4_pcie_pf_readl()
50 static inline void ls_g4_pcie_pf_writel(struct ls_g4_pcie *pcie,  in ls_g4_pcie_pf_writel()  argument
53 	iowrite32(val, pcie->pci.csr_axi_slave_base + PCIE_PF_OFF + off);  in ls_g4_pcie_pf_writel()
58 	struct ls_g4_pcie *pcie = to_ls_g4_pcie(pci);  in ls_g4_pcie_link_up()  local
61 	state = ls_g4_pcie_pf_readl(pcie, PCIE_PF_DBG);  in ls_g4_pcie_link_up()
70 static void ls_g4_pcie_disable_interrupt(struct ls_g4_pcie *pcie)  in ls_g4_pcie_disable_interrupt()  argument
72 	struct mobiveil_pcie *mv_pci = &pcie->pci;  in ls_g4_pcie_disable_interrupt()
77 static void ls_g4_pcie_enable_interrupt(struct ls_g4_pcie *pcie)  in ls_g4_pcie_enable_interrupt()  argument
79 	struct mobiveil_pcie *mv_pci = &pcie->pci;  in ls_g4_pcie_enable_interrupt()
90 static int ls_g4_pcie_reinit_hw(struct ls_g4_pcie *pcie)  in ls_g4_pcie_reinit_hw()  argument
92 	struct mobiveil_pcie *mv_pci = &pcie->pci;  in ls_g4_pcie_reinit_hw()
93 	struct device *dev = &mv_pci->pdev->dev;  in ls_g4_pcie_reinit_hw()
100 		val = ls_g4_pcie_pf_readl(pcie, PCIE_PF_INT_STAT);  in ls_g4_pcie_reinit_hw()
102 	} while (((val & PF_INT_STAT_PABRST) == 0 || act_stat) && to--);  in ls_g4_pcie_reinit_hw()
105 		return -EIO;  in ls_g4_pcie_reinit_hw()
109 	val = ls_g4_pcie_pf_readl(pcie, PCIE_PF_DBG);  in ls_g4_pcie_reinit_hw()
111 	ls_g4_pcie_pf_writel(pcie, PCIE_PF_DBG, val);  in ls_g4_pcie_reinit_hw()
113 	val = ls_g4_pcie_pf_readl(pcie, PCIE_PF_DBG);  in ls_g4_pcie_reinit_hw()
115 	ls_g4_pcie_pf_writel(pcie, PCIE_PF_DBG, val);  in ls_g4_pcie_reinit_hw()
117 	val = ls_g4_pcie_pf_readl(pcie, PCIE_PF_DBG);  in ls_g4_pcie_reinit_hw()
119 	ls_g4_pcie_pf_writel(pcie, PCIE_PF_DBG, val);  in ls_g4_pcie_reinit_hw()
124 	while (!ls_g4_pcie_link_up(mv_pci) && to--)  in ls_g4_pcie_reinit_hw()
127 		dev_err(dev, "PCIe link training timeout\n");  in ls_g4_pcie_reinit_hw()
128 		return -EIO;  in ls_g4_pcie_reinit_hw()
136 	struct ls_g4_pcie *pcie = (struct ls_g4_pcie *)dev_id;  in ls_g4_pcie_isr()  local
137 	struct mobiveil_pcie *mv_pci = &pcie->pci;  in ls_g4_pcie_isr()
145 		ls_g4_pcie_disable_interrupt(pcie);  in ls_g4_pcie_isr()
146 		schedule_delayed_work(&pcie->dwork, msecs_to_jiffies(1));  in ls_g4_pcie_isr()
156 	struct ls_g4_pcie *pcie = to_ls_g4_pcie(mv_pci);  in ls_g4_pcie_interrupt_init()  local
157 	struct platform_device *pdev = mv_pci->pdev;  in ls_g4_pcie_interrupt_init()
158 	struct device *dev = &pdev->dev;  in ls_g4_pcie_interrupt_init()
161 	pcie->irq = platform_get_irq_byname(pdev, "intr");  in ls_g4_pcie_interrupt_init()
162 	if (pcie->irq < 0)  in ls_g4_pcie_interrupt_init()
163 		return pcie->irq;  in ls_g4_pcie_interrupt_init()
165 	ret = devm_request_irq(dev, pcie->irq, ls_g4_pcie_isr,  in ls_g4_pcie_interrupt_init()
166 			       IRQF_SHARED, pdev->name, pcie);  in ls_g4_pcie_interrupt_init()
168 		dev_err(dev, "Can't register PCIe IRQ, errno = %d\n", ret);  in ls_g4_pcie_interrupt_init()
179 	struct ls_g4_pcie *pcie = container_of(dwork, struct ls_g4_pcie, dwork);  in ls_g4_pcie_reset()  local
180 	struct mobiveil_pcie *mv_pci = &pcie->pci;  in ls_g4_pcie_reset()
181 	u16 ctrl;  in ls_g4_pcie_reset()  local
183 	ctrl = mobiveil_csr_readw(mv_pci, PCI_BRIDGE_CONTROL);  in ls_g4_pcie_reset()
184 	ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;  in ls_g4_pcie_reset()
185 	mobiveil_csr_writew(mv_pci, ctrl, PCI_BRIDGE_CONTROL);  in ls_g4_pcie_reset()
187 	if (!ls_g4_pcie_reinit_hw(pcie))  in ls_g4_pcie_reset()
190 	ls_g4_pcie_enable_interrupt(pcie);  in ls_g4_pcie_reset()
203 	struct device *dev = &pdev->dev;  in ls_g4_pcie_probe()
206 	struct ls_g4_pcie *pcie;  in ls_g4_pcie_probe()  local
207 	struct device_node *np = dev->of_node;  in ls_g4_pcie_probe()
210 	if (!of_parse_phandle(np, "msi-parent", 0)) {  in ls_g4_pcie_probe()
211 		dev_err(dev, "Failed to find msi-parent\n");  in ls_g4_pcie_probe()
212 		return -EINVAL;  in ls_g4_pcie_probe()
215 	bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));  in ls_g4_pcie_probe()
217 		return -ENOMEM;  in ls_g4_pcie_probe()
219 	pcie = pci_host_bridge_priv(bridge);  in ls_g4_pcie_probe()
220 	mv_pci = &pcie->pci;  in ls_g4_pcie_probe()
222 	mv_pci->pdev = pdev;  in ls_g4_pcie_probe()
223 	mv_pci->ops = &ls_g4_pcie_pab_ops;  in ls_g4_pcie_probe()
224 	mv_pci->rp.ops = &ls_g4_pcie_rp_ops;  in ls_g4_pcie_probe()
225 	mv_pci->rp.bridge = bridge;  in ls_g4_pcie_probe()
227 	platform_set_drvdata(pdev, pcie);  in ls_g4_pcie_probe()
229 	INIT_DELAYED_WORK(&pcie->dwork, ls_g4_pcie_reset);  in ls_g4_pcie_probe()
237 	ls_g4_pcie_enable_interrupt(pcie);  in ls_g4_pcie_probe()
243 	{ .compatible = "fsl,lx2160a-pcie", },
249 		.name = "layerscape-pcie-gen4",