50 #define APPL_CTRL				0x4  macro
445 	val = appl_readl(pcie, APPL_CTRL);  in pex_ep_event_hot_rst_done()
447 	appl_writel(pcie, val, APPL_CTRL);  in pex_ep_event_hot_rst_done()
963 	val = appl_readl(pcie, APPL_CTRL);  in tegra_pcie_dw_start_link()
965 	appl_writel(pcie, val, APPL_CTRL);  in tegra_pcie_dw_start_link()
998 		val = appl_readl(pcie, APPL_CTRL);  in tegra_pcie_dw_start_link()
1000 		appl_writel(pcie, val, APPL_CTRL);  in tegra_pcie_dw_start_link()
1408 		val = appl_readl(pcie, APPL_CTRL);  in tegra_pcie_config_controller()
1414 		appl_writel(pcie, val, APPL_CTRL);  in tegra_pcie_config_controller()
1432 	val = appl_readl(pcie, APPL_CTRL);  in tegra_pcie_config_controller()
1433 	appl_writel(pcie, val | APPL_CTRL_SYS_PRE_DET_STATE, APPL_CTRL);  in tegra_pcie_config_controller()
1596 		data = readl(pcie->appl_base + APPL_CTRL);  in tegra_pcie_dw_pme_turnoff()
1598 		writel(data, pcie->appl_base + APPL_CTRL);  in tegra_pcie_dw_pme_turnoff()
1691 	val = appl_readl(pcie, APPL_CTRL);  in pex_ep_event_pex_rst_assert()
1693 	appl_writel(pcie, val, APPL_CTRL);  in pex_ep_event_pex_rst_assert()
1806 	val = appl_readl(pcie, APPL_CTRL);  in pex_ep_event_pex_rst_deassert()
1809 	appl_writel(pcie, val, APPL_CTRL);  in pex_ep_event_pex_rst_deassert()
1904 	val = appl_readl(pcie, APPL_CTRL);  in pex_ep_event_pex_rst_deassert()
1906 	appl_writel(pcie, val, APPL_CTRL);  in pex_ep_event_pex_rst_deassert()
2306 		val = appl_readl(pcie, APPL_CTRL);  in tegra_pcie_dw_suspend_late()
2310 		appl_writel(pcie, val, APPL_CTRL);  in tegra_pcie_dw_suspend_late()
2376 		val = appl_readl(pcie, APPL_CTRL);  in tegra_pcie_dw_resume_early()
2382 		appl_writel(pcie, val, APPL_CTRL);  in tegra_pcie_dw_resume_early()