Lines Matching +full:bpmp +full:- +full:bus +full:- +full:id
1 // SPDX-License-Identifier: GPL-2.0+
7 * Copyright (C) 2019-2022 NVIDIA Corporation.
35 #include "pcie-designware.h"
36 #include <soc/tegra/bpmp.h>
37 #include <soc/tegra/bpmp-abi.h>
255 struct tegra_bpmp *bpmp; member
300 writel_relaxed(value, pcie->appl_base + reg); in appl_writel()
305 return readl_relaxed(pcie->appl_base + reg); in appl_readl()
320 * NOTE:- Since this scenario is uncommon and link as such is not in apply_bad_link_workaround()
322 * transitioning to Gen-2 speed in apply_bad_link_workaround()
324 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA); in apply_bad_link_workaround()
328 if (pcie->init_link_width > current_link_width) { in apply_bad_link_workaround()
329 dev_warn(pci->dev, "PCIe link is bad, width reduced\n"); in apply_bad_link_workaround()
330 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + in apply_bad_link_workaround()
334 dw_pcie_writew_dbi(pci, pcie->pcie_cap_base + in apply_bad_link_workaround()
337 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + in apply_bad_link_workaround()
340 dw_pcie_writew_dbi(pci, pcie->pcie_cap_base + in apply_bad_link_workaround()
349 struct dw_pcie *pci = &pcie->pci; in tegra_pcie_rp_irq_handler()
350 struct dw_pcie_rp *pp = &pci->pp; in tegra_pcie_rp_irq_handler()
358 if (!pcie->of_data->has_sbr_reset_fix && in tegra_pcie_rp_irq_handler()
384 val_w = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + in tegra_pcie_rp_irq_handler()
387 dw_pcie_writew_dbi(pci, pcie->pcie_cap_base + in tegra_pcie_rp_irq_handler()
394 val_w = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + in tegra_pcie_rp_irq_handler()
396 dev_dbg(pci->dev, "Link Speed : Gen-%u\n", val_w & in tegra_pcie_rp_irq_handler()
405 dev_info(pci->dev, "CDM check complete\n"); in tegra_pcie_rp_irq_handler()
409 dev_err(pci->dev, "CDM comparison mismatch\n"); in tegra_pcie_rp_irq_handler()
413 dev_err(pci->dev, "CDM Logic error\n"); in tegra_pcie_rp_irq_handler()
418 dev_err(pci->dev, "CDM Error Address Offset = 0x%08X\n", val); in tegra_pcie_rp_irq_handler()
453 struct dw_pcie *pci = &pcie->pci; in tegra_pcie_ep_irq_thread()
456 speed = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA) & in tegra_pcie_ep_irq_thread()
458 clk_set_rate(pcie->core_clk, pcie_gen_freq[speed - 1]); in tegra_pcie_ep_irq_thread()
460 if (pcie->of_data->has_ltr_req_fix) in tegra_pcie_ep_irq_thread()
464 val = dw_pcie_readl_dbi(pci, pcie->cfg_link_cap_l1sub); in tegra_pcie_ep_irq_thread()
473 /* 110us for both snoop and no-snoop */ in tegra_pcie_ep_irq_thread()
493 dev_err(pcie->dev, "Failed to send LTR message\n"); in tegra_pcie_ep_irq_thread()
502 struct dw_pcie_ep *ep = &pcie->pci.ep; in tegra_pcie_ep_hard_irq()
517 dev_dbg(pcie->dev, "Link is up with Host\n"); in tegra_pcie_ep_hard_irq()
536 dev_warn(pcie->dev, "Random interrupt (STATUS = 0x%08X)\n", in tegra_pcie_ep_hard_irq()
544 static int tegra_pcie_dw_rd_own_conf(struct pci_bus *bus, u32 devfn, int where, in tegra_pcie_dw_rd_own_conf() argument
547 struct dw_pcie_rp *pp = bus->sysdata; in tegra_pcie_dw_rd_own_conf()
554 * when it is accessed with link being in ASPM-L1 state. in tegra_pcie_dw_rd_own_conf()
557 if (!pcie->of_data->has_msix_doorbell_access_fix && in tegra_pcie_dw_rd_own_conf()
563 return pci_generic_config_read(bus, devfn, where, size, val); in tegra_pcie_dw_rd_own_conf()
566 static int tegra_pcie_dw_wr_own_conf(struct pci_bus *bus, u32 devfn, int where, in tegra_pcie_dw_wr_own_conf() argument
569 struct dw_pcie_rp *pp = bus->sysdata; in tegra_pcie_dw_wr_own_conf()
576 * when it is accessed with link being in ASPM-L1 state. in tegra_pcie_dw_wr_own_conf()
579 if (!pcie->of_data->has_msix_doorbell_access_fix && in tegra_pcie_dw_wr_own_conf()
583 return pci_generic_config_write(bus, devfn, where, size, val); in tegra_pcie_dw_wr_own_conf()
597 val = dw_pcie_readl_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub); in disable_aspm_l11()
599 dw_pcie_writel_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub, val); in disable_aspm_l11()
606 val = dw_pcie_readl_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub); in disable_aspm_l12()
608 dw_pcie_writel_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub, val); in disable_aspm_l12()
615 val = dw_pcie_readl_dbi(&pcie->pci, pcie->ras_des_cap + in event_counter_prog()
621 dw_pcie_writel_dbi(&pcie->pci, pcie->ras_des_cap + in event_counter_prog()
623 val = dw_pcie_readl_dbi(&pcie->pci, pcie->ras_des_cap + in event_counter_prog()
632 dev_get_drvdata(s->private); in aspm_state_cnt()
651 dw_pcie_writel_dbi(&pcie->pci, pcie->ras_des_cap + in aspm_state_cnt()
655 /* Re-enable counting */ in aspm_state_cnt()
658 dw_pcie_writel_dbi(&pcie->pci, pcie->ras_des_cap + in aspm_state_cnt()
666 struct dw_pcie *pci = &pcie->pci; in init_host_aspm()
670 pcie->cfg_link_cap_l1sub = val + PCI_L1SS_CAP; in init_host_aspm()
672 pcie->ras_des_cap = dw_pcie_find_ext_capability(&pcie->pci, in init_host_aspm()
678 dw_pcie_writel_dbi(pci, pcie->ras_des_cap + in init_host_aspm()
682 val = dw_pcie_readl_dbi(pci, pcie->cfg_link_cap_l1sub); in init_host_aspm()
684 val |= (pcie->aspm_cmrt << 8); in init_host_aspm()
685 val |= (pcie->aspm_pwr_on_t << 19); in init_host_aspm()
686 dw_pcie_writel_dbi(pci, pcie->cfg_link_cap_l1sub, val); in init_host_aspm()
691 val |= (pcie->aspm_l0s_enter_lat << PORT_AFR_L0S_ENTRANCE_LAT_SHIFT); in init_host_aspm()
698 debugfs_create_devm_seqfile(pcie->dev, "aspm_state_cnt", pcie->debugfs, in init_debugfs()
719 if (!pcie->of_data->has_sbr_reset_fix) { in tegra_pcie_enable_system_interrupts()
725 if (pcie->enable_cdm_check) { in tegra_pcie_enable_system_interrupts()
727 val |= pcie->of_data->cdm_chk_int_en_bit; in tegra_pcie_enable_system_interrupts()
736 val_w = dw_pcie_readw_dbi(&pcie->pci, pcie->pcie_cap_base + in tegra_pcie_enable_system_interrupts()
738 pcie->init_link_width = (val_w & PCI_EXP_LNKSTA_NLW) >> in tegra_pcie_enable_system_interrupts()
741 val_w = dw_pcie_readw_dbi(&pcie->pci, pcie->pcie_cap_base + in tegra_pcie_enable_system_interrupts()
744 dw_pcie_writew_dbi(&pcie->pci, pcie->pcie_cap_base + PCI_EXP_LNKCTL, in tegra_pcie_enable_system_interrupts()
812 struct dw_pcie *pci = &pcie->pci; in config_gen3_gen4_eq_presets()
816 for (i = 0; i < pcie->num_lanes; i++) { in config_gen3_gen4_eq_presets()
854 val |= (pcie->of_data->gen4_preset_vec << in config_gen3_gen4_eq_presets()
871 pp->bridge->ops = &tegra_pci_ops; in tegra_pcie_dw_host_init()
873 if (!pcie->pcie_cap_base) in tegra_pcie_dw_host_init()
874 pcie->pcie_cap_base = dw_pcie_find_capability(&pcie->pci, in tegra_pcie_dw_host_init()
877 val_16 = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_DEVCTL); in tegra_pcie_dw_host_init()
880 dw_pcie_writew_dbi(pci, pcie->pcie_cap_base + PCI_EXP_DEVCTL, val_16); in tegra_pcie_dw_host_init()
901 val = dw_pcie_readl_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKCAP); in tegra_pcie_dw_host_init()
903 val |= (pcie->num_lanes << PCI_EXP_LNKSTA_NLW_SHIFT); in tegra_pcie_dw_host_init()
904 dw_pcie_writel_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKCAP, val); in tegra_pcie_dw_host_init()
907 if (pcie->enable_srns) { in tegra_pcie_dw_host_init()
908 val_16 = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + in tegra_pcie_dw_host_init()
911 dw_pcie_writew_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA, in tegra_pcie_dw_host_init()
919 /* Disable ASPM-L1SS advertisement if there is no CLKREQ routing */ in tegra_pcie_dw_host_init()
920 if (!pcie->supports_clkreq) { in tegra_pcie_dw_host_init()
925 if (!pcie->of_data->has_l1ss_exit_fix) { in tegra_pcie_dw_host_init()
931 if (pcie->update_fc_fixup) { in tegra_pcie_dw_host_init()
937 clk_set_rate(pcie->core_clk, GEN4_CORE_CLK_FREQ); in tegra_pcie_dw_host_init()
946 struct dw_pcie_rp *pp = &pci->pp; in tegra_pcie_dw_start_link()
949 if (pcie->of_data->mode == DW_PCIE_EP_TYPE) { in tegra_pcie_dw_start_link()
950 enable_irq(pcie->pex_rst_irq); in tegra_pcie_dw_start_link()
967 /* De-assert RST */ in tegra_pcie_dw_start_link()
995 dev_info(pci->dev, "Link is down in DLL"); in tegra_pcie_dw_start_link()
996 dev_info(pci->dev, "Trying again with DLFE disabled\n"); in tegra_pcie_dw_start_link()
1002 reset_control_assert(pcie->core_rst); in tegra_pcie_dw_start_link()
1003 reset_control_deassert(pcie->core_rst); in tegra_pcie_dw_start_link()
1017 speed = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA) & in tegra_pcie_dw_start_link()
1019 clk_set_rate(pcie->core_clk, pcie_gen_freq[speed - 1]); in tegra_pcie_dw_start_link()
1029 u32 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA); in tegra_pcie_dw_link_up()
1038 disable_irq(pcie->pex_rst_irq); in tegra_pcie_dw_stop_link()
1053 unsigned int phy_count = pcie->phy_count; in tegra_pcie_disable_phy()
1055 while (phy_count--) { in tegra_pcie_disable_phy()
1056 phy_power_off(pcie->phys[phy_count]); in tegra_pcie_disable_phy()
1057 phy_exit(pcie->phys[phy_count]); in tegra_pcie_disable_phy()
1066 for (i = 0; i < pcie->phy_count; i++) { in tegra_pcie_enable_phy()
1067 ret = phy_init(pcie->phys[i]); in tegra_pcie_enable_phy()
1071 ret = phy_power_on(pcie->phys[i]); in tegra_pcie_enable_phy()
1079 while (i--) { in tegra_pcie_enable_phy()
1080 phy_power_off(pcie->phys[i]); in tegra_pcie_enable_phy()
1082 phy_exit(pcie->phys[i]); in tegra_pcie_enable_phy()
1090 struct platform_device *pdev = to_platform_device(pcie->dev); in tegra_pcie_dw_parse_dt()
1091 struct device_node *np = pcie->dev->of_node; in tegra_pcie_dw_parse_dt()
1094 pcie->dbi_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi"); in tegra_pcie_dw_parse_dt()
1095 if (!pcie->dbi_res) { in tegra_pcie_dw_parse_dt()
1096 dev_err(pcie->dev, "Failed to find \"dbi\" region\n"); in tegra_pcie_dw_parse_dt()
1097 return -ENODEV; in tegra_pcie_dw_parse_dt()
1100 ret = of_property_read_u32(np, "nvidia,aspm-cmrt-us", &pcie->aspm_cmrt); in tegra_pcie_dw_parse_dt()
1102 dev_info(pcie->dev, "Failed to read ASPM T_cmrt: %d\n", ret); in tegra_pcie_dw_parse_dt()
1106 ret = of_property_read_u32(np, "nvidia,aspm-pwr-on-t-us", in tegra_pcie_dw_parse_dt()
1107 &pcie->aspm_pwr_on_t); in tegra_pcie_dw_parse_dt()
1109 dev_info(pcie->dev, "Failed to read ASPM Power On time: %d\n", in tegra_pcie_dw_parse_dt()
1112 ret = of_property_read_u32(np, "nvidia,aspm-l0s-entrance-latency-us", in tegra_pcie_dw_parse_dt()
1113 &pcie->aspm_l0s_enter_lat); in tegra_pcie_dw_parse_dt()
1115 dev_info(pcie->dev, in tegra_pcie_dw_parse_dt()
1118 ret = of_property_read_u32(np, "num-lanes", &pcie->num_lanes); in tegra_pcie_dw_parse_dt()
1120 dev_err(pcie->dev, "Failed to read num-lanes: %d\n", ret); in tegra_pcie_dw_parse_dt()
1124 ret = of_property_read_u32_index(np, "nvidia,bpmp", 1, &pcie->cid); in tegra_pcie_dw_parse_dt()
1126 dev_err(pcie->dev, "Failed to read Controller-ID: %d\n", ret); in tegra_pcie_dw_parse_dt()
1130 ret = of_property_count_strings(np, "phy-names"); in tegra_pcie_dw_parse_dt()
1132 dev_err(pcie->dev, "Failed to find PHY entries: %d\n", in tegra_pcie_dw_parse_dt()
1136 pcie->phy_count = ret; in tegra_pcie_dw_parse_dt()
1138 if (of_property_read_bool(np, "nvidia,update-fc-fixup")) in tegra_pcie_dw_parse_dt()
1139 pcie->update_fc_fixup = true; in tegra_pcie_dw_parse_dt()
1142 if (pcie->of_data->version == TEGRA194_DWC_IP_VER) { in tegra_pcie_dw_parse_dt()
1143 if (pcie->of_data->mode == DW_PCIE_EP_TYPE) in tegra_pcie_dw_parse_dt()
1144 pcie->enable_ext_refclk = true; in tegra_pcie_dw_parse_dt()
1146 pcie->enable_ext_refclk = in tegra_pcie_dw_parse_dt()
1147 of_property_read_bool(pcie->dev->of_node, in tegra_pcie_dw_parse_dt()
1148 "nvidia,enable-ext-refclk"); in tegra_pcie_dw_parse_dt()
1151 pcie->supports_clkreq = in tegra_pcie_dw_parse_dt()
1152 of_property_read_bool(pcie->dev->of_node, "supports-clkreq"); in tegra_pcie_dw_parse_dt()
1154 pcie->enable_cdm_check = in tegra_pcie_dw_parse_dt()
1155 of_property_read_bool(np, "snps,enable-cdm-check"); in tegra_pcie_dw_parse_dt()
1157 if (pcie->of_data->version == TEGRA234_DWC_IP_VER) in tegra_pcie_dw_parse_dt()
1158 pcie->enable_srns = in tegra_pcie_dw_parse_dt()
1159 of_property_read_bool(np, "nvidia,enable-srns"); in tegra_pcie_dw_parse_dt()
1161 if (pcie->of_data->mode == DW_PCIE_RC_TYPE) in tegra_pcie_dw_parse_dt()
1165 pcie->pex_rst_gpiod = devm_gpiod_get(pcie->dev, "reset", GPIOD_IN); in tegra_pcie_dw_parse_dt()
1166 if (IS_ERR(pcie->pex_rst_gpiod)) { in tegra_pcie_dw_parse_dt()
1167 int err = PTR_ERR(pcie->pex_rst_gpiod); in tegra_pcie_dw_parse_dt()
1170 if (err == -EPROBE_DEFER) in tegra_pcie_dw_parse_dt()
1173 dev_printk(level, pcie->dev, in tegra_pcie_dw_parse_dt()
1179 pcie->pex_refclk_sel_gpiod = devm_gpiod_get(pcie->dev, in tegra_pcie_dw_parse_dt()
1180 "nvidia,refclk-select", in tegra_pcie_dw_parse_dt()
1182 if (IS_ERR(pcie->pex_refclk_sel_gpiod)) { in tegra_pcie_dw_parse_dt()
1183 int err = PTR_ERR(pcie->pex_refclk_sel_gpiod); in tegra_pcie_dw_parse_dt()
1186 if (err == -EPROBE_DEFER) in tegra_pcie_dw_parse_dt()
1189 dev_printk(level, pcie->dev, in tegra_pcie_dw_parse_dt()
1192 pcie->pex_refclk_sel_gpiod = NULL; in tegra_pcie_dw_parse_dt()
1206 * Controller-5 doesn't need to have its state set by BPMP-FW in in tegra_pcie_bpmp_set_ctrl_state()
1209 if (pcie->of_data->version == TEGRA194_DWC_IP_VER && pcie->cid == 5) in tegra_pcie_bpmp_set_ctrl_state()
1216 req.controller_state.pcie_controller = pcie->cid; in tegra_pcie_bpmp_set_ctrl_state()
1226 return tegra_bpmp_transfer(pcie->bpmp, &msg); in tegra_pcie_bpmp_set_ctrl_state()
1241 req.ep_ctrlr_pll_init.ep_controller = pcie->cid; in tegra_pcie_bpmp_set_pll_state()
1244 req.ep_ctrlr_pll_off.ep_controller = pcie->cid; in tegra_pcie_bpmp_set_pll_state()
1254 return tegra_bpmp_transfer(pcie->bpmp, &msg); in tegra_pcie_bpmp_set_pll_state()
1259 struct dw_pcie_rp *pp = &pcie->pci.pp; in tegra_pcie_downstream_dev_to_D0()
1268 * This is as per PCI Express Base r4.0 v1.0 September 27-2017, in tegra_pcie_downstream_dev_to_D0()
1272 list_for_each_entry(child, &pp->bridge->bus->children, node) { in tegra_pcie_downstream_dev_to_D0()
1274 if (child->parent == pp->bridge->bus) { in tegra_pcie_downstream_dev_to_D0()
1281 dev_err(pcie->dev, "Failed to find downstream devices\n"); in tegra_pcie_downstream_dev_to_D0()
1285 list_for_each_entry(pdev, &root_bus->devices, bus_list) { in tegra_pcie_downstream_dev_to_D0()
1286 if (PCI_SLOT(pdev->devfn) == 0) { in tegra_pcie_downstream_dev_to_D0()
1288 dev_err(pcie->dev, in tegra_pcie_downstream_dev_to_D0()
1290 dev_name(&pdev->dev)); in tegra_pcie_downstream_dev_to_D0()
1297 pcie->slot_ctl_3v3 = devm_regulator_get_optional(pcie->dev, "vpcie3v3"); in tegra_pcie_get_slot_regulators()
1298 if (IS_ERR(pcie->slot_ctl_3v3)) { in tegra_pcie_get_slot_regulators()
1299 if (PTR_ERR(pcie->slot_ctl_3v3) != -ENODEV) in tegra_pcie_get_slot_regulators()
1300 return PTR_ERR(pcie->slot_ctl_3v3); in tegra_pcie_get_slot_regulators()
1302 pcie->slot_ctl_3v3 = NULL; in tegra_pcie_get_slot_regulators()
1305 pcie->slot_ctl_12v = devm_regulator_get_optional(pcie->dev, "vpcie12v"); in tegra_pcie_get_slot_regulators()
1306 if (IS_ERR(pcie->slot_ctl_12v)) { in tegra_pcie_get_slot_regulators()
1307 if (PTR_ERR(pcie->slot_ctl_12v) != -ENODEV) in tegra_pcie_get_slot_regulators()
1308 return PTR_ERR(pcie->slot_ctl_12v); in tegra_pcie_get_slot_regulators()
1310 pcie->slot_ctl_12v = NULL; in tegra_pcie_get_slot_regulators()
1320 if (pcie->slot_ctl_3v3) { in tegra_pcie_enable_slot_regulators()
1321 ret = regulator_enable(pcie->slot_ctl_3v3); in tegra_pcie_enable_slot_regulators()
1323 dev_err(pcie->dev, in tegra_pcie_enable_slot_regulators()
1329 if (pcie->slot_ctl_12v) { in tegra_pcie_enable_slot_regulators()
1330 ret = regulator_enable(pcie->slot_ctl_12v); in tegra_pcie_enable_slot_regulators()
1332 dev_err(pcie->dev, in tegra_pcie_enable_slot_regulators()
1340 * Revision 1.1, Table-2.4, T_PVPERL (Power stable to PERST# inactive) in tegra_pcie_enable_slot_regulators()
1343 if (pcie->slot_ctl_3v3 || pcie->slot_ctl_12v) in tegra_pcie_enable_slot_regulators()
1349 if (pcie->slot_ctl_3v3) in tegra_pcie_enable_slot_regulators()
1350 regulator_disable(pcie->slot_ctl_3v3); in tegra_pcie_enable_slot_regulators()
1356 if (pcie->slot_ctl_12v) in tegra_pcie_disable_slot_regulators()
1357 regulator_disable(pcie->slot_ctl_12v); in tegra_pcie_disable_slot_regulators()
1358 if (pcie->slot_ctl_3v3) in tegra_pcie_disable_slot_regulators()
1359 regulator_disable(pcie->slot_ctl_3v3); in tegra_pcie_disable_slot_regulators()
1370 dev_err(pcie->dev, in tegra_pcie_config_controller()
1371 "Failed to enable controller %u: %d\n", pcie->cid, ret); in tegra_pcie_config_controller()
1375 if (pcie->enable_ext_refclk) { in tegra_pcie_config_controller()
1378 dev_err(pcie->dev, "Failed to init UPHY: %d\n", ret); in tegra_pcie_config_controller()
1387 ret = regulator_enable(pcie->pex_ctl_supply); in tegra_pcie_config_controller()
1389 dev_err(pcie->dev, "Failed to enable regulator: %d\n", ret); in tegra_pcie_config_controller()
1393 ret = clk_prepare_enable(pcie->core_clk); in tegra_pcie_config_controller()
1395 dev_err(pcie->dev, "Failed to enable core clock: %d\n", ret); in tegra_pcie_config_controller()
1399 ret = reset_control_deassert(pcie->core_apb_rst); in tegra_pcie_config_controller()
1401 dev_err(pcie->dev, "Failed to deassert core APB reset: %d\n", in tegra_pcie_config_controller()
1406 if (en_hw_hot_rst || pcie->of_data->has_sbr_reset_fix) { in tegra_pcie_config_controller()
1419 dev_err(pcie->dev, "Failed to enable PHY: %d\n", ret); in tegra_pcie_config_controller()
1424 appl_writel(pcie, pcie->dbi_res->start & APPL_CFG_BASE_ADDR_MASK, in tegra_pcie_config_controller()
1439 if (pcie->enable_srns || pcie->enable_ext_refclk) { in tegra_pcie_config_controller()
1452 if (!pcie->supports_clkreq) { in tegra_pcie_config_controller()
1461 pcie->atu_dma_res->start & APPL_CFG_IATU_DMA_BASE_ADDR_MASK, in tegra_pcie_config_controller()
1464 reset_control_deassert(pcie->core_rst); in tegra_pcie_config_controller()
1469 reset_control_assert(pcie->core_apb_rst); in tegra_pcie_config_controller()
1471 clk_disable_unprepare(pcie->core_clk); in tegra_pcie_config_controller()
1473 regulator_disable(pcie->pex_ctl_supply); in tegra_pcie_config_controller()
1477 if (pcie->enable_ext_refclk) in tegra_pcie_config_controller()
1489 ret = reset_control_assert(pcie->core_rst); in tegra_pcie_unconfig_controller()
1491 dev_err(pcie->dev, "Failed to assert \"core\" reset: %d\n", ret); in tegra_pcie_unconfig_controller()
1495 ret = reset_control_assert(pcie->core_apb_rst); in tegra_pcie_unconfig_controller()
1497 dev_err(pcie->dev, "Failed to assert APB reset: %d\n", ret); in tegra_pcie_unconfig_controller()
1499 clk_disable_unprepare(pcie->core_clk); in tegra_pcie_unconfig_controller()
1501 ret = regulator_disable(pcie->pex_ctl_supply); in tegra_pcie_unconfig_controller()
1503 dev_err(pcie->dev, "Failed to disable regulator: %d\n", ret); in tegra_pcie_unconfig_controller()
1507 if (pcie->enable_ext_refclk) { in tegra_pcie_unconfig_controller()
1510 dev_err(pcie->dev, "Failed to deinit UPHY: %d\n", ret); in tegra_pcie_unconfig_controller()
1515 dev_err(pcie->dev, "Failed to disable controller %d: %d\n", in tegra_pcie_unconfig_controller()
1516 pcie->cid, ret); in tegra_pcie_unconfig_controller()
1521 struct dw_pcie *pci = &pcie->pci; in tegra_pcie_init_controller()
1522 struct dw_pcie_rp *pp = &pci->pp; in tegra_pcie_init_controller()
1529 pp->ops = &tegra_pcie_dw_host_ops; in tegra_pcie_init_controller()
1533 dev_err(pcie->dev, "Failed to add PCIe port: %d\n", ret); in tegra_pcie_init_controller()
1548 if (!tegra_pcie_dw_link_up(&pcie->pci)) in tegra_pcie_try_link_l2()
1555 return readl_poll_timeout_atomic(pcie->appl_base + APPL_DEBUG, val, in tegra_pcie_try_link_l2()
1565 if (!tegra_pcie_dw_link_up(&pcie->pci)) { in tegra_pcie_dw_pme_turnoff()
1566 dev_dbg(pcie->dev, "PCIe link is not up...!\n"); in tegra_pcie_dw_pme_turnoff()
1581 dev_info(pcie->dev, "Link didn't transition to L2 state\n"); in tegra_pcie_dw_pme_turnoff()
1593 * Some cards do not go to detect state even after de-asserting in tegra_pcie_dw_pme_turnoff()
1594 * PERST#. So, de-assert LTSSM to bring link to detect state. in tegra_pcie_dw_pme_turnoff()
1596 data = readl(pcie->appl_base + APPL_CTRL); in tegra_pcie_dw_pme_turnoff()
1598 writel(data, pcie->appl_base + APPL_CTRL); in tegra_pcie_dw_pme_turnoff()
1600 err = readl_poll_timeout_atomic(pcie->appl_base + APPL_DEBUG, in tegra_pcie_dw_pme_turnoff()
1608 dev_info(pcie->dev, "Link didn't go to detect state\n"); in tegra_pcie_dw_pme_turnoff()
1611 * DBI registers may not be accessible after this as PLL-E would be in tegra_pcie_dw_pme_turnoff()
1625 dw_pcie_host_deinit(&pcie->pci.pp); in tegra_pcie_deinit_controller()
1632 struct device *dev = pcie->dev; in tegra_pcie_config_rp()
1657 pcie->link_state = tegra_pcie_dw_link_up(&pcie->pci); in tegra_pcie_config_rp()
1658 if (!pcie->link_state) { in tegra_pcie_config_rp()
1659 ret = -ENOMEDIUM; in tegra_pcie_config_rp()
1663 name = devm_kasprintf(dev, GFP_KERNEL, "%pOFP", dev->of_node); in tegra_pcie_config_rp()
1665 ret = -ENOMEM; in tegra_pcie_config_rp()
1669 pcie->debugfs = debugfs_create_dir(name, NULL); in tegra_pcie_config_rp()
1687 if (pcie->ep_state == EP_STATE_DISABLED) in pex_ep_event_pex_rst_assert()
1695 ret = readl_poll_timeout(pcie->appl_base + APPL_DEBUG, val, in pex_ep_event_pex_rst_assert()
1701 dev_err(pcie->dev, "Failed to go Detect state: %d\n", ret); in pex_ep_event_pex_rst_assert()
1703 reset_control_assert(pcie->core_rst); in pex_ep_event_pex_rst_assert()
1707 reset_control_assert(pcie->core_apb_rst); in pex_ep_event_pex_rst_assert()
1709 clk_disable_unprepare(pcie->core_clk); in pex_ep_event_pex_rst_assert()
1711 pm_runtime_put_sync(pcie->dev); in pex_ep_event_pex_rst_assert()
1713 if (pcie->enable_ext_refclk) { in pex_ep_event_pex_rst_assert()
1716 dev_err(pcie->dev, "Failed to turn off UPHY: %d\n", in pex_ep_event_pex_rst_assert()
1722 dev_err(pcie->dev, "Failed to turn off UPHY: %d\n", ret); in pex_ep_event_pex_rst_assert()
1724 pcie->ep_state = EP_STATE_DISABLED; in pex_ep_event_pex_rst_assert()
1725 dev_dbg(pcie->dev, "Uninitialization of endpoint is completed\n"); in pex_ep_event_pex_rst_assert()
1730 struct dw_pcie *pci = &pcie->pci; in pex_ep_event_pex_rst_deassert()
1731 struct dw_pcie_ep *ep = &pci->ep; in pex_ep_event_pex_rst_deassert()
1732 struct device *dev = pcie->dev; in pex_ep_event_pex_rst_deassert()
1737 if (pcie->ep_state == EP_STATE_ENABLED) in pex_ep_event_pex_rst_deassert()
1749 dev_err(pcie->dev, "Failed to enable controller %u: %d\n", in pex_ep_event_pex_rst_deassert()
1750 pcie->cid, ret); in pex_ep_event_pex_rst_deassert()
1754 if (pcie->enable_ext_refclk) { in pex_ep_event_pex_rst_deassert()
1763 ret = clk_prepare_enable(pcie->core_clk); in pex_ep_event_pex_rst_deassert()
1769 ret = reset_control_deassert(pcie->core_apb_rst); in pex_ep_event_pex_rst_deassert()
1821 appl_writel(pcie, pcie->dbi_res->start & APPL_CFG_BASE_ADDR_MASK, in pex_ep_event_pex_rst_deassert()
1824 appl_writel(pcie, pcie->atu_dma_res->start & in pex_ep_event_pex_rst_deassert()
1839 reset_control_deassert(pcie->core_rst); in pex_ep_event_pex_rst_deassert()
1841 if (pcie->update_fc_fixup) { in pex_ep_event_pex_rst_deassert()
1851 /* Disable ASPM-L1SS advertisement if there is no CLKREQ routing */ in pex_ep_event_pex_rst_deassert()
1852 if (!pcie->supports_clkreq) { in pex_ep_event_pex_rst_deassert()
1857 if (!pcie->of_data->has_l1ss_exit_fix) { in pex_ep_event_pex_rst_deassert()
1863 pcie->pcie_cap_base = dw_pcie_find_capability(&pcie->pci, in pex_ep_event_pex_rst_deassert()
1866 val_16 = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_DEVCTL); in pex_ep_event_pex_rst_deassert()
1869 dw_pcie_writew_dbi(pci, pcie->pcie_cap_base + PCI_EXP_DEVCTL, val_16); in pex_ep_event_pex_rst_deassert()
1872 if (pcie->enable_srns) { in pex_ep_event_pex_rst_deassert()
1873 val_16 = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + in pex_ep_event_pex_rst_deassert()
1876 dw_pcie_writew_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA, in pex_ep_event_pex_rst_deassert()
1880 clk_set_rate(pcie->core_clk, GEN4_CORE_CLK_FREQ); in pex_ep_event_pex_rst_deassert()
1882 val = (ep->msi_mem_phys & MSIX_ADDR_MATCH_LOW_OFF_MASK); in pex_ep_event_pex_rst_deassert()
1885 val = (upper_32_bits(ep->msi_mem_phys) & MSIX_ADDR_MATCH_HIGH_OFF_MASK); in pex_ep_event_pex_rst_deassert()
1897 if (pcie->of_data->has_ltr_req_fix) { in pex_ep_event_pex_rst_deassert()
1908 pcie->ep_state = EP_STATE_ENABLED; in pex_ep_event_pex_rst_deassert()
1914 reset_control_assert(pcie->core_rst); in pex_ep_event_pex_rst_deassert()
1917 reset_control_assert(pcie->core_apb_rst); in pex_ep_event_pex_rst_deassert()
1919 clk_disable_unprepare(pcie->core_clk); in pex_ep_event_pex_rst_deassert()
1932 if (gpiod_get_value(pcie->pex_rst_gpiod)) in tegra_pcie_ep_pex_rst_irq()
1944 return -EINVAL; in tegra_pcie_ep_raise_legacy_irq()
1955 return -EINVAL; in tegra_pcie_ep_raise_msi_irq()
1964 struct dw_pcie_ep *ep = &pcie->pci.ep; in tegra_pcie_ep_raise_msix_irq()
1966 writel(irq, ep->msi_mem); in tegra_pcie_ep_raise_msix_irq()
1989 dev_err(pci->dev, "Unknown IRQ type\n"); in tegra_pcie_ep_raise_irq()
1990 return -EPERM; in tegra_pcie_ep_raise_irq()
2020 struct dw_pcie *pci = &pcie->pci; in tegra_pcie_config_ep()
2021 struct device *dev = pcie->dev; in tegra_pcie_config_ep()
2026 ep = &pci->ep; in tegra_pcie_config_ep()
2027 ep->ops = &pcie_ep_ops; in tegra_pcie_config_ep()
2029 ep->page_size = SZ_64K; in tegra_pcie_config_ep()
2031 ret = gpiod_set_debounce(pcie->pex_rst_gpiod, PERST_DEBOUNCE_TIME); in tegra_pcie_config_ep()
2038 ret = gpiod_to_irq(pcie->pex_rst_gpiod); in tegra_pcie_config_ep()
2043 pcie->pex_rst_irq = (unsigned int)ret; in tegra_pcie_config_ep()
2046 pcie->cid); in tegra_pcie_config_ep()
2049 return -ENOMEM; in tegra_pcie_config_ep()
2052 irq_set_status_flags(pcie->pex_rst_irq, IRQ_NOAUTOEN); in tegra_pcie_config_ep()
2054 pcie->ep_state = EP_STATE_DISABLED; in tegra_pcie_config_ep()
2056 ret = devm_request_threaded_irq(dev, pcie->pex_rst_irq, NULL, in tegra_pcie_config_ep()
2082 struct device *dev = &pdev->dev; in tegra_pcie_dw_probe()
2096 return -ENOMEM; in tegra_pcie_dw_probe()
2098 pci = &pcie->pci; in tegra_pcie_dw_probe()
2099 pci->dev = &pdev->dev; in tegra_pcie_dw_probe()
2100 pci->ops = &tegra_dw_pcie_ops; in tegra_pcie_dw_probe()
2101 pcie->dev = &pdev->dev; in tegra_pcie_dw_probe()
2102 pcie->of_data = (struct tegra_pcie_dw_of_data *)data; in tegra_pcie_dw_probe()
2103 pci->n_fts[0] = pcie->of_data->n_fts[0]; in tegra_pcie_dw_probe()
2104 pci->n_fts[1] = pcie->of_data->n_fts[1]; in tegra_pcie_dw_probe()
2105 pp = &pci->pp; in tegra_pcie_dw_probe()
2106 pp->num_vectors = MAX_MSI_IRQS; in tegra_pcie_dw_probe()
2112 if (ret == -EPROBE_DEFER) in tegra_pcie_dw_probe()
2125 if (ret == -EPROBE_DEFER) in tegra_pcie_dw_probe()
2134 if (pcie->pex_refclk_sel_gpiod) in tegra_pcie_dw_probe()
2135 gpiod_set_value(pcie->pex_refclk_sel_gpiod, 1); in tegra_pcie_dw_probe()
2137 pcie->pex_ctl_supply = devm_regulator_get(dev, "vddio-pex-ctl"); in tegra_pcie_dw_probe()
2138 if (IS_ERR(pcie->pex_ctl_supply)) { in tegra_pcie_dw_probe()
2139 ret = PTR_ERR(pcie->pex_ctl_supply); in tegra_pcie_dw_probe()
2140 if (ret != -EPROBE_DEFER) in tegra_pcie_dw_probe()
2142 PTR_ERR(pcie->pex_ctl_supply)); in tegra_pcie_dw_probe()
2146 pcie->core_clk = devm_clk_get(dev, "core"); in tegra_pcie_dw_probe()
2147 if (IS_ERR(pcie->core_clk)) { in tegra_pcie_dw_probe()
2149 PTR_ERR(pcie->core_clk)); in tegra_pcie_dw_probe()
2150 return PTR_ERR(pcie->core_clk); in tegra_pcie_dw_probe()
2153 pcie->appl_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, in tegra_pcie_dw_probe()
2155 if (!pcie->appl_res) { in tegra_pcie_dw_probe()
2157 return -ENODEV; in tegra_pcie_dw_probe()
2160 pcie->appl_base = devm_ioremap_resource(dev, pcie->appl_res); in tegra_pcie_dw_probe()
2161 if (IS_ERR(pcie->appl_base)) in tegra_pcie_dw_probe()
2162 return PTR_ERR(pcie->appl_base); in tegra_pcie_dw_probe()
2164 pcie->core_apb_rst = devm_reset_control_get(dev, "apb"); in tegra_pcie_dw_probe()
2165 if (IS_ERR(pcie->core_apb_rst)) { in tegra_pcie_dw_probe()
2167 PTR_ERR(pcie->core_apb_rst)); in tegra_pcie_dw_probe()
2168 return PTR_ERR(pcie->core_apb_rst); in tegra_pcie_dw_probe()
2171 phys = devm_kcalloc(dev, pcie->phy_count, sizeof(*phys), GFP_KERNEL); in tegra_pcie_dw_probe()
2173 return -ENOMEM; in tegra_pcie_dw_probe()
2175 for (i = 0; i < pcie->phy_count; i++) { in tegra_pcie_dw_probe()
2176 name = kasprintf(GFP_KERNEL, "p2u-%u", i); in tegra_pcie_dw_probe()
2179 return -ENOMEM; in tegra_pcie_dw_probe()
2185 if (ret != -EPROBE_DEFER) in tegra_pcie_dw_probe()
2191 pcie->phys = phys; in tegra_pcie_dw_probe()
2197 return -ENODEV; in tegra_pcie_dw_probe()
2199 pcie->atu_dma_res = atu_dma_res; in tegra_pcie_dw_probe()
2201 pci->atu_size = resource_size(atu_dma_res); in tegra_pcie_dw_probe()
2202 pci->atu_base = devm_ioremap_resource(dev, atu_dma_res); in tegra_pcie_dw_probe()
2203 if (IS_ERR(pci->atu_base)) in tegra_pcie_dw_probe()
2204 return PTR_ERR(pci->atu_base); in tegra_pcie_dw_probe()
2206 pcie->core_rst = devm_reset_control_get(dev, "core"); in tegra_pcie_dw_probe()
2207 if (IS_ERR(pcie->core_rst)) { in tegra_pcie_dw_probe()
2209 PTR_ERR(pcie->core_rst)); in tegra_pcie_dw_probe()
2210 return PTR_ERR(pcie->core_rst); in tegra_pcie_dw_probe()
2213 pp->irq = platform_get_irq_byname(pdev, "intr"); in tegra_pcie_dw_probe()
2214 if (pp->irq < 0) in tegra_pcie_dw_probe()
2215 return pp->irq; in tegra_pcie_dw_probe()
2217 pcie->bpmp = tegra_bpmp_get(dev); in tegra_pcie_dw_probe()
2218 if (IS_ERR(pcie->bpmp)) in tegra_pcie_dw_probe()
2219 return PTR_ERR(pcie->bpmp); in tegra_pcie_dw_probe()
2223 switch (pcie->of_data->mode) { in tegra_pcie_dw_probe()
2225 ret = devm_request_irq(dev, pp->irq, tegra_pcie_rp_irq_handler, in tegra_pcie_dw_probe()
2226 IRQF_SHARED, "tegra-pcie-intr", pcie); in tegra_pcie_dw_probe()
2228 dev_err(dev, "Failed to request IRQ %d: %d\n", pp->irq, in tegra_pcie_dw_probe()
2234 if (ret && ret != -ENOMEDIUM) in tegra_pcie_dw_probe()
2241 ret = devm_request_threaded_irq(dev, pp->irq, in tegra_pcie_dw_probe()
2245 "tegra-pcie-ep-intr", pcie); in tegra_pcie_dw_probe()
2247 dev_err(dev, "Failed to request IRQ %d: %d\n", pp->irq, in tegra_pcie_dw_probe()
2259 pcie->of_data->mode); in tegra_pcie_dw_probe()
2263 tegra_bpmp_put(pcie->bpmp); in tegra_pcie_dw_probe()
2271 if (pcie->of_data->mode == DW_PCIE_RC_TYPE) { in tegra_pcie_dw_remove()
2272 if (!pcie->link_state) in tegra_pcie_dw_remove()
2275 debugfs_remove_recursive(pcie->debugfs); in tegra_pcie_dw_remove()
2277 pm_runtime_put_sync(pcie->dev); in tegra_pcie_dw_remove()
2279 disable_irq(pcie->pex_rst_irq); in tegra_pcie_dw_remove()
2283 pm_runtime_disable(pcie->dev); in tegra_pcie_dw_remove()
2284 tegra_bpmp_put(pcie->bpmp); in tegra_pcie_dw_remove()
2285 if (pcie->pex_refclk_sel_gpiod) in tegra_pcie_dw_remove()
2286 gpiod_set_value(pcie->pex_refclk_sel_gpiod, 0); in tegra_pcie_dw_remove()
2296 if (pcie->of_data->mode == DW_PCIE_EP_TYPE) { in tegra_pcie_dw_suspend_late()
2298 return -EPERM; in tegra_pcie_dw_suspend_late()
2301 if (!pcie->link_state) in tegra_pcie_dw_suspend_late()
2305 if (!pcie->of_data->has_sbr_reset_fix) { in tegra_pcie_dw_suspend_late()
2320 if (!pcie->link_state) in tegra_pcie_dw_suspend_noirq()
2335 if (!pcie->link_state) in tegra_pcie_dw_resume_noirq()
2342 ret = tegra_pcie_dw_host_init(&pcie->pci.pp); in tegra_pcie_dw_resume_noirq()
2348 dw_pcie_setup_rc(&pcie->pci.pp); in tegra_pcie_dw_resume_noirq()
2350 ret = tegra_pcie_dw_start_link(&pcie->pci); in tegra_pcie_dw_resume_noirq()
2366 if (pcie->of_data->mode == DW_PCIE_EP_TYPE) { in tegra_pcie_dw_resume_early()
2368 return -ENOTSUPP; in tegra_pcie_dw_resume_early()
2371 if (!pcie->link_state) in tegra_pcie_dw_resume_early()
2375 if (!pcie->of_data->has_sbr_reset_fix) { in tegra_pcie_dw_resume_early()
2392 if (pcie->of_data->mode == DW_PCIE_RC_TYPE) { in tegra_pcie_dw_shutdown()
2393 if (!pcie->link_state) in tegra_pcie_dw_shutdown()
2396 debugfs_remove_recursive(pcie->debugfs); in tegra_pcie_dw_shutdown()
2399 disable_irq(pcie->pci.pp.irq); in tegra_pcie_dw_shutdown()
2401 disable_irq(pcie->pci.pp.msi_irq[0]); in tegra_pcie_dw_shutdown()
2405 pm_runtime_put_sync(pcie->dev); in tegra_pcie_dw_shutdown()
2407 disable_irq(pcie->pex_rst_irq); in tegra_pcie_dw_shutdown()
2416 /* Gen4 - 5, 6, 8 and 9 presets enabled */
2425 /* Gen4 - 5, 6, 8 and 9 presets enabled */
2437 /* Gen4 - 6, 8 and 9 presets enabled */
2448 /* Gen4 - 6, 8 and 9 presets enabled */
2455 .compatible = "nvidia,tegra194-pcie",
2459 .compatible = "nvidia,tegra194-pcie-ep",
2463 .compatible = "nvidia,tegra234-pcie",
2467 .compatible = "nvidia,tegra234-pcie-ep",
2485 .name = "tegra194-pcie",