100 /* PARF registers */
221 	void __iomem *parf;			/* DT parf */  member
333 	writel(1, pcie->parf + PCIE20_PARF_PHY_CTRL);  in qcom_pcie_deinit_2_1_0()
423 	val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);  in qcom_pcie_post_init_2_1_0()
425 	writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);  in qcom_pcie_post_init_2_1_0()
436 		       pcie->parf + PCIE20_PARF_PCS_DEEMPH);  in qcom_pcie_post_init_2_1_0()
439 		       pcie->parf + PCIE20_PARF_PCS_SWING);  in qcom_pcie_post_init_2_1_0()
440 		writel(PHY_RX0_EQ(4), pcie->parf + PCIE20_PARF_CONFIG_BITS);  in qcom_pcie_post_init_2_1_0()
445 		val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);  in qcom_pcie_post_init_2_1_0()
448 		writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);  in qcom_pcie_post_init_2_1_0()
452 	val = readl(pcie->parf + PCIE20_PARF_PHY_REFCLK);  in qcom_pcie_post_init_2_1_0()
457 	writel(val, pcie->parf + PCIE20_PARF_PHY_REFCLK);  in qcom_pcie_post_init_2_1_0()
574 	writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);  in qcom_pcie_post_init_1_0_0()
577 		u32 val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT);  in qcom_pcie_post_init_1_0_0()
580 		writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT);  in qcom_pcie_post_init_1_0_0()
591 	val = readl(pcie->parf + PCIE20_PARF_LTSSM);  in qcom_pcie_2_3_2_ltssm_enable()
593 	writel(val, pcie->parf + PCIE20_PARF_LTSSM);  in qcom_pcie_2_3_2_ltssm_enable()
698 	val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);  in qcom_pcie_post_init_2_3_2()
700 	writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);  in qcom_pcie_post_init_2_3_2()
703 	writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);  in qcom_pcie_post_init_2_3_2()
706 	val = readl(pcie->parf + PCIE20_PARF_SYS_CTRL);  in qcom_pcie_post_init_2_3_2()
708 	writel(val, pcie->parf + PCIE20_PARF_SYS_CTRL);  in qcom_pcie_post_init_2_3_2()
710 	val = readl(pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);  in qcom_pcie_post_init_2_3_2()
712 	writel(val, pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);  in qcom_pcie_post_init_2_3_2()
714 	val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2);  in qcom_pcie_post_init_2_3_2()
716 	writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2);  in qcom_pcie_post_init_2_3_2()
768 		res->parf_reset = devm_reset_control_get_exclusive(dev, "parf");  in qcom_pcie_get_resources_2_4_0()
977 	val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);  in qcom_pcie_post_init_2_4_0()
979 	writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);  in qcom_pcie_post_init_2_4_0()
982 	writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);  in qcom_pcie_post_init_2_4_0()
985 	val = readl(pcie->parf + PCIE20_PARF_SYS_CTRL);  in qcom_pcie_post_init_2_4_0()
987 	writel(val, pcie->parf + PCIE20_PARF_SYS_CTRL);  in qcom_pcie_post_init_2_4_0()
989 	val = readl(pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);  in qcom_pcie_post_init_2_4_0()
991 	writel(val, pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);  in qcom_pcie_post_init_2_4_0()
993 	val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2);  in qcom_pcie_post_init_2_4_0()
995 	writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2);  in qcom_pcie_post_init_2_4_0()
1140 		pcie->parf + PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE);  in qcom_pcie_post_init_2_3_3()
1142 	val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);  in qcom_pcie_post_init_2_3_3()
1144 	writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);  in qcom_pcie_post_init_2_3_3()
1146 	writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);  in qcom_pcie_post_init_2_3_3()
1151 		pcie->parf + PCIE20_PARF_SYS_CTRL);  in qcom_pcie_post_init_2_3_3()
1152 	writel(0, pcie->parf + PCIE20_PARF_Q2A_FLUSH);  in qcom_pcie_post_init_2_3_3()
1255 	writel(DEVICE_TYPE_RC, pcie->parf + PCIE20_PARF_DEVICE_TYPE);  in qcom_pcie_init_2_7_0()
1258 	val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);  in qcom_pcie_init_2_7_0()
1260 	writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);  in qcom_pcie_init_2_7_0()
1263 	writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);  in qcom_pcie_init_2_7_0()
1266 	val = readl(pcie->parf + PCIE20_PARF_SYS_CTRL);  in qcom_pcie_init_2_7_0()
1268 	writel(val, pcie->parf + PCIE20_PARF_SYS_CTRL);  in qcom_pcie_init_2_7_0()
1270 	val = readl(pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);  in qcom_pcie_init_2_7_0()
1272 	writel(val, pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);  in qcom_pcie_init_2_7_0()
1275 	val = readl(pcie->parf + PCIE20_PARF_PM_CTRL);  in qcom_pcie_init_2_7_0()
1277 	writel(val, pcie->parf + PCIE20_PARF_PM_CTRL);  in qcom_pcie_init_2_7_0()
1280 		val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT);  in qcom_pcie_init_2_7_0()
1282 		writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT);  in qcom_pcie_init_2_7_0()
1371 		pcie->parf + PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE);  in qcom_pcie_post_init_2_9_0()
1373 	val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);  in qcom_pcie_post_init_2_9_0()
1375 	writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);  in qcom_pcie_post_init_2_9_0()
1377 	writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);  in qcom_pcie_post_init_2_9_0()
1379 	writel(DEVICE_TYPE_RC, pcie->parf + PCIE20_PARF_DEVICE_TYPE);  in qcom_pcie_post_init_2_9_0()
1381 		pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);  in qcom_pcie_post_init_2_9_0()
1389 		pcie->parf + PCIE20_PARF_SYS_CTRL);  in qcom_pcie_post_init_2_9_0()
1391 	writel(0, pcie->parf + PCIE20_PARF_Q2A_FLUSH);  in qcom_pcie_post_init_2_9_0()
1404 		writel(0, pcie->parf + PCIE20_PARF_BDF_TO_SID_TABLE_N + (4 * i));  in qcom_pcie_post_init_2_9_0()
1426 	void __iomem *bdf_to_sid_base = pcie->parf + PCIE20_PARF_BDF_TO_SID_TABLE_N;  in qcom_pcie_config_sid_sm8250()
1684 	pcie->parf = devm_platform_ioremap_resource_byname(pdev, "parf");  in qcom_pcie_probe()
1685 	if (IS_ERR(pcie->parf)) {  in qcom_pcie_probe()
1686 		ret = PTR_ERR(pcie->parf);  in qcom_pcie_probe()