Lines Matching +full:0 +full:x8c8
41 #define SIFIVE_DEVICESRESETREG 0x28
43 #define PCIEX8MGMT_PERST_N 0x0
44 #define PCIEX8MGMT_APP_LTSSM_ENABLE 0x10
45 #define PCIEX8MGMT_APP_HOLD_PHY_RST 0x18
46 #define PCIEX8MGMT_DEVICE_TYPE 0x708
47 #define PCIEX8MGMT_PHY0_CR_PARA_ADDR 0x860
48 #define PCIEX8MGMT_PHY0_CR_PARA_RD_EN 0x870
49 #define PCIEX8MGMT_PHY0_CR_PARA_RD_DATA 0x878
50 #define PCIEX8MGMT_PHY0_CR_PARA_SEL 0x880
51 #define PCIEX8MGMT_PHY0_CR_PARA_WR_DATA 0x888
52 #define PCIEX8MGMT_PHY0_CR_PARA_WR_EN 0x890
53 #define PCIEX8MGMT_PHY0_CR_PARA_ACK 0x898
54 #define PCIEX8MGMT_PHY1_CR_PARA_ADDR 0x8a0
55 #define PCIEX8MGMT_PHY1_CR_PARA_RD_EN 0x8b0
56 #define PCIEX8MGMT_PHY1_CR_PARA_RD_DATA 0x8b8
57 #define PCIEX8MGMT_PHY1_CR_PARA_SEL 0x8c0
58 #define PCIEX8MGMT_PHY1_CR_PARA_WR_DATA 0x8c8
59 #define PCIEX8MGMT_PHY1_CR_PARA_WR_EN 0x8d0
60 #define PCIEX8MGMT_PHY1_CR_PARA_ACK 0x8d8
62 #define PCIEX8MGMT_PHY_CDR_TRACK_EN BIT(0)
73 #define PCIEX8MGMT_PHY_LANEN_DIG_ASIC_RX_OVRD_IN_3 0x1008
74 #define PCIEX8MGMT_PHY_LANE_OFF 0x100
75 #define PCIEX8MGMT_PHY_LANE0_BASE (PCIEX8MGMT_PHY_LANEN_DIG_ASIC_RX_OVRD_IN_3 + 0x100 * 0)
76 #define PCIEX8MGMT_PHY_LANE1_BASE (PCIEX8MGMT_PHY_LANEN_DIG_ASIC_RX_OVRD_IN_3 + 0x100 * 1)
77 #define PCIEX8MGMT_PHY_LANE2_BASE (PCIEX8MGMT_PHY_LANEN_DIG_ASIC_RX_OVRD_IN_3 + 0x100 * 2)
78 #define PCIEX8MGMT_PHY_LANE3_BASE (PCIEX8MGMT_PHY_LANEN_DIG_ASIC_RX_OVRD_IN_3 + 0x100 * 3)
83 gpiod_set_value_cansleep(afp->reset, 0); in fu740_pcie_assert_reset()
85 writel_relaxed(0x0, afp->mgmt_base + PCIEX8MGMT_PERST_N); in fu740_pcie_assert_reset()
91 writel_relaxed(0x1, afp->mgmt_base + PCIEX8MGMT_PERST_N); in fu740_pcie_deassert_reset()
147 writel_relaxed(0, phy_cr_para_wr_en); in fu740_phyregwrite()
158 writel_relaxed(0x1, afp->mgmt_base + PCIEX8MGMT_PHY0_CR_PARA_SEL); in fu740_pcie_init_phy()
159 writel_relaxed(0x1, afp->mgmt_base + PCIEX8MGMT_PHY1_CR_PARA_SEL); in fu740_pcie_init_phy()
168 fu740_phyregwrite(0, PCIEX8MGMT_PHY_LANE0_BASE, PCIEX8MGMT_PHY_INIT_VAL, afp); in fu740_pcie_init_phy()
169 fu740_phyregwrite(0, PCIEX8MGMT_PHY_LANE1_BASE, PCIEX8MGMT_PHY_INIT_VAL, afp); in fu740_pcie_init_phy()
170 fu740_phyregwrite(0, PCIEX8MGMT_PHY_LANE2_BASE, PCIEX8MGMT_PHY_INIT_VAL, afp); in fu740_pcie_init_phy()
171 fu740_phyregwrite(0, PCIEX8MGMT_PHY_LANE3_BASE, PCIEX8MGMT_PHY_INIT_VAL, afp); in fu740_pcie_init_phy()
203 writel_relaxed(0x1, afp->mgmt_base + PCIEX8MGMT_APP_LTSSM_ENABLE); in fu740_pcie_start_link()
230 ret = 0; in fu740_pcie_start_link()
258 writel_relaxed(0x1, afp->mgmt_base + PCIEX8MGMT_APP_HOLD_PHY_RST); in fu740_pcie_host_init()
272 writel_relaxed(0x0, afp->mgmt_base + PCIEX8MGMT_APP_HOLD_PHY_RST); in fu740_pcie_host_init()
276 writel_relaxed(0x4, afp->mgmt_base + PCIEX8MGMT_DEVICE_TYPE); in fu740_pcie_host_init()
278 return 0; in fu740_pcie_host_init()