Lines Matching +full:d +full:- +full:tlb +full:- +full:sets
1 // SPDX-License-Identifier: GPL-2.0-or-later
3 ** ccio-dma.c:
4 ** DMA management routines for first generation cache-coherent machines.
9 ** (c) Copyright 2000 Hewlett-Packard Company
15 ** the I/O MMU - basically what x86 does.
17 ** Philipp Rumpf has a "Real Mode" driver for PCX-W machines at:
18 ** CVSROOT=:pserver:anonymous@198.186.203.37:/cvsroot/linux-parisc
19 ** cvs -z3 co linux/arch/parisc/kernel/dma-rm.c
21 ** I've rewritten his code to work under TPG's tree. See ccio-rm-dma.c.
24 ** o outbound DMA is slower - U2 won't prefetch data (GSC+ XQL signal).
25 ** o Inbound DMA less efficient - U2 can't use DMA_FAST attribute.
27 ** o Doesn't work under PCX-U/U+ machines since they didn't follow
28 ** the coherency design originally worked out. Only PCX-W does.
42 #include <linux/dma-map-ops.h>
44 #include <linux/iommu-helper.h>
54 #include <asm/parisc-device.h>
59 ** Choose "ccio" since that's what HP-UX calls it.
110 #define CMD_TLB_DIRECT_WRITE 35 /* IO_COMMAND for I/O TLB Writes */
111 #define CMD_TLB_PURGE 33 /* IO_COMMAND to Purge I/O TLB entry */
141 ** -------------
148 ** | HV | TLB | reserved | HV | mode | reserved |
169 ** o TLB field affects transactions which are forwarded from GSC+ to Runway.
172 ** TLB Mode Value Description
173 ** Real 0 No TLB translation. Address is directly mapped and the
175 ** Error 1 Software fills the TLB manually.
176 ** Normal 2 IOA fetches IO TLB misses from IO PDIR (in host memory).
192 ** with both sets of LOW/HIGH registers. If the address is in the range
217 ** Writes to both sets of registers will take effect immediately, bypassing
230 u32 res_hint; /* next available IOVP -
256 struct pci_dev *fake_pci_dev; /* the fake pci_dev for non-pci devs */
273 * allocation policies is also adjusted. We'd like to avoid
274 * I/O TLB thrashing by having resource allocation policy
275 * match the I/O TLB replacement policy.
299 idx = (unsigned int)((unsigned long)res_ptr - (unsigned long)ioc->res_map); \
304 ioc->res_hint = res_idx + (size >> 3); \
310 u##size *res_ptr = (u##size *)&((ioc)->res_map[ioa->res_hint & ~((size >> 3) - 1)]); \
311 u##size *res_end = (u##size *)&(ioc)->res_map[ioa->res_size]; \
313 res_ptr = (u##size *)&(ioc)->res_map[0]; \
319 ** o Most IOVA's are "temporary" - avg search time should be small.
331 * ccio_alloc_range - Allocate pages in the ioc's resource map.
352 DBG_RES("%s() size: %d pages_needed %d\n", in ccio_alloc_range()
364 * LAN traffic will not thrash the TLB IFF the same NIC in ccio_alloc_range()
370 * an unsigned long - not byte at a time. As it is now, in ccio_alloc_range()
396 DBG_RES("%s() res_idx %d res_hint: %d\n", in ccio_alloc_range()
397 __func__, res_idx, ioc->res_hint); in ccio_alloc_range()
402 unsigned long tmp = cr_end - cr_start; in ccio_alloc_range()
404 cr_start = (cr_end < cr_start) ? -(tmp) : (tmp); in ccio_alloc_range()
406 ioc->avg_search[ioc->avg_idx++] = cr_start; in ccio_alloc_range()
407 ioc->avg_idx &= CCIO_SEARCH_SAMPLE - 1; in ccio_alloc_range()
408 ioc->used_pages += pages_needed; in ccio_alloc_range()
417 u##size *res_ptr = (u##size *)&((ioc)->res_map[res_idx]); \
422 * ccio_free_range - Free pages from the ioc's resource map.
440 DBG_RES("%s(): res_idx: %d pages_mapped %d\n", in ccio_free_range()
444 ioc->used_pages -= pages_mapped; in ccio_free_range()
497 ** FIXME: the default hints need to be per GSC device - not global.
499 ** HP-UX dorks: linux device driver programming model is totally different
500 ** than HP-UX's. HP-UX always sets HINT_PREFETCH since it's drivers
501 ** do special things to work on non-coherent platforms...linux has to
527 * ccio_io_pdir_entry - Initialize an I/O Pdir.
539 * +------+----------------+-----------------------------------------------+
543 * +------+----------------+-----------------------------------------------+
545 * +-----------------------+-----------------------------------------------+
549 * +-----------------------+-----------------------------------------------+
566 ** WORD 1 - low order word in ccio_io_pdir_entry()
575 ** WORD 0 - high order word in ccio_io_pdir_entry()
603 ** PCX-U/U+ do. (eg C200/C240) in ccio_io_pdir_entry()
604 ** PCX-T'? Don't know. (eg C110 or similar K-class) in ccio_io_pdir_entry()
606 ** See PDC_MODEL/option 0/SW_CAP word for "Non-coherent IO-PDIR bit". in ccio_io_pdir_entry()
608 ** "Since PCX-U employs an offset hash that is incompatible with in ccio_io_pdir_entry()
617 * ccio_clear_io_tlb - Remove stale entries from the I/O TLB.
622 * Purge invalid I/O PDIR entries from the I/O TLB.
629 u32 chain_size = 1 << ioc->chainid_shift; in ccio_clear_io_tlb()
635 WRITE_U32(CMD_TLB_PURGE | iovp, &ioc->ioc_regs->io_command); in ccio_clear_io_tlb()
637 byte_cnt -= chain_size; in ccio_clear_io_tlb()
642 * ccio_mark_invalid - Mark the I/O Pdir entries invalid.
648 * TLB entries.
651 * away the entire I/O TLB instead of individual entries.
653 * FIXME: Uturn has 256 TLB entries. We don't need to purge every
654 * PDIR entry - just once for each possible TLB entry.
671 char *pdir_ptr = (char *) &(ioc->pdir_base[idx]); in ccio_mark_invalid()
673 BUG_ON(idx >= (ioc->pdir_size / sizeof(u64))); in ccio_mark_invalid()
677 ** PCX-U/U+ do. (eg C200/C240) in ccio_mark_invalid()
678 ** See PDC_MODEL/option 0/SW_CAP for "Non-coherent IO-PDIR bit". in ccio_mark_invalid()
683 byte_cnt -= IOVP_SIZE; in ccio_mark_invalid()
697 * ccio_dma_supported - Verify the IOMMU supports the DMA address range.
710 /* only support 32-bit or better devices (ie PCI/GSC) */ in ccio_dma_supported()
715 * ccio_map_single - Map an address range into the IOMMU.
747 spin_lock_irqsave(&ioc->res_lock, flags); in ccio_map_single()
750 ioc->msingle_calls++; in ccio_map_single()
751 ioc->msingle_pages += size >> IOVP_SHIFT; in ccio_map_single()
757 pdir_start = &(ioc->pdir_base[idx]); in ccio_map_single()
759 DBG_RUN("%s() 0x%p -> 0x%lx size: %0x%x\n", in ccio_map_single()
775 size -= IOVP_SIZE; in ccio_map_single()
778 spin_unlock_irqrestore(&ioc->res_lock, flags); in ccio_map_single()
796 * ccio_unmap_page - Unmap an address range from the IOMMU.
824 spin_lock_irqsave(&ioc->res_lock, flags); in ccio_unmap_page()
827 ioc->usingle_calls++; in ccio_unmap_page()
828 ioc->usingle_pages += size >> IOVP_SHIFT; in ccio_unmap_page()
833 spin_unlock_irqrestore(&ioc->res_lock, flags); in ccio_unmap_page()
837 * ccio_alloc - Allocate a consistent DMA mapping.
850 /* GRANT Need to establish hierarchy for non-PCI devs as well in ccio_alloc()
870 * ccio_free - Free a consistent DMA mapping.
896 #include "iommu-helpers.h"
899 * ccio_map_sg - Map the scatter/gather list into the IOMMU.
921 return -EINVAL; in ccio_map_sg()
923 DBG_RUN_SG("%s() START %d entries\n", __func__, nents); in ccio_map_sg()
928 sg_virt(sglist), sglist->length, in ccio_map_sg()
930 sg_dma_len(sglist) = sglist->length; in ccio_map_sg()
937 spin_lock_irqsave(&ioc->res_lock, flags); in ccio_map_sg()
940 ioc->msg_calls++; in ccio_map_sg()
963 spin_unlock_irqrestore(&ioc->res_lock, flags); in ccio_map_sg()
967 DBG_RUN_SG("%s() DONE %d mappings\n", __func__, filled); in ccio_map_sg()
978 * ccio_unmap_sg - Unmap the scatter/gather list from the IOMMU.
999 DBG_RUN_SG("%s() START %d entries, %p,%x\n", in ccio_unmap_sg()
1000 __func__, nents, sg_virt(sglist), sglist->length); in ccio_unmap_sg()
1003 ioc->usg_calls++; in ccio_unmap_sg()
1009 ioc->usg_pages += sg_dma_len(sglist) >> PAGE_SHIFT; in ccio_unmap_sg()
1014 nents--; in ccio_unmap_sg()
1017 DBG_RUN_SG("%s() DONE (nents %d)\n", __func__, nents); in ccio_unmap_sg()
1039 unsigned int total_pages = ioc->res_size << 3; in ccio_proc_info()
1045 seq_printf(m, "%s\n", ioc->name); in ccio_proc_info()
1048 (ioc->cujo20_bug ? "yes" : "no")); in ccio_proc_info()
1050 seq_printf(m, "IO PDIR size : %d bytes (%d entries)\n", in ccio_proc_info()
1054 seq_printf(m, "IO PDIR entries : %ld free %ld used (%d%%)\n", in ccio_proc_info()
1055 total_pages - ioc->used_pages, ioc->used_pages, in ccio_proc_info()
1056 (int)(ioc->used_pages * 100 / total_pages)); in ccio_proc_info()
1059 seq_printf(m, "Resource bitmap : %d bytes (%d pages)\n", in ccio_proc_info()
1060 ioc->res_size, total_pages); in ccio_proc_info()
1063 min = max = ioc->avg_search[0]; in ccio_proc_info()
1065 avg += ioc->avg_search[j]; in ccio_proc_info()
1066 if(ioc->avg_search[j] > max) in ccio_proc_info()
1067 max = ioc->avg_search[j]; in ccio_proc_info()
1068 if(ioc->avg_search[j] < min) in ccio_proc_info()
1069 min = ioc->avg_search[j]; in ccio_proc_info()
1075 seq_printf(m, "pci_map_single(): %8ld calls %8ld pages (avg %d/1000)\n", in ccio_proc_info()
1076 ioc->msingle_calls, ioc->msingle_pages, in ccio_proc_info()
1077 (int)((ioc->msingle_pages * 1000)/ioc->msingle_calls)); in ccio_proc_info()
1079 /* KLUGE - unmap_sg calls unmap_page for each mapped page */ in ccio_proc_info()
1080 min = ioc->usingle_calls - ioc->usg_calls; in ccio_proc_info()
1081 max = ioc->usingle_pages - ioc->usg_pages; in ccio_proc_info()
1082 seq_printf(m, "pci_unmap_single: %8ld calls %8ld pages (avg %d/1000)\n", in ccio_proc_info()
1085 seq_printf(m, "pci_map_sg() : %8ld calls %8ld pages (avg %d/1000)\n", in ccio_proc_info()
1086 ioc->msg_calls, ioc->msg_pages, in ccio_proc_info()
1087 (int)((ioc->msg_pages * 1000)/ioc->msg_calls)); in ccio_proc_info()
1089 seq_printf(m, "pci_unmap_sg() : %8ld calls %8ld pages (avg %d/1000)\n\n\n", in ccio_proc_info()
1090 ioc->usg_calls, ioc->usg_pages, in ccio_proc_info()
1091 (int)((ioc->usg_pages * 1000)/ioc->usg_calls)); in ccio_proc_info()
1094 ioc = ioc->next; in ccio_proc_info()
1105 seq_hex_dump(m, " ", DUMP_PREFIX_NONE, 32, 4, ioc->res_map, in ccio_proc_bitmap_info()
1106 ioc->res_size, false); in ccio_proc_bitmap_info()
1108 ioc = ioc->next; in ccio_proc_bitmap_info()
1109 break; /* XXX - remove me */ in ccio_proc_bitmap_info()
1117 * ccio_find_ioc - Find the ioc in the ioc_list
1130 if (ioc->hw_path == hw_path) in ccio_find_ioc()
1133 ioc = ioc->next; in ccio_find_ioc()
1140 * ccio_get_iommu - Find the iommu which controls this device
1152 return ccio_find_ioc(dev->hw_path); in ccio_get_iommu()
1168 ioc->cujo20_bug = 1; in ccio_cujo20_fixup()
1169 res_ptr = ioc->res_map; in ccio_cujo20_fixup()
1172 while (idx < ioc->res_size) { in ccio_cujo20_fixup()
1179 /* GRANT - is this needed for U2 or not? */
1182 ** Get the size of the I/O TLB for this I/O MMU.
1184 ** If spa_shift is non-zero (ie probably U2),
1185 ** then calculate the I/O TLB size using spa_shift.
1187 ** Otherwise we are supposed to get the IODC entry point ENTRY TLB
1189 ** I think only Java (K/D/R-class too?) systems don't do this.
1194 if (dev->spa_shift == 0) {
1195 panic("%s() : Can't determine I/O TLB size.\n", __func__);
1197 return (1 << dev->spa_shift);
1201 /* Uturn supports 256 TLB entries */
1222 * ccio_ioc_init - Initialize the I/O Controller
1242 ** can be outstanding based on PCI Class/sub-class. Both in ccio_ioc_init()
1244 ** Hot-Plug/Removal of PCI cards. (aka PCI OLARD). in ccio_ioc_init()
1249 /* limit IOVA space size to 1MB-1GB */ in ccio_ioc_init()
1251 if (iova_space_size < (1 << (20 - PAGE_SHIFT))) { in ccio_ioc_init()
1252 iova_space_size = 1 << (20 - PAGE_SHIFT); in ccio_ioc_init()
1254 } else if (iova_space_size > (1 << (30 - PAGE_SHIFT))) { in ccio_ioc_init()
1255 iova_space_size = 1 << (30 - PAGE_SHIFT); in ccio_ioc_init()
1268 ** since the pages must also be physically contiguous - typically in ccio_ioc_init()
1277 ioc->pdir_size = (iova_space_size / IOVP_SIZE) * sizeof(u64); in ccio_ioc_init()
1279 BUG_ON(ioc->pdir_size > 8 * 1024 * 1024); /* max pdir size <= 8MB */ in ccio_ioc_init()
1282 BUG_ON((1 << get_order(ioc->pdir_size)) != (ioc->pdir_size >> PAGE_SHIFT)); in ccio_ioc_init()
1284 DBG_INIT("%s() hpa 0x%p mem %luMB IOV %dMB (%d bits)\n", in ccio_ioc_init()
1285 __func__, ioc->ioc_regs, in ccio_ioc_init()
1286 (unsigned long) totalram_pages() >> (20 - PAGE_SHIFT), in ccio_ioc_init()
1290 ioc->pdir_base = (u64 *)__get_free_pages(GFP_KERNEL, in ccio_ioc_init()
1291 get_order(ioc->pdir_size)); in ccio_ioc_init()
1292 if(NULL == ioc->pdir_base) { in ccio_ioc_init()
1295 memset(ioc->pdir_base, 0, ioc->pdir_size); in ccio_ioc_init()
1297 BUG_ON((((unsigned long)ioc->pdir_base) & PAGE_MASK) != (unsigned long)ioc->pdir_base); in ccio_ioc_init()
1298 DBG_INIT(" base %p\n", ioc->pdir_base); in ccio_ioc_init()
1301 ioc->res_size = (ioc->pdir_size / sizeof(u64)) >> 3; in ccio_ioc_init()
1302 DBG_INIT("%s() res_size 0x%x\n", __func__, ioc->res_size); in ccio_ioc_init()
1304 ioc->res_map = (u8 *)__get_free_pages(GFP_KERNEL, in ccio_ioc_init()
1305 get_order(ioc->res_size)); in ccio_ioc_init()
1306 if(NULL == ioc->res_map) { in ccio_ioc_init()
1309 memset(ioc->res_map, 0, ioc->res_size); in ccio_ioc_init()
1312 ioc->res_hint = 16; in ccio_ioc_init()
1315 spin_lock_init(&ioc->res_lock); in ccio_ioc_init()
1319 ** which TLB entry an IOVP will use. in ccio_ioc_init()
1321 ioc->chainid_shift = get_order(iova_space_size) + PAGE_SHIFT - CCIO_CHAINID_SHIFT; in ccio_ioc_init()
1322 DBG_INIT(" chainid_shift 0x%x\n", ioc->chainid_shift); in ccio_ioc_init()
1327 WRITE_U32(CCIO_CHAINID_MASK << ioc->chainid_shift, in ccio_ioc_init()
1328 &ioc->ioc_regs->io_chain_id_mask); in ccio_ioc_init()
1330 WRITE_U32(virt_to_phys(ioc->pdir_base), in ccio_ioc_init()
1331 &ioc->ioc_regs->io_pdir_base); in ccio_ioc_init()
1336 WRITE_U32(IOA_NORMAL_MODE, &ioc->ioc_regs->io_control); in ccio_ioc_init()
1339 ** Initialize all I/O TLB entries to 0 (Valid bit off). in ccio_ioc_init()
1341 WRITE_U32(0, &ioc->ioc_regs->io_tlb_entry_m); in ccio_ioc_init()
1342 WRITE_U32(0, &ioc->ioc_regs->io_tlb_entry_l); in ccio_ioc_init()
1344 for(i = 1 << CCIO_CHAINID_SHIFT; i ; i--) { in ccio_ioc_init()
1345 WRITE_U32((CMD_TLB_DIRECT_WRITE | (i << ioc->chainid_shift)), in ccio_ioc_init()
1346 &ioc->ioc_regs->io_command); in ccio_ioc_init()
1355 res->parent = NULL; in ccio_init_resource()
1356 res->flags = IORESOURCE_MEM; in ccio_init_resource()
1360 * The upper 16-bits of range registers are hardcoded to 0xffff. in ccio_init_resource()
1362 res->start = (unsigned long)((signed) READ_U32(ioaddr) << 16); in ccio_init_resource()
1363 res->end = (unsigned long)((signed) (READ_U32(ioaddr + 4) << 16) - 1); in ccio_init_resource()
1364 res->name = name; in ccio_init_resource()
1368 if (res->end + 1 == res->start) in ccio_init_resource()
1371 /* On some platforms (e.g. K-Class), we have already registered in ccio_init_resource()
1379 __func__, (unsigned long)res->start, (unsigned long)res->end); in ccio_init_resource()
1385 struct resource *res = ioc->mmio_region; in ccio_init_resources()
1388 return -ENOMEM; in ccio_init_resources()
1389 snprintf(name, 14, "GSC Bus [%d/]", ioc->hw_path); in ccio_init_resources()
1391 ccio_init_resource(res, name, &ioc->ioc_regs->io_io_low); in ccio_init_resources()
1392 ccio_init_resource(res + 1, name, &ioc->ioc_regs->io_io_low_hv); in ccio_init_resources()
1400 return -EBUSY; in new_ioc_area()
1402 res->start = (max - size + 1) &~ (align - 1); in new_ioc_area()
1403 res->end = res->start + size; in new_ioc_area()
1412 return new_ioc_area(res, size, min, max - size, align); in new_ioc_area()
1420 if (!res->parent) in expand_ioc_area()
1423 start = (res->start - size) &~ (align - 1); in expand_ioc_area()
1424 len = res->end - start + 1; in expand_ioc_area()
1430 start = res->start; in expand_ioc_area()
1431 len = ((size + res->end + align) &~ (align - 1)) - start; in expand_ioc_area()
1437 return -EBUSY; in expand_ioc_area()
1456 parent = ioc->mmio_region; in ccio_allocate_resource()
1457 if (parent->parent && in ccio_allocate_resource()
1461 if ((parent + 1)->parent && in ccio_allocate_resource()
1467 __raw_writel(((parent->start)>>16) | 0xffff0000, in ccio_allocate_resource()
1468 &ioc->ioc_regs->io_io_low); in ccio_allocate_resource()
1469 __raw_writel(((parent->end)>>16) | 0xffff0000, in ccio_allocate_resource()
1470 &ioc->ioc_regs->io_io_high); in ccio_allocate_resource()
1473 __raw_writel(((parent->start)>>16) | 0xffff0000, in ccio_allocate_resource()
1474 &ioc->ioc_regs->io_io_low_hv); in ccio_allocate_resource()
1475 __raw_writel(((parent->end)>>16) | 0xffff0000, in ccio_allocate_resource()
1476 &ioc->ioc_regs->io_io_high_hv); in ccio_allocate_resource()
1478 return -EBUSY; in ccio_allocate_resource()
1493 } else if ((ioc->mmio_region->start <= res->start) && in ccio_request_resource()
1494 (res->end <= ioc->mmio_region->end)) { in ccio_request_resource()
1495 parent = ioc->mmio_region; in ccio_request_resource()
1496 } else if (((ioc->mmio_region + 1)->start <= res->start) && in ccio_request_resource()
1497 (res->end <= (ioc->mmio_region + 1)->end)) { in ccio_request_resource()
1498 parent = ioc->mmio_region + 1; in ccio_request_resource()
1500 return -EBUSY; in ccio_request_resource()
1504 * firmware assigned them. e.g. children of hppb.c (e.g. K-class) in ccio_request_resource()
1512 * ccio_probe - Determine if ccio should claim this device.
1528 return -ENOMEM; in ccio_probe()
1531 ioc->name = dev->id.hversion == U2_IOA_RUNWAY ? "U2" : "UTurn"; in ccio_probe()
1533 printk(KERN_INFO "Found %s at 0x%lx\n", ioc->name, in ccio_probe()
1534 (unsigned long)dev->hpa.start); in ccio_probe()
1537 ioc_p = &(*ioc_p)->next; in ccio_probe()
1541 ioc->hw_path = dev->hw_path; in ccio_probe()
1542 ioc->ioc_regs = ioremap(dev->hpa.start, 4096); in ccio_probe()
1543 if (!ioc->ioc_regs) { in ccio_probe()
1545 return -ENOMEM; in ccio_probe()
1549 iounmap(ioc->ioc_regs); in ccio_probe()
1551 return -ENOMEM; in ccio_probe()
1559 hba->iommu = ioc; in ccio_probe()
1560 dev->dev.platform_data = hba; in ccio_probe()
1566 proc_create_single(MODULE_NAME"-bitmap", 0, proc_runway_root, in ccio_probe()
1575 * ccio_init - ccio initialization procedure.