29 					       * OTP Bank0 Word0
32 					       * of two consecutive OTP words.
253 	 * ipg_clk. OTP writes will work at maximum bus frequencies as long  in imx_ocotp_set_imx6_timing()
256 	 * Note: there are minimum timings required to ensure an OTP fuse burns  in imx_ocotp_set_imx6_timing()
265 	 * - Minimum STROBE_READ i.e. the time to wait post OTP fuse burn before  in imx_ocotp_set_imx6_timing()
275 	 *   value will mess up a re-load of the shadow registers post OTP  in imx_ocotp_set_imx6_timing()
328 	/* allow only writing one complete OTP word at a time */  in imx_ocotp_write()
366 		 * In banked/i.MX7 mode the OTP register bank goes into waddr  in imx_ocotp_write()
376 		 * OTP write/read address specifies one of 128 word address  in imx_ocotp_write()
392 	 * protect programming same OTP bit twice, before program OCOTP will  in imx_ocotp_write()
393 	 * automatically read fuse value in OTP and use read value to mask  in imx_ocotp_write()
395 	 * a 32-bit word in the OTP per the address in HW_OCOTP_CTRL[ADDR]. Bit  in imx_ocotp_write()
396 	 * fields with 1's will result in that OTP bit being programmed. Bit  in imx_ocotp_write()
404 	 * the OTP serially. During the write operation, HW_OCOTP_DATA cannot be  in imx_ocotp_write()
446 	 * protected or locked region will result in no OTP access and no  in imx_ocotp_write()
464 	 * OTP during writes, all OTP operations following a write must be  in imx_ocotp_write()