2260 	ctrl->ctrl_config &= ~NVME_CC_SHN_MASK;  in nvme_disable_ctrl()
2261 	ctrl->ctrl_config &= ~NVME_CC_ENABLE;  in nvme_disable_ctrl()
2263 	ret = ctrl->ops->reg_write32(ctrl, NVME_REG_CC, ctrl->ctrl_config);  in nvme_disable_ctrl()
2295 		ctrl->ctrl_config = NVME_CC_CSS_CSI;  in nvme_enable_ctrl()
2297 		ctrl->ctrl_config = NVME_CC_CSS_NVM;  in nvme_enable_ctrl()
2310 			ctrl->ctrl_config |= NVME_CC_CRIME;  in nvme_enable_ctrl()
2319 	ctrl->ctrl_config |= (NVME_CTRL_PAGE_SHIFT - 12) << NVME_CC_MPS_SHIFT;  in nvme_enable_ctrl()
2320 	ctrl->ctrl_config |= NVME_CC_AMS_RR | NVME_CC_SHN_NONE;  in nvme_enable_ctrl()
2321 	ctrl->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;  in nvme_enable_ctrl()
2322 	ret = ctrl->ops->reg_write32(ctrl, NVME_REG_CC, ctrl->ctrl_config);  in nvme_enable_ctrl()
2327 	ret = ctrl->ops->reg_read32(ctrl, NVME_REG_CC, &ctrl->ctrl_config);  in nvme_enable_ctrl()
2331 	ctrl->ctrl_config |= NVME_CC_ENABLE;  in nvme_enable_ctrl()
2332 	ret = ctrl->ops->reg_write32(ctrl, NVME_REG_CC, ctrl->ctrl_config);  in nvme_enable_ctrl()
2345 	ctrl->ctrl_config &= ~NVME_CC_SHN_MASK;  in nvme_shutdown_ctrl()
2346 	ctrl->ctrl_config |= NVME_CC_SHN_NORMAL;  in nvme_shutdown_ctrl()
2348 	ret = ctrl->ops->reg_write32(ctrl, NVME_REG_CC, ctrl->ctrl_config);  in nvme_shutdown_ctrl()
4665 	return ((ctrl->ctrl_config & NVME_CC_ENABLE) && (csts & NVME_CSTS_PP));  in nvme_ctrl_pp_status()