Lines Matching refs:bar_entry
42 #define MAX_DIRECT_MW ARRAY_SIZE(((struct ntb_ctrl_regs *)(0))->bar_entry)
227 ctl_val = ioread32(&ctl->bar_entry[bar].ctl); in switchtec_ntb_mw_clr_direct()
229 iowrite32(ctl_val, &ctl->bar_entry[bar].ctl); in switchtec_ntb_mw_clr_direct()
230 iowrite32(0, &ctl->bar_entry[bar].win_size); in switchtec_ntb_mw_clr_direct()
232 iowrite64(sndev->self_partition, &ctl->bar_entry[bar].xlate_addr); in switchtec_ntb_mw_clr_direct()
250 ctl_val = ioread32(&ctl->bar_entry[bar].ctl); in switchtec_ntb_mw_set_direct()
253 iowrite32(ctl_val, &ctl->bar_entry[bar].ctl); in switchtec_ntb_mw_set_direct()
255 &ctl->bar_entry[bar].win_size); in switchtec_ntb_mw_set_direct()
258 &ctl->bar_entry[bar].xlate_addr); in switchtec_ntb_mw_set_direct()
924 ctl_val = ioread32(&ctl->bar_entry[peer_bar].ctl); in config_rsvd_lut_win()
929 iowrite32(ctl_val, &ctl->bar_entry[peer_bar].ctl); in config_rsvd_lut_win()
1035 ctl_val = ioread32(&ctl->bar_entry[bar].ctl); in crosslink_setup_mws()
1038 iowrite32(ctl_val, &ctl->bar_entry[bar].ctl); in crosslink_setup_mws()
1040 &ctl->bar_entry[bar].win_size); in crosslink_setup_mws()
1043 &ctl->bar_entry[bar].xlate_addr); in crosslink_setup_mws()
1189 for (i = 0; i < ARRAY_SIZE(ctrl->bar_entry); i++) { in map_bars()
1190 u32 r = ioread32(&ctrl->bar_entry[i].ctl); in map_bars()