1 // SPDX-License-Identifier: GPL-2.0-only
4  * Copyright (c) 2021-2022, Intel Corporation.
7  *  Haijun Liu <haijun.liu@mediatek.com>
8  *  Moises Veleta <moises.veleta@intel.com>
9  *  Sreehari Kancharla <sreehari.kancharla@intel.com>
12  *  Amir Hanania <amir.hanania@intel.com>
13  *  Chiranjeevi Rapolu <chiranjeevi.rapolu@intel.com>
14  *  Ricardo Martinez <ricardo.martinez@linux.intel.com>
20 #include <linux/io-64-nonatomic-lo-hi.h>
73 	int i, offset;  in t7xx_pcie_mac_atr_tables_dis()  local
76 		offset = ATR_PORT_OFFSET * port + ATR_TABLE_OFFSET * i;  in t7xx_pcie_mac_atr_tables_dis()
77 		reg = pbase + ATR_PCIE_WIN0_T0_ATR_PARAM_SRC_ADDR + offset;  in t7xx_pcie_mac_atr_tables_dis()
84 	struct device *dev = &t7xx_dev->pdev->dev;  in t7xx_pcie_mac_atr_cfg()
86 	int atr_size, pos, offset;  in t7xx_pcie_mac_atr_cfg()  local
90 	if (cfg->transparent) {  in t7xx_pcie_mac_atr_cfg()
94 		if (cfg->src_addr & (cfg->size - 1)) {  in t7xx_pcie_mac_atr_cfg()
96 			return -EINVAL;  in t7xx_pcie_mac_atr_cfg()
99 		if (cfg->trsl_addr & (cfg->size - 1)) {  in t7xx_pcie_mac_atr_cfg()
101 				cfg->trsl_addr, cfg->size - 1);  in t7xx_pcie_mac_atr_cfg()
102 			return -EINVAL;  in t7xx_pcie_mac_atr_cfg()
105 		pos = __ffs64(cfg->size);  in t7xx_pcie_mac_atr_cfg()
108 		atr_size = pos - 1;  in t7xx_pcie_mac_atr_cfg()
111 	offset = ATR_PORT_OFFSET * cfg->port + ATR_TABLE_OFFSET * cfg->table;  in t7xx_pcie_mac_atr_cfg()
113 	reg = pbase + ATR_PCIE_WIN0_T0_TRSL_ADDR + offset;  in t7xx_pcie_mac_atr_cfg()
114 	value = cfg->trsl_addr & ATR_PCIE_WIN0_ADDR_ALGMT;  in t7xx_pcie_mac_atr_cfg()
117 	reg = pbase + ATR_PCIE_WIN0_T0_TRSL_PARAM + offset;  in t7xx_pcie_mac_atr_cfg()
118 	iowrite32(cfg->trsl_id, reg);  in t7xx_pcie_mac_atr_cfg()
120 	reg = pbase + ATR_PCIE_WIN0_T0_ATR_PARAM_SRC_ADDR + offset;  in t7xx_pcie_mac_atr_cfg()
121 	value = (cfg->src_addr & ATR_PCIE_WIN0_ADDR_ALGMT) | (atr_size << 1) | BIT(0);  in t7xx_pcie_mac_atr_cfg()
130  * t7xx_pcie_mac_atr_init() - Initialize address translation.
146 	cfg.src_addr = pci_resource_start(t7xx_dev->pdev, T7XX_PCIE_REG_BAR);  in t7xx_pcie_mac_atr_init()
155 	t7xx_dev->base_addr.pcie_dev_reg_trsl_addr = T7XX_PCIE_REG_TRSL_ADDR_CHIP;  in t7xx_pcie_mac_atr_init()
172  * t7xx_pcie_mac_enable_disable_int() - Enable/disable interrupts.
203  * t7xx_pcie_mac_clear_set_int() - Clear/set interrupt by type.
236  * t7xx_pcie_mac_clear_int_status() - Clear interrupt status by type.
251  * t7xx_pcie_set_mac_msix_cfg() - Write MSIX control configuration.
259 	u32 val = ffs(irq_count) * 2 - 1;  in t7xx_pcie_set_mac_msix_cfg()