Lines Matching +full:1 +full:khz

58 MODULE_PARM_DESC(cw1200_power_mode, "WSM power mode.  0 == active, 1 == doze, 2 == quiescent (defau…
69 RATETAB_ENT(20, 1, 0),
120 CHAN2G(1, 2412, 0),
165 (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT) |
167 .ht_supported = 1,
185 (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT) |
187 .ht_supported = 1,
199 1 * HZ, /* VO */
237 static int cw1200_ba_rx_tids = -1;
238 static int cw1200_ba_tx_tids = -1;
265 priv->hw_type = -1; in cw1200_init_common()
269 if (cw1200_ba_rx_tids != -1) in cw1200_init_common()
273 if (cw1200_ba_tx_tids != -1) in cw1200_init_common()
302 priv->rts_threshold = -1; in cw1200_init_common()
350 sema_init(&priv->scan.lock, 1); in cw1200_init_common()
394 cw1200_queue_deinit(&priv->tx_queue[i - 1]); in cw1200_init_common()
408 priv->wsm_cmd.done = 1; in cw1200_init_common()
482 /* Clock is in KHz */
486 case 0x32C8: /* 13000 KHz */ in cw1200_dpll_from_clk()
488 case 0x3E80: /* 16000 KHz */ in cw1200_dpll_from_clk()
490 case 0x41A0: /* 16800 KHz */ in cw1200_dpll_from_clk()
492 case 0x4B00: /* 19200 KHz */ in cw1200_dpll_from_clk()
494 case 0x5DC0: /* 24000 KHz */ in cw1200_dpll_from_clk()
496 case 0x6590: /* 26000 KHz */ in cw1200_dpll_from_clk()
498 case 0x8340: /* 33600 KHz */ in cw1200_dpll_from_clk()
500 case 0x9600: /* 38400 KHz */ in cw1200_dpll_from_clk()
502 case 0x9C40: /* 40000 KHz */ in cw1200_dpll_from_clk()
504 case 0xBB80: /* 48000 KHz */ in cw1200_dpll_from_clk()
506 case 0xCB20: /* 52000 KHz */ in cw1200_dpll_from_clk()
509 pr_err("Unknown Refclk freq (0x%04x), using 26000KHz\n", in cw1200_dpll_from_clk()